| Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * File: arch/blackfin/mach-bf527/dma.c |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: |
| 7 | * Description: This file contains the simple DMA Implementation for Blackfin |
| 8 | * |
| 9 | * Modified: |
| 10 | * Copyright 2004-2007 Analog Devices Inc. |
| 11 | * |
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify |
| 15 | * it under the terms of the GNU General Public License as published by |
| 16 | * the Free Software Foundation; either version 2 of the License, or |
| 17 | * (at your option) any later version. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, see the file COPYING, or write |
| 26 | * to the Free Software Foundation, Inc., |
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 28 | */ |
| 29 | #include <asm/blackfin.h> |
| 30 | #include <asm/dma.h> |
| 31 | |
| 32 | struct dma_register *base_addr[MAX_BLACKFIN_DMA_CHANNEL] = { |
| 33 | (struct dma_register *) DMA0_NEXT_DESC_PTR, |
| 34 | (struct dma_register *) DMA1_NEXT_DESC_PTR, |
| 35 | (struct dma_register *) DMA2_NEXT_DESC_PTR, |
| 36 | (struct dma_register *) DMA3_NEXT_DESC_PTR, |
| 37 | (struct dma_register *) DMA4_NEXT_DESC_PTR, |
| 38 | (struct dma_register *) DMA5_NEXT_DESC_PTR, |
| 39 | (struct dma_register *) DMA6_NEXT_DESC_PTR, |
| 40 | (struct dma_register *) DMA7_NEXT_DESC_PTR, |
| 41 | (struct dma_register *) DMA8_NEXT_DESC_PTR, |
| 42 | (struct dma_register *) DMA9_NEXT_DESC_PTR, |
| 43 | (struct dma_register *) DMA10_NEXT_DESC_PTR, |
| 44 | (struct dma_register *) DMA11_NEXT_DESC_PTR, |
| 45 | (struct dma_register *) MDMA_D0_NEXT_DESC_PTR, |
| 46 | (struct dma_register *) MDMA_S0_NEXT_DESC_PTR, |
| 47 | (struct dma_register *) MDMA_D1_NEXT_DESC_PTR, |
| 48 | (struct dma_register *) MDMA_S1_NEXT_DESC_PTR, |
| 49 | }; |
| 50 | |
| 51 | int channel2irq(unsigned int channel) |
| 52 | { |
| 53 | int ret_irq = -1; |
| 54 | |
| 55 | switch (channel) { |
| 56 | case CH_PPI: |
| 57 | ret_irq = IRQ_PPI; |
| 58 | break; |
| 59 | |
| 60 | case CH_EMAC_RX: |
| 61 | ret_irq = IRQ_MAC_RX; |
| 62 | break; |
| 63 | |
| 64 | case CH_EMAC_TX: |
| 65 | ret_irq = IRQ_MAC_TX; |
| 66 | break; |
| 67 | |
| 68 | case CH_UART1_RX: |
| 69 | ret_irq = IRQ_UART1_RX; |
| 70 | break; |
| 71 | |
| 72 | case CH_UART1_TX: |
| 73 | ret_irq = IRQ_UART1_TX; |
| 74 | break; |
| 75 | |
| 76 | case CH_SPORT0_RX: |
| 77 | ret_irq = IRQ_SPORT0_RX; |
| 78 | break; |
| 79 | |
| 80 | case CH_SPORT0_TX: |
| 81 | ret_irq = IRQ_SPORT0_TX; |
| 82 | break; |
| 83 | |
| 84 | case CH_SPORT1_RX: |
| 85 | ret_irq = IRQ_SPORT1_RX; |
| 86 | break; |
| 87 | |
| 88 | case CH_SPORT1_TX: |
| 89 | ret_irq = IRQ_SPORT1_TX; |
| 90 | break; |
| 91 | |
| 92 | case CH_SPI: |
| 93 | ret_irq = IRQ_SPI; |
| 94 | break; |
| 95 | |
| 96 | case CH_UART0_RX: |
| 97 | ret_irq = IRQ_UART0_RX; |
| 98 | break; |
| 99 | |
| 100 | case CH_UART0_TX: |
| 101 | ret_irq = IRQ_UART0_TX; |
| 102 | break; |
| 103 | |
| 104 | case CH_MEM_STREAM0_SRC: |
| 105 | case CH_MEM_STREAM0_DEST: |
| 106 | ret_irq = IRQ_MEM_DMA0; |
| 107 | break; |
| 108 | |
| 109 | case CH_MEM_STREAM1_SRC: |
| 110 | case CH_MEM_STREAM1_DEST: |
| 111 | ret_irq = IRQ_MEM_DMA1; |
| 112 | break; |
| 113 | } |
| 114 | return ret_irq; |
| 115 | } |