Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
| 2 | * File: arch/blackfin/mach-common/ints-priority-sc.c |
| 3 | * Based on: |
| 4 | * Author: |
| 5 | * |
| 6 | * Created: ? |
Simon Arlott | d2d50aa | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 7 | * Description: Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 8 | * |
| 9 | * Modified: |
| 10 | * 1996 Roman Zippel |
| 11 | * 1999 D. Jeff Dionne <jeff@uclinux.org> |
| 12 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> |
| 13 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> |
| 14 | * 2003 Metrowerks/Motorola |
| 15 | * 2003 Bas Vermeulen <bas@buyways.nl> |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 16 | * Copyright 2004-2007 Analog Devices Inc. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 17 | * |
| 18 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2 of the License, or |
| 23 | * (at your option) any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; if not, see the file COPYING, or write |
| 32 | * to the Free Software Foundation, Inc., |
| 33 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 34 | */ |
| 35 | |
| 36 | #include <linux/module.h> |
| 37 | #include <linux/kernel_stat.h> |
| 38 | #include <linux/seq_file.h> |
| 39 | #include <linux/irq.h> |
| 40 | #ifdef CONFIG_KGDB |
| 41 | #include <linux/kgdb.h> |
| 42 | #endif |
| 43 | #include <asm/traps.h> |
| 44 | #include <asm/blackfin.h> |
| 45 | #include <asm/gpio.h> |
| 46 | #include <asm/irq_handler.h> |
| 47 | |
| 48 | #ifdef BF537_FAMILY |
| 49 | # define BF537_GENERIC_ERROR_INT_DEMUX |
| 50 | #else |
| 51 | # undef BF537_GENERIC_ERROR_INT_DEMUX |
| 52 | #endif |
| 53 | |
| 54 | /* |
| 55 | * NOTES: |
| 56 | * - we have separated the physical Hardware interrupt from the |
| 57 | * levels that the LINUX kernel sees (see the description in irq.h) |
| 58 | * - |
| 59 | */ |
| 60 | |
| 61 | unsigned long irq_flags = 0; |
| 62 | |
| 63 | /* The number of spurious interrupts */ |
| 64 | atomic_t num_spurious; |
| 65 | |
| 66 | struct ivgx { |
| 67 | /* irq number for request_irq, available in mach-bf533/irq.h */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 68 | unsigned int irqno; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 69 | /* corresponding bit in the SIC_ISR register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 70 | unsigned int isrflag; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 71 | } ivg_table[NR_PERI_INTS]; |
| 72 | |
| 73 | struct ivg_slice { |
| 74 | /* position of first irq in ivg_table for given ivg */ |
| 75 | struct ivgx *ifirst; |
| 76 | struct ivgx *istop; |
| 77 | } ivg7_13[IVG13 - IVG7 + 1]; |
| 78 | |
| 79 | static void search_IAR(void); |
| 80 | |
| 81 | /* |
| 82 | * Search SIC_IAR and fill tables with the irqvalues |
| 83 | * and their positions in the SIC_ISR register. |
| 84 | */ |
| 85 | static void __init search_IAR(void) |
| 86 | { |
| 87 | unsigned ivg, irq_pos = 0; |
| 88 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { |
| 89 | int irqn; |
| 90 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 91 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 92 | |
| 93 | for (irqn = 0; irqn < NR_PERI_INTS; irqn++) { |
| 94 | int iar_shift = (irqn & 7) * 4; |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 95 | if (ivg == |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 96 | (0xf & |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 97 | #ifndef CONFIG_BF52x |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 98 | bfin_read32((unsigned long *)SIC_IAR0 + |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 99 | (irqn >> 3)) >> iar_shift)) { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 100 | #else |
| 101 | bfin_read32((unsigned long *)SIC_IAR0 + |
| 102 | ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) { |
| 103 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 104 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 105 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 106 | ivg7_13[ivg].istop++; |
| 107 | irq_pos++; |
| 108 | } |
| 109 | } |
| 110 | } |
| 111 | } |
| 112 | |
| 113 | /* |
| 114 | * This is for BF533 internal IRQs |
| 115 | */ |
| 116 | |
| 117 | static void ack_noop(unsigned int irq) |
| 118 | { |
| 119 | /* Dummy function. */ |
| 120 | } |
| 121 | |
| 122 | static void bfin_core_mask_irq(unsigned int irq) |
| 123 | { |
| 124 | irq_flags &= ~(1 << irq); |
| 125 | if (!irqs_disabled()) |
| 126 | local_irq_enable(); |
| 127 | } |
| 128 | |
| 129 | static void bfin_core_unmask_irq(unsigned int irq) |
| 130 | { |
| 131 | irq_flags |= 1 << irq; |
| 132 | /* |
| 133 | * If interrupts are enabled, IMASK must contain the same value |
| 134 | * as irq_flags. Make sure that invariant holds. If interrupts |
| 135 | * are currently disabled we need not do anything; one of the |
| 136 | * callers will take care of setting IMASK to the proper value |
| 137 | * when reenabling interrupts. |
| 138 | * local_irq_enable just does "STI irq_flags", so it's exactly |
| 139 | * what we need. |
| 140 | */ |
| 141 | if (!irqs_disabled()) |
| 142 | local_irq_enable(); |
| 143 | return; |
| 144 | } |
| 145 | |
| 146 | static void bfin_internal_mask_irq(unsigned int irq) |
| 147 | { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 148 | #ifdef CONFIG_BF53x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 149 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
| 150 | ~(1 << (irq - (IRQ_CORETMR + 1)))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 151 | #else |
| 152 | unsigned mask_bank, mask_bit; |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 153 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
| 154 | mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 155 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
| 156 | ~(1 << mask_bit)); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 157 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 158 | SSYNC(); |
| 159 | } |
| 160 | |
| 161 | static void bfin_internal_unmask_irq(unsigned int irq) |
| 162 | { |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 163 | #ifdef CONFIG_BF53x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 164 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
| 165 | (1 << (irq - (IRQ_CORETMR + 1)))); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 166 | #else |
| 167 | unsigned mask_bank, mask_bit; |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 168 | mask_bank = (irq - (IRQ_CORETMR + 1)) / 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 169 | mask_bit = (irq - (IRQ_CORETMR + 1)) % 32; |
| 170 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
| 171 | (1 << mask_bit)); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 172 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 173 | SSYNC(); |
| 174 | } |
| 175 | |
| 176 | static struct irq_chip bfin_core_irqchip = { |
| 177 | .ack = ack_noop, |
| 178 | .mask = bfin_core_mask_irq, |
| 179 | .unmask = bfin_core_unmask_irq, |
| 180 | }; |
| 181 | |
| 182 | static struct irq_chip bfin_internal_irqchip = { |
| 183 | .ack = ack_noop, |
| 184 | .mask = bfin_internal_mask_irq, |
| 185 | .unmask = bfin_internal_unmask_irq, |
| 186 | }; |
| 187 | |
| 188 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 189 | static int error_int_mask; |
| 190 | |
| 191 | static void bfin_generic_error_ack_irq(unsigned int irq) |
| 192 | { |
| 193 | |
| 194 | } |
| 195 | |
| 196 | static void bfin_generic_error_mask_irq(unsigned int irq) |
| 197 | { |
| 198 | error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR)); |
| 199 | |
| 200 | if (!error_int_mask) { |
| 201 | local_irq_disable(); |
| 202 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
| 203 | ~(1 << |
| 204 | (IRQ_GENERIC_ERROR - |
| 205 | (IRQ_CORETMR + 1)))); |
| 206 | SSYNC(); |
| 207 | local_irq_enable(); |
| 208 | } |
| 209 | } |
| 210 | |
| 211 | static void bfin_generic_error_unmask_irq(unsigned int irq) |
| 212 | { |
| 213 | local_irq_disable(); |
| 214 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 << |
| 215 | (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1))); |
| 216 | SSYNC(); |
| 217 | local_irq_enable(); |
| 218 | |
| 219 | error_int_mask |= 1L << (irq - IRQ_PPI_ERROR); |
| 220 | } |
| 221 | |
| 222 | static struct irq_chip bfin_generic_error_irqchip = { |
| 223 | .ack = bfin_generic_error_ack_irq, |
| 224 | .mask = bfin_generic_error_mask_irq, |
| 225 | .unmask = bfin_generic_error_unmask_irq, |
| 226 | }; |
| 227 | |
| 228 | static void bfin_demux_error_irq(unsigned int int_err_irq, |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 229 | struct irq_desc *intb_desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 230 | { |
| 231 | int irq = 0; |
| 232 | |
| 233 | SSYNC(); |
| 234 | |
| 235 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 236 | if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK) |
| 237 | irq = IRQ_MAC_ERROR; |
| 238 | else |
| 239 | #endif |
| 240 | if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK) |
| 241 | irq = IRQ_SPORT0_ERROR; |
| 242 | else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK) |
| 243 | irq = IRQ_SPORT1_ERROR; |
| 244 | else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK) |
| 245 | irq = IRQ_PPI_ERROR; |
| 246 | else if (bfin_read_CAN_GIF() & CAN_ERR_MASK) |
| 247 | irq = IRQ_CAN_ERROR; |
| 248 | else if (bfin_read_SPI_STAT() & SPI_ERR_MASK) |
| 249 | irq = IRQ_SPI_ERROR; |
| 250 | else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) && |
| 251 | (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0)) |
| 252 | irq = IRQ_UART0_ERROR; |
| 253 | else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) && |
| 254 | (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0)) |
| 255 | irq = IRQ_UART1_ERROR; |
| 256 | |
| 257 | if (irq) { |
| 258 | if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) { |
| 259 | struct irq_desc *desc = irq_desc + irq; |
| 260 | desc->handle_irq(irq, desc); |
| 261 | } else { |
| 262 | |
| 263 | switch (irq) { |
| 264 | case IRQ_PPI_ERROR: |
| 265 | bfin_write_PPI_STATUS(PPI_ERR_MASK); |
| 266 | break; |
| 267 | #if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) |
| 268 | case IRQ_MAC_ERROR: |
| 269 | bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK); |
| 270 | break; |
| 271 | #endif |
| 272 | case IRQ_SPORT0_ERROR: |
| 273 | bfin_write_SPORT0_STAT(SPORT_ERR_MASK); |
| 274 | break; |
| 275 | |
| 276 | case IRQ_SPORT1_ERROR: |
| 277 | bfin_write_SPORT1_STAT(SPORT_ERR_MASK); |
| 278 | break; |
| 279 | |
| 280 | case IRQ_CAN_ERROR: |
| 281 | bfin_write_CAN_GIS(CAN_ERR_MASK); |
| 282 | break; |
| 283 | |
| 284 | case IRQ_SPI_ERROR: |
| 285 | bfin_write_SPI_STAT(SPI_ERR_MASK); |
| 286 | break; |
| 287 | |
| 288 | default: |
| 289 | break; |
| 290 | } |
| 291 | |
| 292 | pr_debug("IRQ %d:" |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 293 | " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n", |
| 294 | irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 295 | } |
| 296 | } else |
| 297 | printk(KERN_ERR |
| 298 | "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR" |
| 299 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n", |
| 300 | __FUNCTION__, __FILE__, __LINE__); |
| 301 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 302 | } |
| 303 | #endif /* BF537_GENERIC_ERROR_INT_DEMUX */ |
| 304 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 305 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && !defined(CONFIG_BF54x) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 306 | |
| 307 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 308 | static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 309 | |
| 310 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 311 | { |
| 312 | u16 gpionr = irq - IRQ_PF0; |
| 313 | |
| 314 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { |
| 315 | set_gpio_data(gpionr, 0); |
| 316 | SSYNC(); |
| 317 | } |
| 318 | } |
| 319 | |
| 320 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 321 | { |
| 322 | u16 gpionr = irq - IRQ_PF0; |
| 323 | |
| 324 | if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) { |
| 325 | set_gpio_data(gpionr, 0); |
| 326 | SSYNC(); |
| 327 | } |
| 328 | |
| 329 | set_gpio_maska(gpionr, 0); |
| 330 | SSYNC(); |
| 331 | } |
| 332 | |
| 333 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 334 | { |
| 335 | set_gpio_maska(irq - IRQ_PF0, 0); |
| 336 | SSYNC(); |
| 337 | } |
| 338 | |
| 339 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 340 | { |
| 341 | set_gpio_maska(irq - IRQ_PF0, 1); |
| 342 | SSYNC(); |
| 343 | } |
| 344 | |
| 345 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 346 | { |
| 347 | unsigned int ret; |
| 348 | u16 gpionr = irq - IRQ_PF0; |
| 349 | |
| 350 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
Michael Hennerich | 6782ea9 | 2007-07-24 15:16:59 +0800 | [diff] [blame] | 351 | ret = gpio_request(gpionr, "IRQ"); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 352 | if (ret) |
| 353 | return ret; |
| 354 | } |
| 355 | |
| 356 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 357 | bfin_gpio_unmask_irq(irq); |
| 358 | |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 363 | { |
| 364 | bfin_gpio_mask_irq(irq); |
| 365 | gpio_free(irq - IRQ_PF0); |
| 366 | gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0); |
| 367 | } |
| 368 | |
| 369 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 370 | { |
| 371 | |
| 372 | unsigned int ret; |
| 373 | u16 gpionr = irq - IRQ_PF0; |
| 374 | |
| 375 | if (type == IRQ_TYPE_PROBE) { |
| 376 | /* only probe unenabled GPIO interrupt lines */ |
| 377 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) |
| 378 | return 0; |
| 379 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 380 | } |
| 381 | |
| 382 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 383 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 384 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
Michael Hennerich | 6782ea9 | 2007-07-24 15:16:59 +0800 | [diff] [blame] | 385 | ret = gpio_request(gpionr, "IRQ"); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 386 | if (ret) |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 391 | } else { |
| 392 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 393 | return 0; |
| 394 | } |
| 395 | |
| 396 | set_gpio_dir(gpionr, 0); |
| 397 | set_gpio_inen(gpionr, 1); |
| 398 | |
| 399 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 400 | gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 401 | set_gpio_edge(gpionr, 1); |
| 402 | } else { |
| 403 | set_gpio_edge(gpionr, 0); |
| 404 | gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 405 | } |
| 406 | |
| 407 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 408 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 409 | set_gpio_both(gpionr, 1); |
| 410 | else |
| 411 | set_gpio_both(gpionr, 0); |
| 412 | |
| 413 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
| 414 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ |
| 415 | else |
| 416 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ |
| 417 | |
| 418 | SSYNC(); |
| 419 | |
| 420 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 421 | set_irq_handler(irq, handle_edge_irq); |
| 422 | else |
| 423 | set_irq_handler(irq, handle_level_irq); |
| 424 | |
| 425 | return 0; |
| 426 | } |
| 427 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 428 | static struct irq_chip bfin_gpio_irqchip = { |
| 429 | .ack = bfin_gpio_ack_irq, |
| 430 | .mask = bfin_gpio_mask_irq, |
| 431 | .mask_ack = bfin_gpio_mask_ack_irq, |
| 432 | .unmask = bfin_gpio_unmask_irq, |
| 433 | .set_type = bfin_gpio_irq_type, |
| 434 | .startup = bfin_gpio_irq_startup, |
| 435 | .shutdown = bfin_gpio_irq_shutdown |
| 436 | }; |
| 437 | |
| 438 | static void bfin_demux_gpio_irq(unsigned int intb_irq, |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 439 | struct irq_desc *intb_desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 440 | { |
| 441 | u16 i; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 442 | struct irq_desc *desc; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 443 | |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 444 | for (i = 0; i < MAX_BLACKFIN_GPIOS; i += 16) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 445 | int irq = IRQ_PF0 + i; |
| 446 | int flag_d = get_gpiop_data(i); |
| 447 | int mask = |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 448 | flag_d & (gpio_enabled[gpio_bank(i)] & get_gpiop_maska(i)); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 449 | |
| 450 | while (mask) { |
| 451 | if (mask & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 452 | desc = irq_desc + irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 453 | desc->handle_irq(irq, desc); |
| 454 | } |
| 455 | irq++; |
| 456 | mask >>= 1; |
| 457 | } |
| 458 | } |
| 459 | } |
| 460 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 461 | #else /* CONFIG_IRQCHIP_DEMUX_GPIO */ |
| 462 | |
| 463 | #define NR_PINT_SYS_IRQS 4 |
| 464 | #define NR_PINT_BITS 32 |
| 465 | #define NR_PINTS 160 |
| 466 | #define IRQ_NOT_AVAIL 0xFF |
| 467 | |
| 468 | #define PINT_2_BANK(x) ((x) >> 5) |
| 469 | #define PINT_2_BIT(x) ((x) & 0x1F) |
| 470 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) |
| 471 | |
| 472 | static unsigned char irq2pint_lut[NR_PINTS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 473 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 474 | |
| 475 | struct pin_int_t { |
| 476 | unsigned int mask_set; |
| 477 | unsigned int mask_clear; |
| 478 | unsigned int request; |
| 479 | unsigned int assign; |
| 480 | unsigned int edge_set; |
| 481 | unsigned int edge_clear; |
| 482 | unsigned int invert_set; |
| 483 | unsigned int invert_clear; |
| 484 | unsigned int pinstate; |
| 485 | unsigned int latch; |
| 486 | }; |
| 487 | |
| 488 | static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = { |
| 489 | (struct pin_int_t *)PINT0_MASK_SET, |
| 490 | (struct pin_int_t *)PINT1_MASK_SET, |
| 491 | (struct pin_int_t *)PINT2_MASK_SET, |
| 492 | (struct pin_int_t *)PINT3_MASK_SET, |
| 493 | }; |
| 494 | |
| 495 | unsigned short get_irq_base(u8 bank, u8 bmap) |
| 496 | { |
| 497 | |
| 498 | u16 irq_base; |
| 499 | |
| 500 | if (bank < 2) { /*PA-PB */ |
| 501 | irq_base = IRQ_PA0 + bmap * 16; |
| 502 | } else { /*PC-PJ */ |
| 503 | irq_base = IRQ_PC0 + bmap * 16; |
| 504 | } |
| 505 | |
| 506 | return irq_base; |
| 507 | |
| 508 | } |
| 509 | |
| 510 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 511 | void init_pint_lut(void) |
| 512 | { |
| 513 | u16 bank, bit, irq_base, bit_pos; |
| 514 | u32 pint_assign; |
| 515 | u8 bmap; |
| 516 | |
| 517 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); |
| 518 | |
| 519 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 520 | |
| 521 | pint_assign = pint[bank]->assign; |
| 522 | |
| 523 | for (bit = 0; bit < NR_PINT_BITS; bit++) { |
| 524 | |
| 525 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; |
| 526 | |
| 527 | irq_base = get_irq_base(bank, bmap); |
| 528 | |
| 529 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); |
| 530 | bit_pos = bit + bank * NR_PINT_BITS; |
| 531 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 532 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 533 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
| 534 | |
| 535 | } |
| 536 | |
| 537 | } |
| 538 | |
| 539 | } |
| 540 | |
| 541 | static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)]; |
| 542 | |
| 543 | static void bfin_gpio_ack_irq(unsigned int irq) |
| 544 | { |
| 545 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 546 | |
| 547 | pint[PINT_2_BANK(pint_val)]->request = PINT_BIT(pint_val); |
| 548 | SSYNC(); |
| 549 | } |
| 550 | |
| 551 | static void bfin_gpio_mask_ack_irq(unsigned int irq) |
| 552 | { |
| 553 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 554 | u32 pintbit = PINT_BIT(pint_val); |
| 555 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 556 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 557 | pint[bank]->request = pintbit; |
| 558 | pint[bank]->mask_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 559 | SSYNC(); |
| 560 | } |
| 561 | |
| 562 | static void bfin_gpio_mask_irq(unsigned int irq) |
| 563 | { |
| 564 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 565 | |
| 566 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
| 567 | SSYNC(); |
| 568 | } |
| 569 | |
| 570 | static void bfin_gpio_unmask_irq(unsigned int irq) |
| 571 | { |
| 572 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 573 | u32 pintbit = PINT_BIT(pint_val); |
| 574 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 575 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 576 | pint[bank]->request = pintbit; |
| 577 | pint[bank]->mask_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 578 | SSYNC(); |
| 579 | } |
| 580 | |
| 581 | static unsigned int bfin_gpio_irq_startup(unsigned int irq) |
| 582 | { |
| 583 | unsigned int ret; |
| 584 | u16 gpionr = irq - IRQ_PA0; |
| 585 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
| 586 | |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 587 | if (pint_val == IRQ_NOT_AVAIL) { |
| 588 | printk(KERN_ERR |
| 589 | "GPIO IRQ %d :Not in PINT Assign table " |
| 590 | "Reconfigure Interrupt to Port Assignemt\n", irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 591 | return -ENODEV; |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 592 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 593 | |
| 594 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
Michael Hennerich | 6782ea9 | 2007-07-24 15:16:59 +0800 | [diff] [blame] | 595 | ret = gpio_request(gpionr, "IRQ"); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 596 | if (ret) |
| 597 | return ret; |
| 598 | } |
| 599 | |
| 600 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 601 | bfin_gpio_unmask_irq(irq); |
| 602 | |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | static void bfin_gpio_irq_shutdown(unsigned int irq) |
| 607 | { |
| 608 | bfin_gpio_mask_irq(irq); |
| 609 | gpio_free(irq - IRQ_PA0); |
| 610 | gpio_enabled[gpio_bank(irq - IRQ_PA0)] &= ~gpio_bit(irq - IRQ_PA0); |
| 611 | } |
| 612 | |
| 613 | static int bfin_gpio_irq_type(unsigned int irq, unsigned int type) |
| 614 | { |
| 615 | |
| 616 | unsigned int ret; |
| 617 | u16 gpionr = irq - IRQ_PA0; |
| 618 | u8 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 619 | u32 pintbit = PINT_BIT(pint_val); |
| 620 | u8 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 621 | |
| 622 | if (pint_val == IRQ_NOT_AVAIL) |
| 623 | return -ENODEV; |
| 624 | |
| 625 | if (type == IRQ_TYPE_PROBE) { |
| 626 | /* only probe unenabled GPIO interrupt lines */ |
| 627 | if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)) |
| 628 | return 0; |
| 629 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 630 | } |
| 631 | |
| 632 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 633 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
| 634 | if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) { |
Michael Hennerich | 6782ea9 | 2007-07-24 15:16:59 +0800 | [diff] [blame] | 635 | ret = gpio_request(gpionr, "IRQ"); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 636 | if (ret) |
| 637 | return ret; |
| 638 | } |
| 639 | |
| 640 | gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr); |
| 641 | } else { |
| 642 | gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr); |
| 643 | return 0; |
| 644 | } |
| 645 | |
| 646 | gpio_direction_input(gpionr); |
| 647 | |
| 648 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 649 | pint[bank]->edge_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 650 | } else { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 651 | pint[bank]->edge_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 652 | } |
| 653 | |
| 654 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 655 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 656 | else |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 657 | pint[bank]->invert_set = pintbit; /* high or rising edge denoted by zero */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 658 | |
| 659 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 660 | pint[bank]->invert_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 661 | else |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 662 | pint[bank]->invert_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 663 | |
| 664 | SSYNC(); |
| 665 | |
| 666 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 667 | set_irq_handler(irq, handle_edge_irq); |
| 668 | else |
| 669 | set_irq_handler(irq, handle_level_irq); |
| 670 | |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | static struct irq_chip bfin_gpio_irqchip = { |
| 675 | .ack = bfin_gpio_ack_irq, |
| 676 | .mask = bfin_gpio_mask_irq, |
| 677 | .mask_ack = bfin_gpio_mask_ack_irq, |
| 678 | .unmask = bfin_gpio_unmask_irq, |
| 679 | .set_type = bfin_gpio_irq_type, |
| 680 | .startup = bfin_gpio_irq_startup, |
| 681 | .shutdown = bfin_gpio_irq_shutdown |
| 682 | }; |
| 683 | |
| 684 | static void bfin_demux_gpio_irq(unsigned int intb_irq, |
| 685 | struct irq_desc *intb_desc) |
| 686 | { |
| 687 | u8 bank, pint_val; |
| 688 | u32 request, irq; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 689 | struct irq_desc *desc; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 690 | |
| 691 | switch (intb_irq) { |
| 692 | case IRQ_PINT0: |
| 693 | bank = 0; |
| 694 | break; |
| 695 | case IRQ_PINT2: |
| 696 | bank = 2; |
| 697 | break; |
| 698 | case IRQ_PINT3: |
| 699 | bank = 3; |
| 700 | break; |
| 701 | case IRQ_PINT1: |
| 702 | bank = 1; |
| 703 | break; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 704 | default: |
| 705 | return; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 706 | } |
| 707 | |
| 708 | pint_val = bank * NR_PINT_BITS; |
| 709 | |
| 710 | request = pint[bank]->request; |
| 711 | |
| 712 | while (request) { |
| 713 | if (request & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 714 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
| 715 | desc = irq_desc + irq; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 716 | desc->handle_irq(irq, desc); |
| 717 | } |
| 718 | pint_val++; |
| 719 | request >>= 1; |
| 720 | } |
| 721 | |
| 722 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 723 | #endif /* CONFIG_IRQCHIP_DEMUX_GPIO */ |
| 724 | |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 725 | void __init init_exception_vectors(void) |
| 726 | { |
| 727 | SSYNC(); |
| 728 | |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 729 | /* cannot program in software: |
| 730 | * evt0 - emulation (jtag) |
| 731 | * evt1 - reset |
| 732 | */ |
| 733 | bfin_write_EVT2(evt_nmi); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 734 | bfin_write_EVT3(trap); |
| 735 | bfin_write_EVT5(evt_ivhw); |
| 736 | bfin_write_EVT6(evt_timer); |
| 737 | bfin_write_EVT7(evt_evt7); |
| 738 | bfin_write_EVT8(evt_evt8); |
| 739 | bfin_write_EVT9(evt_evt9); |
| 740 | bfin_write_EVT10(evt_evt10); |
| 741 | bfin_write_EVT11(evt_evt11); |
| 742 | bfin_write_EVT12(evt_evt12); |
| 743 | bfin_write_EVT13(evt_evt13); |
| 744 | bfin_write_EVT14(evt14_softirq); |
| 745 | bfin_write_EVT15(evt_system_call); |
| 746 | CSYNC(); |
| 747 | } |
| 748 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 749 | /* |
| 750 | * This function should be called during kernel startup to initialize |
| 751 | * the BFin IRQ handling routines. |
| 752 | */ |
| 753 | int __init init_arch_irq(void) |
| 754 | { |
| 755 | int irq; |
| 756 | unsigned long ilat = 0; |
| 757 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 758 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 759 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 760 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
Michael Hennerich | 1c5d226 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 761 | bfin_write_SIC_IWR0(IWR_ENABLE_ALL); |
| 762 | bfin_write_SIC_IWR1(IWR_ENABLE_ALL); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 763 | #ifdef CONFIG_BF54x |
| 764 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 765 | bfin_write_SIC_IWR2(IWR_ENABLE_ALL); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 766 | #endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 767 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 768 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
Michael Hennerich | 1c5d226 | 2007-06-21 11:34:16 +0800 | [diff] [blame] | 769 | bfin_write_SIC_IWR(IWR_ENABLE_ALL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 770 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 771 | SSYNC(); |
| 772 | |
| 773 | local_irq_disable(); |
| 774 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 775 | #if defined(CONFIG_IRQCHIP_DEMUX_GPIO) && defined(CONFIG_BF54x) |
| 776 | #ifdef CONFIG_PINTx_REASSIGN |
| 777 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 778 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 779 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 780 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
| 781 | #endif |
| 782 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 783 | init_pint_lut(); |
| 784 | #endif |
| 785 | |
| 786 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 787 | if (irq <= IRQ_CORETMR) |
| 788 | set_irq_chip(irq, &bfin_core_irqchip); |
| 789 | else |
| 790 | set_irq_chip(irq, &bfin_internal_irqchip); |
| 791 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 792 | if (irq != IRQ_GENERIC_ERROR) { |
| 793 | #endif |
| 794 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 795 | switch (irq) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 796 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 797 | #if defined(CONFIG_BF53x) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 798 | case IRQ_PROG_INTA: |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 799 | set_irq_chained_handler(irq, |
| 800 | bfin_demux_gpio_irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 801 | break; |
| 802 | #if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
| 803 | case IRQ_MAC_RX: |
| 804 | set_irq_chained_handler(irq, |
| 805 | bfin_demux_gpio_irq); |
| 806 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 807 | #endif |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 808 | #elif defined(CONFIG_BF54x) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 809 | case IRQ_PINT0: |
| 810 | set_irq_chained_handler(irq, |
| 811 | bfin_demux_gpio_irq); |
| 812 | break; |
| 813 | case IRQ_PINT1: |
| 814 | set_irq_chained_handler(irq, |
| 815 | bfin_demux_gpio_irq); |
| 816 | break; |
| 817 | case IRQ_PINT2: |
| 818 | set_irq_chained_handler(irq, |
| 819 | bfin_demux_gpio_irq); |
| 820 | break; |
| 821 | case IRQ_PINT3: |
| 822 | set_irq_chained_handler(irq, |
| 823 | bfin_demux_gpio_irq); |
| 824 | break; |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 825 | #elif defined(CONFIG_BF52x) |
| 826 | case IRQ_PORTF_INTA: |
| 827 | set_irq_chained_handler(irq, |
| 828 | bfin_demux_gpio_irq); |
| 829 | break; |
| 830 | case IRQ_PORTG_INTA: |
| 831 | set_irq_chained_handler(irq, |
| 832 | bfin_demux_gpio_irq); |
| 833 | break; |
| 834 | case IRQ_PORTH_INTA: |
| 835 | set_irq_chained_handler(irq, |
| 836 | bfin_demux_gpio_irq); |
| 837 | break; |
| 838 | #endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 839 | #endif |
| 840 | default: |
| 841 | set_irq_handler(irq, handle_simple_irq); |
| 842 | break; |
| 843 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 844 | |
| 845 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 846 | } else { |
| 847 | set_irq_handler(irq, bfin_demux_error_irq); |
| 848 | } |
| 849 | #endif |
| 850 | } |
| 851 | #ifdef BF537_GENERIC_ERROR_INT_DEMUX |
| 852 | for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) { |
| 853 | set_irq_chip(irq, &bfin_generic_error_irqchip); |
| 854 | set_irq_handler(irq, handle_level_irq); |
| 855 | } |
| 856 | #endif |
| 857 | |
| 858 | #ifdef CONFIG_IRQCHIP_DEMUX_GPIO |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 859 | #ifndef CONFIG_BF54x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 860 | for (irq = IRQ_PF0; irq < NR_IRQS; irq++) { |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 861 | #else |
| 862 | for (irq = IRQ_PA0; irq < NR_IRQS; irq++) { |
| 863 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 864 | set_irq_chip(irq, &bfin_gpio_irqchip); |
| 865 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
| 866 | set_irq_handler(irq, handle_level_irq); |
| 867 | } |
| 868 | #endif |
| 869 | bfin_write_IMASK(0); |
| 870 | CSYNC(); |
| 871 | ilat = bfin_read_ILAT(); |
| 872 | CSYNC(); |
| 873 | bfin_write_ILAT(ilat); |
| 874 | CSYNC(); |
| 875 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 876 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 877 | /* IMASK=xxx is equivalent to STI xx or irq_flags=xx, |
| 878 | * local_irq_enable() |
| 879 | */ |
| 880 | program_IAR(); |
| 881 | /* Therefore it's better to setup IARs before interrupts enabled */ |
| 882 | search_IAR(); |
| 883 | |
| 884 | /* Enable interrupts IVG7-15 */ |
| 885 | irq_flags = irq_flags | IMASK_IVG15 | |
| 886 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 887 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 888 | |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | #ifdef CONFIG_DO_IRQ_L1 |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 893 | void do_irq(int vec, struct pt_regs *fp) __attribute__((l1_text)); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 894 | #endif |
| 895 | |
| 896 | void do_irq(int vec, struct pt_regs *fp) |
| 897 | { |
| 898 | if (vec == EVT_IVTMR_P) { |
| 899 | vec = IRQ_CORETMR; |
| 900 | } else { |
| 901 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 902 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 903 | #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 904 | unsigned long sic_status[3]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 905 | |
| 906 | SSYNC(); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 907 | sic_status[0] = bfin_read_SIC_ISR(0) & bfin_read_SIC_IMASK(0); |
| 908 | sic_status[1] = bfin_read_SIC_ISR(1) & bfin_read_SIC_IMASK(1); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 909 | #ifdef CONFIG_BF54x |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 910 | sic_status[2] = bfin_read_SIC_ISR(2) & bfin_read_SIC_IMASK(2); |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame^] | 911 | #endif |
Mike Frysinger | 1f83b8f | 2007-07-12 22:58:21 +0800 | [diff] [blame] | 912 | for (;; ivg++) { |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 913 | if (ivg >= ivg_stop) { |
| 914 | atomic_inc(&num_spurious); |
| 915 | return; |
| 916 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 917 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 918 | break; |
| 919 | } |
| 920 | #else |
| 921 | unsigned long sic_status; |
| 922 | SSYNC(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 923 | sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 924 | |
| 925 | for (;; ivg++) { |
| 926 | if (ivg >= ivg_stop) { |
| 927 | atomic_inc(&num_spurious); |
| 928 | return; |
| 929 | } else if (sic_status & ivg->isrflag) |
| 930 | break; |
| 931 | } |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 932 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 933 | vec = ivg->irqno; |
| 934 | } |
| 935 | asm_do_IRQ(vec, fp); |
| 936 | |
| 937 | #ifdef CONFIG_KGDB |
| 938 | kgdb_process_breakpoint(); |
| 939 | #endif |
| 940 | } |