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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * arch/arm/mach-ixp4xx/common.c
3 *
4 * Generic code shared across all IXP4XX platforms
5 *
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/config.h>
17#include <linux/kernel.h>
18#include <linux/mm.h>
19#include <linux/init.h>
20#include <linux/serial.h>
21#include <linux/sched.h>
22#include <linux/tty.h>
23#include <linux/serial_core.h>
24#include <linux/bootmem.h>
25#include <linux/interrupt.h>
26#include <linux/bitops.h>
27#include <linux/time.h>
28#include <linux/timex.h>
29
30#include <asm/hardware.h>
31#include <asm/uaccess.h>
32#include <asm/io.h>
33#include <asm/pgtable.h>
34#include <asm/page.h>
35#include <asm/irq.h>
36
37#include <asm/mach/map.h>
38#include <asm/mach/irq.h>
39#include <asm/mach/time.h>
40
41enum ixp4xx_irq_type {
42 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
43};
44static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
45
46/*************************************************************************
47 * GPIO acces functions
48 *************************************************************************/
49
50/*
51 * Configure GPIO line for input, interrupt, or output operation
52 *
53 * TODO: Enable/disable the irq_desc based on interrupt or output mode.
54 * TODO: Should these be named ixp4xx_gpio_?
55 */
56void gpio_line_config(u8 line, u32 style)
57{
58 static const int gpio2irq[] = {
59 6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
60 };
61 u32 enable;
62 volatile u32 *int_reg;
63 u32 int_style;
64 enum ixp4xx_irq_type irq_type;
65
66 enable = *IXP4XX_GPIO_GPOER;
67
68 if (style & IXP4XX_GPIO_OUT) {
69 enable &= ~((1) << line);
70 } else if (style & IXP4XX_GPIO_IN) {
71 enable |= ((1) << line);
72
73 switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
74 {
75 case (IXP4XX_GPIO_ACTIVE_HIGH):
76 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
77 irq_type = IXP4XX_IRQ_LEVEL;
78 break;
79 case (IXP4XX_GPIO_ACTIVE_LOW):
80 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
81 irq_type = IXP4XX_IRQ_LEVEL;
82 break;
83 case (IXP4XX_GPIO_RISING_EDGE):
84 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
85 irq_type = IXP4XX_IRQ_EDGE;
86 break;
87 case (IXP4XX_GPIO_FALLING_EDGE):
88 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
89 irq_type = IXP4XX_IRQ_EDGE;
90 break;
91 case (IXP4XX_GPIO_TRANSITIONAL):
92 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
93 irq_type = IXP4XX_IRQ_EDGE;
94 break;
95 default:
96 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
97 irq_type = IXP4XX_IRQ_LEVEL;
98 break;
99 }
100
101 if (style & IXP4XX_GPIO_INTSTYLE_MASK)
102 ixp4xx_config_irq(gpio2irq[line], irq_type);
103
104 if (line >= 8) { /* pins 8-15 */
105 line -= 8;
106 int_reg = IXP4XX_GPIO_GPIT2R;
107 }
108 else { /* pins 0-7 */
109 int_reg = IXP4XX_GPIO_GPIT1R;
110 }
111
112 /* Clear the style for the appropriate pin */
113 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
114 (line * IXP4XX_GPIO_STYLE_SIZE));
115
116 /* Set the new style */
117 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
118 }
119
120 *IXP4XX_GPIO_GPOER = enable;
121}
122
123EXPORT_SYMBOL(gpio_line_config);
124
125/*************************************************************************
126 * IXP4xx chipset I/O mapping
127 *************************************************************************/
128static struct map_desc ixp4xx_io_desc[] __initdata = {
129 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
130 .virtual = IXP4XX_PERIPHERAL_BASE_VIRT,
131 .physical = IXP4XX_PERIPHERAL_BASE_PHYS,
132 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
133 .type = MT_DEVICE
134 }, { /* Expansion Bus Config Registers */
135 .virtual = IXP4XX_EXP_CFG_BASE_VIRT,
136 .physical = IXP4XX_EXP_CFG_BASE_PHYS,
137 .length = IXP4XX_EXP_CFG_REGION_SIZE,
138 .type = MT_DEVICE
139 }, { /* PCI Registers */
140 .virtual = IXP4XX_PCI_CFG_BASE_VIRT,
141 .physical = IXP4XX_PCI_CFG_BASE_PHYS,
142 .length = IXP4XX_PCI_CFG_REGION_SIZE,
143 .type = MT_DEVICE
Deepak Saxena5932ae32005-06-24 20:54:35 +0100144 },
145#ifdef CONFIG_DEBUG_LL
146 { /* Debug UART mapping */
147 .virtual = IXP4XX_DEBUG_UART_BASE_VIRT,
148 .physical = IXP4XX_DEBUG_UART_BASE_PHYS,
149 .length = IXP4XX_DEBUG_UART_REGION_SIZE,
150 .type = MT_DEVICE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 }
Deepak Saxena5932ae32005-06-24 20:54:35 +0100152#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153};
154
155void __init ixp4xx_map_io(void)
156{
157 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
158}
159
160
161/*************************************************************************
162 * IXP4xx chipset IRQ handling
163 *
164 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
165 * (be it PCI or something else) configures that GPIO line
166 * as an IRQ.
167 **************************************************************************/
168static void ixp4xx_irq_mask(unsigned int irq)
169{
170 if (cpu_is_ixp46x() && irq >= 32)
171 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
172 else
173 *IXP4XX_ICMR &= ~(1 << irq);
174}
175
176static void ixp4xx_irq_unmask(unsigned int irq)
177{
178 if (cpu_is_ixp46x() && irq >= 32)
179 *IXP4XX_ICMR2 |= (1 << (irq - 32));
180 else
181 *IXP4XX_ICMR |= (1 << irq);
182}
183
184static void ixp4xx_irq_ack(unsigned int irq)
185{
186 static int irq2gpio[32] = {
187 -1, -1, -1, -1, -1, -1, 0, 1,
188 -1, -1, -1, -1, -1, -1, -1, -1,
189 -1, -1, -1, 2, 3, 4, 5, 6,
190 7, 8, 9, 10, 11, 12, -1, -1,
191 };
192 int line = (irq < 32) ? irq2gpio[irq] : -1;
193
194 if (line >= 0)
195 gpio_line_isr_clear(line);
196}
197
198/*
199 * Level triggered interrupts on GPIO lines can only be cleared when the
200 * interrupt condition disappears.
201 */
202static void ixp4xx_irq_level_unmask(unsigned int irq)
203{
204 ixp4xx_irq_ack(irq);
205 ixp4xx_irq_unmask(irq);
206}
207
208static struct irqchip ixp4xx_irq_level_chip = {
209 .ack = ixp4xx_irq_mask,
210 .mask = ixp4xx_irq_mask,
211 .unmask = ixp4xx_irq_level_unmask,
212};
213
214static struct irqchip ixp4xx_irq_edge_chip = {
215 .ack = ixp4xx_irq_ack,
216 .mask = ixp4xx_irq_mask,
217 .unmask = ixp4xx_irq_unmask,
218};
219
220static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
221{
222 switch (type) {
223 case IXP4XX_IRQ_LEVEL:
224 set_irq_chip(irq, &ixp4xx_irq_level_chip);
225 set_irq_handler(irq, do_level_IRQ);
226 break;
227 case IXP4XX_IRQ_EDGE:
228 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
229 set_irq_handler(irq, do_edge_IRQ);
230 break;
231 }
232 set_irq_flags(irq, IRQF_VALID);
233}
234
235void __init ixp4xx_init_irq(void)
236{
237 int i = 0;
238
239 /* Route all sources to IRQ instead of FIQ */
240 *IXP4XX_ICLR = 0x0;
241
242 /* Disable all interrupt */
243 *IXP4XX_ICMR = 0x0;
244
245 if (cpu_is_ixp46x()) {
246 /* Route upper 32 sources to IRQ instead of FIQ */
247 *IXP4XX_ICLR2 = 0x00;
248
249 /* Disable upper 32 interrupts */
250 *IXP4XX_ICMR2 = 0x00;
251 }
252
253 /* Default to all level triggered */
254 for(i = 0; i < NR_IRQS; i++)
255 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
256}
257
258
259/*************************************************************************
260 * IXP4xx timer tick
261 * We use OS timer1 on the CPU for the timer tick and the timestamp
262 * counter as a source of real clock ticks to account for missed jiffies.
263 *************************************************************************/
264
265static unsigned volatile last_jiffy_time;
266
267#define CLOCK_TICKS_PER_USEC ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
268
269/* IRQs are disabled before entering here from do_gettimeofday() */
270static unsigned long ixp4xx_gettimeoffset(void)
271{
272 u32 elapsed;
273
274 elapsed = *IXP4XX_OSTS - last_jiffy_time;
275
276 return elapsed / CLOCK_TICKS_PER_USEC;
277}
278
279static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
280{
281 write_seqlock(&xtime_lock);
282
283 /* Clear Pending Interrupt by writing '1' to it */
284 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
285
286 /*
287 * Catch up with the real idea of time
288 */
289 while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
290 timer_tick(regs);
291 last_jiffy_time += LATCH;
292 }
293
294 write_sequnlock(&xtime_lock);
295
296 return IRQ_HANDLED;
297}
298
299static struct irqaction ixp4xx_timer_irq = {
300 .name = "IXP4xx Timer Tick",
301 .flags = SA_INTERRUPT,
302 .handler = ixp4xx_timer_interrupt
303};
304
305static void __init ixp4xx_timer_init(void)
306{
307 /* Clear Pending Interrupt by writing '1' to it */
308 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
309
310 /* Setup the Timer counter value */
311 *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
312
313 /* Reset time-stamp counter */
314 *IXP4XX_OSTS = 0;
315 last_jiffy_time = 0;
316
317 /* Connect the interrupt handler and enable the interrupt */
318 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
319}
320
321struct sys_timer ixp4xx_timer = {
322 .init = ixp4xx_timer_init,
323 .offset = ixp4xx_gettimeoffset,
324};
325
326static struct resource ixp46x_i2c_resources[] = {
327 [0] = {
328 .start = 0xc8011000,
329 .end = 0xc801101c,
330 .flags = IORESOURCE_MEM,
331 },
332 [1] = {
333 .start = IRQ_IXP4XX_I2C,
334 .end = IRQ_IXP4XX_I2C,
335 .flags = IORESOURCE_IRQ
336 }
337};
338
339/*
340 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
341 * we just use the same device name.
342 */
343static struct platform_device ixp46x_i2c_controller = {
344 .name = "IOP3xx-I2C",
345 .id = 0,
346 .num_resources = 2,
347 .resource = ixp46x_i2c_resources
348};
349
350static struct platform_device *ixp46x_devices[] __initdata = {
351 &ixp46x_i2c_controller
352};
353
354void __init ixp4xx_sys_init(void)
355{
356 if (cpu_is_ixp46x()) {
357 platform_add_devices(ixp46x_devices,
358 ARRAY_SIZE(ixp46x_devices));
359 }
360}
361