blob: 203371ab19db2b87c97359a12eb8d6defabab649 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-pxa/pxa27x.c
3 *
4 * Author: Nicolas Pitre
5 * Created: Nov 05, 2002
6 * Copyright: MontaVista Software Inc.
7 *
8 * Code specific to PXA27x aka Bulverde.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/pm.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010018#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
20#include <asm/hardware.h>
21#include <asm/irq.h>
Eric Miaocd491042007-06-22 04:14:09 +010022#include <asm/arch/irqs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <asm/arch/pxa-regs.h>
Richard Purdie81f280e2005-11-12 14:22:11 +000024#include <asm/arch/ohci.h>
Russell Kinge176bb02007-05-15 11:16:10 +010025#include <asm/arch/pm.h>
Eric Miaof53f0662007-06-22 05:40:17 +010026#include <asm/arch/dma.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
28#include "generic.h"
Russell King46c41e62007-05-15 15:39:36 +010029#include "devices.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
31/* Crystal clock: 13MHz */
32#define BASE_CLK 13000000
33
34/*
35 * Get the clock frequency as reflected by CCSR and the turbo flag.
36 * We assume these values have been applied via a fcs.
37 * If info is not 0 we also display the current settings.
38 */
39unsigned int get_clk_frequency_khz( int info)
40{
41 unsigned long ccsr, clkcfg;
42 unsigned int l, L, m, M, n2, N, S;
43 int cccr_a, t, ht, b;
44
45 ccsr = CCSR;
46 cccr_a = CCCR & (1 << 25);
47
48 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
49 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
Richard Purdieafe5df22006-02-01 19:25:59 +000050 t = clkcfg & (1 << 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 ht = clkcfg & (1 << 2);
52 b = clkcfg & (1 << 3);
53
54 l = ccsr & 0x1f;
55 n2 = (ccsr>>7) & 0xf;
56 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
57
58 L = l * BASE_CLK;
59 N = (L * n2) / 2;
60 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
61 S = (b) ? L : (L/2);
62
63 if (info) {
64 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
65 L / 1000000, (L % 1000000) / 10000, l );
66 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
67 N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
68 (t) ? "" : "in" );
69 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
70 M / 1000000, (M % 1000000) / 10000, m );
71 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
72 S / 1000000, (S % 1000000) / 10000 );
73 }
74
75 return (t) ? (N/1000) : (L/1000);
76}
77
78/*
79 * Return the current mem clock frequency in units of 10kHz as
80 * reflected by CCCR[A], B, and L
81 */
82unsigned int get_memclk_frequency_10khz(void)
83{
84 unsigned long ccsr, clkcfg;
85 unsigned int l, L, m, M;
86 int cccr_a, b;
87
88 ccsr = CCSR;
89 cccr_a = CCCR & (1 << 25);
90
91 /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
92 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
93 b = clkcfg & (1 << 3);
94
95 l = ccsr & 0x1f;
96 m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
97
98 L = l * BASE_CLK;
99 M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
100
101 return (M / 10000);
102}
103
104/*
105 * Return the current LCD clock frequency in units of 10kHz as
106 */
107unsigned int get_lcdclk_frequency_10khz(void)
108{
109 unsigned long ccsr;
110 unsigned int l, L, k, K;
111
112 ccsr = CCSR;
113
114 l = ccsr & 0x1f;
115 k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
116
117 L = l * BASE_CLK;
118 K = L / k;
119
120 return (K / 10000);
121}
122
123EXPORT_SYMBOL(get_clk_frequency_khz);
124EXPORT_SYMBOL(get_memclk_frequency_10khz);
125EXPORT_SYMBOL(get_lcdclk_frequency_10khz);
126
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100127#ifdef CONFIG_PM
128
Eric Miao711be5c2007-07-18 11:38:45 +0100129#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
130#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
131
132#define RESTORE_GPLEVEL(n) do { \
133 GPSR##n = sleep_save[SLEEP_SAVE_GPLR##n]; \
134 GPCR##n = ~sleep_save[SLEEP_SAVE_GPLR##n]; \
135} while (0)
136
137/*
138 * List of global PXA peripheral registers to preserve.
139 * More ones like CP and general purpose register values are preserved
140 * with the stack pointer in sleep.S.
141 */
142enum { SLEEP_SAVE_START = 0,
143
144 SLEEP_SAVE_GPLR0, SLEEP_SAVE_GPLR1, SLEEP_SAVE_GPLR2, SLEEP_SAVE_GPLR3,
145 SLEEP_SAVE_GPDR0, SLEEP_SAVE_GPDR1, SLEEP_SAVE_GPDR2, SLEEP_SAVE_GPDR3,
146 SLEEP_SAVE_GRER0, SLEEP_SAVE_GRER1, SLEEP_SAVE_GRER2, SLEEP_SAVE_GRER3,
147 SLEEP_SAVE_GFER0, SLEEP_SAVE_GFER1, SLEEP_SAVE_GFER2, SLEEP_SAVE_GFER3,
148 SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2, SLEEP_SAVE_PGSR3,
149
150 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
151 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
152 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
153 SLEEP_SAVE_GAFR3_L, SLEEP_SAVE_GAFR3_U,
154
155 SLEEP_SAVE_PSTR,
156
157 SLEEP_SAVE_ICMR,
158 SLEEP_SAVE_CKEN,
159
160 SLEEP_SAVE_MDREFR,
161 SLEEP_SAVE_PWER, SLEEP_SAVE_PCFR, SLEEP_SAVE_PRER,
162 SLEEP_SAVE_PFER, SLEEP_SAVE_PKWR,
163
164 SLEEP_SAVE_SIZE
165};
166
167void pxa27x_cpu_pm_save(unsigned long *sleep_save)
168{
169 SAVE(GPLR0); SAVE(GPLR1); SAVE(GPLR2); SAVE(GPLR3);
170 SAVE(GPDR0); SAVE(GPDR1); SAVE(GPDR2); SAVE(GPDR3);
171 SAVE(GRER0); SAVE(GRER1); SAVE(GRER2); SAVE(GRER3);
172 SAVE(GFER0); SAVE(GFER1); SAVE(GFER2); SAVE(GFER3);
173 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2); SAVE(PGSR3);
174
175 SAVE(GAFR0_L); SAVE(GAFR0_U);
176 SAVE(GAFR1_L); SAVE(GAFR1_U);
177 SAVE(GAFR2_L); SAVE(GAFR2_U);
178 SAVE(GAFR3_L); SAVE(GAFR3_U);
179
180 SAVE(MDREFR);
181 SAVE(PWER); SAVE(PCFR); SAVE(PRER);
182 SAVE(PFER); SAVE(PKWR);
183
184 SAVE(ICMR); ICMR = 0;
185 SAVE(CKEN);
186 SAVE(PSTR);
187
188 /* Clear GPIO transition detect bits */
189 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2; GEDR3 = GEDR3;
190}
191
192void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
193{
194 /* ensure not to come back here if it wasn't intended */
195 PSPR = 0;
196
197 /* restore registers */
198 RESTORE_GPLEVEL(0); RESTORE_GPLEVEL(1);
199 RESTORE_GPLEVEL(2); RESTORE_GPLEVEL(3);
200 RESTORE(GPDR0); RESTORE(GPDR1); RESTORE(GPDR2); RESTORE(GPDR3);
201 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
202 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
203 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
204 RESTORE(GAFR3_L); RESTORE(GAFR3_U);
205 RESTORE(GRER0); RESTORE(GRER1); RESTORE(GRER2); RESTORE(GRER3);
206 RESTORE(GFER0); RESTORE(GFER1); RESTORE(GFER2); RESTORE(GFER3);
207 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2); RESTORE(PGSR3);
208
209 RESTORE(MDREFR);
210 RESTORE(PWER); RESTORE(PCFR); RESTORE(PRER);
211 RESTORE(PFER); RESTORE(PKWR);
212
213 PSSR = PSSR_RDH | PSSR_PH;
214
215 RESTORE(CKEN);
216
217 ICLR = 0;
218 ICCR = 1;
219 RESTORE(ICMR);
220 RESTORE(PSTR);
221}
222
223void pxa27x_cpu_pm_enter(suspend_state_t state)
Todd Poynor87754202005-06-03 20:52:27 +0100224{
225 extern void pxa_cpu_standby(void);
Todd Poynor87754202005-06-03 20:52:27 +0100226
Todd Poynor26705ca2005-07-01 11:27:05 +0100227 if (state == PM_SUSPEND_STANDBY)
Eric Miao711be5c2007-07-18 11:38:45 +0100228 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER) |
229 (1 << CKEN_LCD) | (1 << CKEN_PWM0);
Todd Poynor26705ca2005-07-01 11:27:05 +0100230 else
Richard Purdie1f750a72007-07-02 10:19:07 +0100231 CKEN = (1 << CKEN_MEMC) | (1 << CKEN_OSTIMER);
Todd Poynor87754202005-06-03 20:52:27 +0100232
233 /* ensure voltage-change sequencer not initiated, which hangs */
234 PCFR &= ~PCFR_FVC;
235
236 /* Clear edge-detect status register. */
237 PEDR = 0xDF12FE1B;
238
239 switch (state) {
Todd Poynor26705ca2005-07-01 11:27:05 +0100240 case PM_SUSPEND_STANDBY:
241 pxa_cpu_standby();
242 break;
Todd Poynor87754202005-06-03 20:52:27 +0100243 case PM_SUSPEND_MEM:
244 /* set resume return address */
245 PSPR = virt_to_phys(pxa_cpu_resume);
Eric Miaob750a092007-07-18 11:40:13 +0100246 pxa27x_cpu_suspend(PWRMODE_SLEEP);
Todd Poynor87754202005-06-03 20:52:27 +0100247 break;
248 }
249}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250
Eric Miao711be5c2007-07-18 11:38:45 +0100251static int pxa27x_cpu_pm_valid(suspend_state_t state)
Russell King88dfe982007-05-15 11:22:48 +0100252{
253 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
254}
255
Eric Miao711be5c2007-07-18 11:38:45 +0100256static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
257 .save_size = SLEEP_SAVE_SIZE,
258 .save = pxa27x_cpu_pm_save,
259 .restore = pxa27x_cpu_pm_restore,
260 .valid = pxa27x_cpu_pm_valid,
261 .enter = pxa27x_cpu_pm_enter,
Russell Kinge176bb02007-05-15 11:16:10 +0100262};
Eric Miao711be5c2007-07-18 11:38:45 +0100263
264static void __init pxa27x_init_pm(void)
265{
266 pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
267}
Nicolas Pitrea8fa3f02005-06-13 22:35:41 +0100268#endif
269
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270/*
271 * device registration specific to PXA27x.
272 */
273
274static u64 pxa27x_dmamask = 0xffffffffUL;
275
276static struct resource pxa27x_ohci_resources[] = {
277 [0] = {
278 .start = 0x4C000000,
279 .end = 0x4C00ff6f,
280 .flags = IORESOURCE_MEM,
281 },
282 [1] = {
283 .start = IRQ_USBH1,
284 .end = IRQ_USBH1,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
Eric Miaoe09d02e2007-07-17 10:45:58 +0100289static struct platform_device pxa27x_device_ohci = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290 .name = "pxa27x-ohci",
291 .id = -1,
292 .dev = {
293 .dma_mask = &pxa27x_dmamask,
294 .coherent_dma_mask = 0xffffffff,
295 },
296 .num_resources = ARRAY_SIZE(pxa27x_ohci_resources),
297 .resource = pxa27x_ohci_resources,
298};
299
Richard Purdie81f280e2005-11-12 14:22:11 +0000300void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
301{
Eric Miaoe09d02e2007-07-17 10:45:58 +0100302 pxa27x_device_ohci.dev.platform_data = info;
Richard Purdie81f280e2005-11-12 14:22:11 +0000303}
304
Russell King34f32312007-05-15 10:39:49 +0100305static struct resource i2c_power_resources[] = {
306 {
307 .start = 0x40f00180,
308 .end = 0x40f001a3,
309 .flags = IORESOURCE_MEM,
310 }, {
311 .start = IRQ_PWRI2C,
312 .end = IRQ_PWRI2C,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
Eric Miaoe09d02e2007-07-17 10:45:58 +0100317static struct platform_device pxa27x_device_i2c_power = {
Russell King34f32312007-05-15 10:39:49 +0100318 .name = "pxa2xx-i2c",
319 .id = 1,
320 .resource = i2c_power_resources,
321 .num_resources = ARRAY_SIZE(i2c_power_resources),
322};
323
Linus Torvalds1da177e2005-04-16 15:20:36 -0700324static struct platform_device *devices[] __initdata = {
Eric Miaoe09d02e2007-07-17 10:45:58 +0100325 &pxa_device_mci,
326 &pxa_device_udc,
327 &pxa_device_fb,
328 &pxa_device_ffuart,
329 &pxa_device_btuart,
330 &pxa_device_stuart,
331 &pxa_device_i2c,
332 &pxa_device_i2s,
333 &pxa_device_ficp,
334 &pxa_device_rtc,
335 &pxa27x_device_i2c_power,
336 &pxa27x_device_ohci,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337};
338
Eric Miaocd491042007-06-22 04:14:09 +0100339void __init pxa27x_init_irq(void)
340{
341 pxa_init_irq_low();
342 pxa_init_irq_high();
343 pxa_init_irq_gpio(128);
344}
345
Linus Torvalds1da177e2005-04-16 15:20:36 -0700346static int __init pxa27x_init(void)
347{
Russell Kinge176bb02007-05-15 11:16:10 +0100348 int ret = 0;
349 if (cpu_is_pxa27x()) {
Eric Miaof53f0662007-06-22 05:40:17 +0100350 if ((ret = pxa_init_dma(32)))
351 return ret;
Russell Kinge176bb02007-05-15 11:16:10 +0100352#ifdef CONFIG_PM
Eric Miao711be5c2007-07-18 11:38:45 +0100353 pxa27x_init_pm();
Russell Kinge176bb02007-05-15 11:16:10 +0100354#endif
355 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
356 }
357 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358}
359
360subsys_initcall(pxa27x_init);