blob: f552003128c6e7899362012766d0eea4f7f6f1cd [file] [log] [blame]
Narsimhulu Musinic8806b62015-05-29 01:04:01 -07001/*
2 * Copyright 2014 Cisco Systems, Inc. All rights reserved.
3 *
4 * This program is free software; you may redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
9 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
10 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
11 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
12 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
13 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
14 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
15 * SOFTWARE.
16 */
17
18#include <linux/string.h>
19#include <linux/errno.h>
20#include <linux/pci.h>
21#include <linux/interrupt.h>
22
23#include "vnic_dev.h"
24#include "vnic_intr.h"
25#include "vnic_stats.h"
26#include "snic_io.h"
27#include "snic.h"
28
29
30/*
31 * snic_isr_msix_wq : MSIx ISR for work queue.
32 */
33
34static irqreturn_t
35snic_isr_msix_wq(int irq, void *data)
36{
37 struct snic *snic = data;
38 unsigned long wq_work_done = 0;
39
40 snic->s_stats.misc.last_isr_time = jiffies;
Narsimhulu Musini3f5c11a2016-03-17 00:51:10 -070041 atomic64_inc(&snic->s_stats.misc.ack_isr_cnt);
Narsimhulu Musinic8806b62015-05-29 01:04:01 -070042
43 wq_work_done = snic_wq_cmpl_handler(snic, -1);
44 svnic_intr_return_credits(&snic->intr[SNIC_MSIX_WQ],
45 wq_work_done,
46 1 /* unmask intr */,
47 1 /* reset intr timer */);
48
49 return IRQ_HANDLED;
50} /* end of snic_isr_msix_wq */
51
52static irqreturn_t
53snic_isr_msix_io_cmpl(int irq, void *data)
54{
55 struct snic *snic = data;
56 unsigned long iocmpl_work_done = 0;
57
58 snic->s_stats.misc.last_isr_time = jiffies;
Narsimhulu Musini3f5c11a2016-03-17 00:51:10 -070059 atomic64_inc(&snic->s_stats.misc.cmpl_isr_cnt);
Narsimhulu Musinic8806b62015-05-29 01:04:01 -070060
61 iocmpl_work_done = snic_fwcq_cmpl_handler(snic, -1);
62 svnic_intr_return_credits(&snic->intr[SNIC_MSIX_IO_CMPL],
63 iocmpl_work_done,
64 1 /* unmask intr */,
65 1 /* reset intr timer */);
66
67 return IRQ_HANDLED;
68} /* end of snic_isr_msix_io_cmpl */
69
70static irqreturn_t
71snic_isr_msix_err_notify(int irq, void *data)
72{
73 struct snic *snic = data;
74
75 snic->s_stats.misc.last_isr_time = jiffies;
Narsimhulu Musini3f5c11a2016-03-17 00:51:10 -070076 atomic64_inc(&snic->s_stats.misc.errnotify_isr_cnt);
Narsimhulu Musinic8806b62015-05-29 01:04:01 -070077
78 svnic_intr_return_all_credits(&snic->intr[SNIC_MSIX_ERR_NOTIFY]);
79 snic_log_q_error(snic);
80
81 /*Handling link events */
82 snic_handle_link_event(snic);
83
84 return IRQ_HANDLED;
85} /* end of snic_isr_msix_err_notify */
86
87
88void
89snic_free_intr(struct snic *snic)
90{
91 int i;
92
93 /* ONLY interrupt mode MSIX is supported */
94 for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
95 if (snic->msix[i].requested) {
96 free_irq(snic->msix_entry[i].vector,
97 snic->msix[i].devid);
98 }
99 }
100} /* end of snic_free_intr */
101
102int
103snic_request_intr(struct snic *snic)
104{
105 int ret = 0, i;
106 enum vnic_dev_intr_mode intr_mode;
107
108 intr_mode = svnic_dev_get_intr_mode(snic->vdev);
109 SNIC_BUG_ON(intr_mode != VNIC_DEV_INTR_MODE_MSIX);
110
111 /*
112 * Currently HW supports single WQ and CQ. So passing devid as snic.
113 * When hardware supports multiple WQs and CQs, one idea is
114 * to pass devid as corresponding WQ or CQ ptr and retrieve snic
115 * from queue ptr.
116 * Except for err_notify, which is always one.
117 */
118 sprintf(snic->msix[SNIC_MSIX_WQ].devname,
119 "%.11s-scsi-wq",
120 snic->name);
121 snic->msix[SNIC_MSIX_WQ].isr = snic_isr_msix_wq;
122 snic->msix[SNIC_MSIX_WQ].devid = snic;
123
124 sprintf(snic->msix[SNIC_MSIX_IO_CMPL].devname,
125 "%.11s-io-cmpl",
126 snic->name);
127 snic->msix[SNIC_MSIX_IO_CMPL].isr = snic_isr_msix_io_cmpl;
128 snic->msix[SNIC_MSIX_IO_CMPL].devid = snic;
129
130 sprintf(snic->msix[SNIC_MSIX_ERR_NOTIFY].devname,
131 "%.11s-err-notify",
132 snic->name);
133 snic->msix[SNIC_MSIX_ERR_NOTIFY].isr = snic_isr_msix_err_notify;
134 snic->msix[SNIC_MSIX_ERR_NOTIFY].devid = snic;
135
136 for (i = 0; i < ARRAY_SIZE(snic->msix); i++) {
137 ret = request_irq(snic->msix_entry[i].vector,
138 snic->msix[i].isr,
139 0,
140 snic->msix[i].devname,
141 snic->msix[i].devid);
142 if (ret) {
143 SNIC_HOST_ERR(snic->shost,
144 "MSI-X: requrest_irq(%d) failed %d\n",
145 i,
146 ret);
147 snic_free_intr(snic);
148 break;
149 }
150 snic->msix[i].requested = 1;
151 }
152
153 return ret;
154} /* end of snic_requrest_intr */
155
156int
157snic_set_intr_mode(struct snic *snic)
158{
159 unsigned int n = ARRAY_SIZE(snic->wq);
160 unsigned int m = SNIC_CQ_IO_CMPL_MAX;
161 unsigned int i;
162
163 /*
164 * We need n WQs, m CQs, and n+m+1 INTRs
165 * (last INTR is used for WQ/CQ errors and notification area
166 */
167
168 BUILD_BUG_ON((ARRAY_SIZE(snic->wq) + SNIC_CQ_IO_CMPL_MAX) >
169 ARRAY_SIZE(snic->intr));
170 SNIC_BUG_ON(ARRAY_SIZE(snic->msix_entry) < (n + m + 1));
171
172 for (i = 0; i < (n + m + 1); i++)
173 snic->msix_entry[i].entry = i;
174
175 if (snic->wq_count >= n && snic->cq_count >= (n + m)) {
176 if (!pci_enable_msix(snic->pdev,
177 snic->msix_entry,
178 (n + m + 1))) {
179 snic->wq_count = n;
180 snic->cq_count = n + m;
181 snic->intr_count = n + m + 1;
182 snic->err_intr_offset = SNIC_MSIX_ERR_NOTIFY;
183
184 SNIC_ISR_DBG(snic->shost,
185 "Using MSI-X Interrupts\n");
186 svnic_dev_set_intr_mode(snic->vdev,
187 VNIC_DEV_INTR_MODE_MSIX);
188
189 return 0;
190 }
191 }
192
193 svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_UNKNOWN);
194
195 return -EINVAL;
196} /* end of snic_set_intr_mode */
197
198void
199snic_clear_intr_mode(struct snic *snic)
200{
201 pci_disable_msix(snic->pdev);
202
203 svnic_dev_set_intr_mode(snic->vdev, VNIC_DEV_INTR_MODE_INTX);
204}