Jani Nikula | 59de081 | 2013-05-22 15:36:16 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include "i915_drv.h" |
| 26 | #include "intel_drv.h" |
| 27 | |
| 28 | /* IOSF sideband */ |
| 29 | static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode, |
| 30 | u8 addr, u32 *val) |
| 31 | { |
| 32 | u32 cmd, devfn, be, bar; |
| 33 | |
| 34 | bar = 0; |
| 35 | be = 0xf; |
| 36 | devfn = PCI_DEVFN(2, 0); |
| 37 | |
| 38 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | |
| 39 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | |
| 40 | (bar << IOSF_BAR_SHIFT); |
| 41 | |
| 42 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 43 | |
| 44 | if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { |
| 45 | DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n", |
| 46 | opcode == PUNIT_OPCODE_REG_READ ? |
| 47 | "read" : "write"); |
| 48 | return -EAGAIN; |
| 49 | } |
| 50 | |
| 51 | I915_WRITE(VLV_IOSF_ADDR, addr); |
| 52 | if (opcode == PUNIT_OPCODE_REG_WRITE) |
| 53 | I915_WRITE(VLV_IOSF_DATA, *val); |
| 54 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); |
| 55 | |
| 56 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, |
| 57 | 5)) { |
| 58 | DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n", |
| 59 | opcode == PUNIT_OPCODE_REG_READ ? "read" : "write", |
| 60 | addr); |
| 61 | return -ETIMEDOUT; |
| 62 | } |
| 63 | |
| 64 | if (opcode == PUNIT_OPCODE_REG_READ) |
| 65 | *val = I915_READ(VLV_IOSF_DATA); |
| 66 | I915_WRITE(VLV_IOSF_DATA, 0); |
| 67 | |
| 68 | return 0; |
| 69 | } |
| 70 | |
| 71 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) |
| 72 | { |
| 73 | return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, |
| 74 | addr, val); |
| 75 | } |
| 76 | |
| 77 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) |
| 78 | { |
| 79 | return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, |
| 80 | addr, &val); |
| 81 | } |
| 82 | |
| 83 | int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) |
| 84 | { |
| 85 | return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, |
| 86 | addr, val); |
| 87 | } |
| 88 | |
| 89 | u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg) |
| 90 | { |
| 91 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 92 | |
| 93 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
| 94 | DRM_ERROR("DPIO idle wait timed out\n"); |
| 95 | return 0; |
| 96 | } |
| 97 | |
| 98 | I915_WRITE(DPIO_REG, reg); |
| 99 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID | |
| 100 | DPIO_BYTE); |
| 101 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
| 102 | DRM_ERROR("DPIO read wait timed out\n"); |
| 103 | return 0; |
| 104 | } |
| 105 | |
| 106 | return I915_READ(DPIO_DATA); |
| 107 | } |
| 108 | |
| 109 | void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) |
| 110 | { |
| 111 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 112 | |
| 113 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) { |
| 114 | DRM_ERROR("DPIO idle wait timed out\n"); |
| 115 | return; |
| 116 | } |
| 117 | |
| 118 | I915_WRITE(DPIO_DATA, val); |
| 119 | I915_WRITE(DPIO_REG, reg); |
| 120 | I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID | |
| 121 | DPIO_BYTE); |
| 122 | if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) |
| 123 | DRM_ERROR("DPIO write wait timed out\n"); |
| 124 | } |
| 125 | |
| 126 | /* SBI access */ |
| 127 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
| 128 | enum intel_sbi_destination destination) |
| 129 | { |
| 130 | u32 value = 0; |
| 131 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 132 | |
| 133 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
| 134 | 100)) { |
| 135 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
| 136 | return 0; |
| 137 | } |
| 138 | |
| 139 | I915_WRITE(SBI_ADDR, (reg << 16)); |
| 140 | |
| 141 | if (destination == SBI_ICLK) |
| 142 | value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; |
| 143 | else |
| 144 | value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; |
| 145 | I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); |
| 146 | |
| 147 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
| 148 | 100)) { |
| 149 | DRM_ERROR("timeout waiting for SBI to complete read transaction\n"); |
| 150 | return 0; |
| 151 | } |
| 152 | |
| 153 | return I915_READ(SBI_DATA); |
| 154 | } |
| 155 | |
| 156 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, |
| 157 | enum intel_sbi_destination destination) |
| 158 | { |
| 159 | u32 tmp; |
| 160 | |
| 161 | WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock)); |
| 162 | |
| 163 | if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, |
| 164 | 100)) { |
| 165 | DRM_ERROR("timeout waiting for SBI to become ready\n"); |
| 166 | return; |
| 167 | } |
| 168 | |
| 169 | I915_WRITE(SBI_ADDR, (reg << 16)); |
| 170 | I915_WRITE(SBI_DATA, value); |
| 171 | |
| 172 | if (destination == SBI_ICLK) |
| 173 | tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; |
| 174 | else |
| 175 | tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; |
| 176 | I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); |
| 177 | |
| 178 | if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, |
| 179 | 100)) { |
| 180 | DRM_ERROR("timeout waiting for SBI to complete write transaction\n"); |
| 181 | return; |
| 182 | } |
| 183 | } |