blob: f6e1e8d4d986df18bd06a2ac7ae047eeb4706182 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include "drmP.h"
31#include "radeon_drm.h"
32#include "radeon_reg.h"
33#include "radeon.h"
34#include "atom.h"
35
36int radeon_debugfs_ib_init(struct radeon_device *rdev);
37
Jerome Glisse9f93ed32010-01-28 18:22:31 +010038void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
39{
40 struct radeon_ib *ib, *n;
41
42 list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) {
43 list_del(&ib->list);
44 vfree(ib->ptr);
45 kfree(ib);
46 }
47}
48
49void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
50{
51 struct radeon_ib *bib;
52
53 bib = kmalloc(sizeof(*bib), GFP_KERNEL);
54 if (bib == NULL)
55 return;
56 bib->ptr = vmalloc(ib->length_dw * 4);
57 if (bib->ptr == NULL) {
58 kfree(bib);
59 return;
60 }
61 memcpy(bib->ptr, ib->ptr, ib->length_dw * 4);
62 bib->length_dw = ib->length_dw;
63 mutex_lock(&rdev->ib_pool.mutex);
64 list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib);
65 mutex_unlock(&rdev->ib_pool.mutex);
66}
67
Jerome Glisse771fe6b2009-06-05 14:42:42 +020068/*
69 * IB.
70 */
71int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib)
72{
73 struct radeon_fence *fence;
74 struct radeon_ib *nib;
Jerome Glisse91cb91b2010-02-15 21:36:13 +010075 int r = 0, i, c;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020076
77 *ib = NULL;
78 r = radeon_fence_create(rdev, &fence);
79 if (r) {
Jerome Glisse91cb91b2010-02-15 21:36:13 +010080 dev_err(rdev->dev, "failed to create fence for new IB\n");
Jerome Glisse771fe6b2009-06-05 14:42:42 +020081 return r;
82 }
83 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +010084 for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) {
85 i &= (RADEON_IB_POOL_SIZE - 1);
86 if (rdev->ib_pool.ibs[i].free) {
87 nib = &rdev->ib_pool.ibs[i];
88 break;
89 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +010091 if (nib == NULL) {
92 /* This should never happen, it means we allocated all
93 * IB and haven't scheduled one yet, return EBUSY to
94 * userspace hoping that on ioctl recall we get better
95 * luck
96 */
97 dev_err(rdev->dev, "no free indirect buffer !\n");
Dave Airlieecb114a2009-09-15 11:12:56 +100098 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +010099 radeon_fence_unref(&fence);
100 return -EBUSY;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200101 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100102 rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1);
103 nib->free = false;
104 if (nib->fence) {
Dave Airlieecb114a2009-09-15 11:12:56 +1000105 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100106 r = radeon_fence_wait(nib->fence, false);
107 if (r) {
108 dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n",
109 nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw);
110 mutex_lock(&rdev->ib_pool.mutex);
111 nib->free = true;
112 mutex_unlock(&rdev->ib_pool.mutex);
113 radeon_fence_unref(&fence);
114 return r;
115 }
116 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200117 }
118 radeon_fence_unref(&nib->fence);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100119 nib->fence = fence;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200120 nib->length_dw = 0;
Dave Airlieecb114a2009-09-15 11:12:56 +1000121 mutex_unlock(&rdev->ib_pool.mutex);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200122 *ib = nib;
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100123 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200124}
125
126void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
127{
128 struct radeon_ib *tmp = *ib;
129
130 *ib = NULL;
131 if (tmp == NULL) {
132 return;
133 }
Jerome Glisse7d404c72010-02-18 13:13:29 +0000134 if (!tmp->fence->emited)
135 radeon_fence_unref(&tmp->fence);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200136 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100137 tmp->free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200138 mutex_unlock(&rdev->ib_pool.mutex);
139}
140
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200141int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
142{
143 int r = 0;
144
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200145 if (!ib->length_dw || !rdev->cp.ready) {
146 /* TODO: Nothings in the ib we should report. */
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100147 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200148 return -EINVAL;
149 }
Dave Airlieecb114a2009-09-15 11:12:56 +1000150
Dave Airlie6cdf6582009-06-29 18:29:13 +1000151 /* 64 dwords should be enough for fence too */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200152 r = radeon_ring_lock(rdev, 64);
153 if (r) {
154 DRM_ERROR("radeon: scheduling IB failled (%d).\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200155 return r;
156 }
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000157 radeon_ring_ib_execute(rdev, ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200158 radeon_fence_emit(rdev, ib->fence);
Dave Airlieecb114a2009-09-15 11:12:56 +1000159 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100160 /* once scheduled IB is considered free and protected by the fence */
161 ib->free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200162 mutex_unlock(&rdev->ib_pool.mutex);
Dave Airlieecb114a2009-09-15 11:12:56 +1000163 radeon_ring_unlock_commit(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200164 return 0;
165}
166
167int radeon_ib_pool_init(struct radeon_device *rdev)
168{
169 void *ptr;
170 uint64_t gpu_addr;
171 int i;
172 int r = 0;
173
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200174 if (rdev->ib_pool.robj)
175 return 0;
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100176 INIT_LIST_HEAD(&rdev->ib_pool.bogus_ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200177 /* Allocate 1M object buffer */
Jerome Glisse4c788672009-11-20 14:29:23 +0100178 r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024,
179 true, RADEON_GEM_DOMAIN_GTT,
180 &rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200181 if (r) {
182 DRM_ERROR("radeon: failed to ib pool (%d).\n", r);
183 return r;
184 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100185 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
186 if (unlikely(r != 0))
187 return r;
188 r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200189 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100190 radeon_bo_unreserve(rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200191 DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r);
192 return r;
193 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100194 r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr);
195 radeon_bo_unreserve(rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 if (r) {
197 DRM_ERROR("radeon: failed to map ib poll (%d).\n", r);
198 return r;
199 }
200 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
201 unsigned offset;
202
203 offset = i * 64 * 1024;
204 rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset;
205 rdev->ib_pool.ibs[i].ptr = ptr + offset;
206 rdev->ib_pool.ibs[i].idx = i;
207 rdev->ib_pool.ibs[i].length_dw = 0;
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100208 rdev->ib_pool.ibs[i].free = true;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200209 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100210 rdev->ib_pool.head_id = 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200211 rdev->ib_pool.ready = true;
212 DRM_INFO("radeon: ib pool ready.\n");
213 if (radeon_debugfs_ib_init(rdev)) {
214 DRM_ERROR("Failed to register debugfs file for IB !\n");
215 }
216 return r;
217}
218
219void radeon_ib_pool_fini(struct radeon_device *rdev)
220{
Jerome Glisse4c788672009-11-20 14:29:23 +0100221 int r;
222
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223 if (!rdev->ib_pool.ready) {
224 return;
225 }
226 mutex_lock(&rdev->ib_pool.mutex);
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100227 radeon_ib_bogus_cleanup(rdev);
Dave Airlieeb6b6d72010-02-25 13:44:04 +1000228
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200229 if (rdev->ib_pool.robj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100230 r = radeon_bo_reserve(rdev->ib_pool.robj, false);
231 if (likely(r == 0)) {
232 radeon_bo_kunmap(rdev->ib_pool.robj);
233 radeon_bo_unpin(rdev->ib_pool.robj);
234 radeon_bo_unreserve(rdev->ib_pool.robj);
235 }
236 radeon_bo_unref(&rdev->ib_pool.robj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200237 rdev->ib_pool.robj = NULL;
238 }
239 mutex_unlock(&rdev->ib_pool.mutex);
240}
241
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200242
243/*
244 * Ring.
245 */
246void radeon_ring_free_size(struct radeon_device *rdev)
247{
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000248 if (rdev->family >= CHIP_R600)
249 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
250 else
251 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200252 /* This works because ring_size is a power of 2 */
253 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4));
254 rdev->cp.ring_free_dw -= rdev->cp.wptr;
255 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask;
256 if (!rdev->cp.ring_free_dw) {
257 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
258 }
259}
260
261int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw)
262{
263 int r;
264
265 /* Align requested size with padding so unlock_commit can
266 * pad safely */
267 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask;
268 mutex_lock(&rdev->cp.mutex);
269 while (ndw > (rdev->cp.ring_free_dw - 1)) {
270 radeon_ring_free_size(rdev);
271 if (ndw < rdev->cp.ring_free_dw) {
272 break;
273 }
274 r = radeon_fence_wait_next(rdev);
275 if (r) {
276 mutex_unlock(&rdev->cp.mutex);
277 return r;
278 }
279 }
280 rdev->cp.count_dw = ndw;
281 rdev->cp.wptr_old = rdev->cp.wptr;
282 return 0;
283}
284
285void radeon_ring_unlock_commit(struct radeon_device *rdev)
286{
287 unsigned count_dw_pad;
288 unsigned i;
289
290 /* We pad to match fetch size */
291 count_dw_pad = (rdev->cp.align_mask + 1) -
292 (rdev->cp.wptr & rdev->cp.align_mask);
293 for (i = 0; i < count_dw_pad; i++) {
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000294 radeon_ring_write(rdev, 2 << 30);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295 }
296 DRM_MEMORYBARRIER();
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000297 radeon_cp_commit(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200298 mutex_unlock(&rdev->cp.mutex);
299}
300
301void radeon_ring_unlock_undo(struct radeon_device *rdev)
302{
303 rdev->cp.wptr = rdev->cp.wptr_old;
304 mutex_unlock(&rdev->cp.mutex);
305}
306
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200307int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size)
308{
309 int r;
310
311 rdev->cp.ring_size = ring_size;
312 /* Allocate ring buffer */
313 if (rdev->cp.ring_obj == NULL) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100314 r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true,
315 RADEON_GEM_DOMAIN_GTT,
316 &rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200317 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100318 dev_err(rdev->dev, "(%d) ring create failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200319 return r;
320 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100321 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
322 if (unlikely(r != 0))
323 return r;
324 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT,
325 &rdev->cp.gpu_addr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200326 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100327 radeon_bo_unreserve(rdev->cp.ring_obj);
328 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200329 return r;
330 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100331 r = radeon_bo_kmap(rdev->cp.ring_obj,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 (void **)&rdev->cp.ring);
Jerome Glisse4c788672009-11-20 14:29:23 +0100333 radeon_bo_unreserve(rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200334 if (r) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100335 dev_err(rdev->dev, "(%d) ring map failed\n", r);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200336 return r;
337 }
338 }
339 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1;
340 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4;
341 return 0;
342}
343
344void radeon_ring_fini(struct radeon_device *rdev)
345{
Jerome Glisse4c788672009-11-20 14:29:23 +0100346 int r;
347
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200348 mutex_lock(&rdev->cp.mutex);
349 if (rdev->cp.ring_obj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100350 r = radeon_bo_reserve(rdev->cp.ring_obj, false);
351 if (likely(r == 0)) {
352 radeon_bo_kunmap(rdev->cp.ring_obj);
353 radeon_bo_unpin(rdev->cp.ring_obj);
354 radeon_bo_unreserve(rdev->cp.ring_obj);
355 }
356 radeon_bo_unref(&rdev->cp.ring_obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200357 rdev->cp.ring = NULL;
358 rdev->cp.ring_obj = NULL;
359 }
360 mutex_unlock(&rdev->cp.mutex);
361}
362
363
364/*
365 * Debugfs info
366 */
367#if defined(CONFIG_DEBUG_FS)
368static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
369{
370 struct drm_info_node *node = (struct drm_info_node *) m->private;
371 struct radeon_ib *ib = node->info_ent->data;
372 unsigned i;
373
374 if (ib == NULL) {
375 return 0;
376 }
Jerome Glisse91cb91b2010-02-15 21:36:13 +0100377 seq_printf(m, "IB %04u\n", ib->idx);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200378 seq_printf(m, "IB fence %p\n", ib->fence);
379 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
380 for (i = 0; i < ib->length_dw; i++) {
381 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
382 }
383 return 0;
384}
385
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100386static int radeon_debugfs_ib_bogus_info(struct seq_file *m, void *data)
387{
388 struct drm_info_node *node = (struct drm_info_node *) m->private;
389 struct radeon_device *rdev = node->info_ent->data;
390 struct radeon_ib *ib;
391 unsigned i;
392
393 mutex_lock(&rdev->ib_pool.mutex);
394 if (list_empty(&rdev->ib_pool.bogus_ib)) {
395 mutex_unlock(&rdev->ib_pool.mutex);
396 seq_printf(m, "no bogus IB recorded\n");
397 return 0;
398 }
399 ib = list_first_entry(&rdev->ib_pool.bogus_ib, struct radeon_ib, list);
400 list_del_init(&ib->list);
401 mutex_unlock(&rdev->ib_pool.mutex);
402 seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
403 for (i = 0; i < ib->length_dw; i++) {
404 seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
405 }
406 vfree(ib->ptr);
407 kfree(ib);
408 return 0;
409}
410
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200411static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
412static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100413
414static struct drm_info_list radeon_debugfs_ib_bogus_info_list[] = {
415 {"radeon_ib_bogus", radeon_debugfs_ib_bogus_info, 0, NULL},
416};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200417#endif
418
419int radeon_debugfs_ib_init(struct radeon_device *rdev)
420{
421#if defined(CONFIG_DEBUG_FS)
422 unsigned i;
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100423 int r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200424
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100425 radeon_debugfs_ib_bogus_info_list[0].data = rdev;
426 r = radeon_debugfs_add_files(rdev, radeon_debugfs_ib_bogus_info_list, 1);
427 if (r)
428 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200429 for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
430 sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
431 radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
432 radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
433 radeon_debugfs_ib_list[i].driver_features = 0;
434 radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i];
435 }
436 return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
437 RADEON_IB_POOL_SIZE);
438#else
439 return 0;
440#endif
441}