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Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_sl82c105.c - SL82C105 PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 *
6 * Based in part on linux/drivers/ide/pci/sl82c105.c
7 * SL82C105/Winbond 553 IDE driver
8 *
9 * and in part on the documentation and errata sheet
Alan16728da2007-02-20 17:51:51 +000010 *
11 *
12 * Note: The controller like many controllers has shared timings for
13 * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
14 * in the dma_stop function. Thus we actually don't need a set_dmamode
15 * method as the PIO method is always called and will set the right PIO
16 * timing parameters.
Jeff Garzik669a5db2006-08-29 18:12:40 -040017 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040018
Jeff Garzik669a5db2006-08-29 18:12:40 -040019#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <scsi/scsi_host.h>
26#include <linux/libata.h>
27
28#define DRV_NAME "pata_sl82c105"
Alan Cox92ba5d02008-01-28 16:08:23 +000029#define DRV_VERSION "0.3.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040030
31enum {
32 /*
33 * SL82C105 PCI config register 0x40 bits.
34 */
35 CTRL_IDE_IRQB = (1 << 30),
36 CTRL_IDE_IRQA = (1 << 28),
37 CTRL_LEGIRQ = (1 << 11),
38 CTRL_P1F16 = (1 << 5),
39 CTRL_P1EN = (1 << 4),
40 CTRL_P0F16 = (1 << 1),
41 CTRL_P0EN = (1 << 0)
42};
43
44/**
45 * sl82c105_pre_reset - probe begin
Tejun Heocc0680a2007-08-06 18:36:23 +090046 * @link: ATA link
Tejun Heod4b2bab2007-02-02 16:50:52 +090047 * @deadline: deadline jiffies for the operation
Jeff Garzik669a5db2006-08-29 18:12:40 -040048 *
49 * Set up cable type and use generic probe init
50 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040051
Tejun Heocc0680a2007-08-06 18:36:23 +090052static int sl82c105_pre_reset(struct ata_link *link, unsigned long deadline)
Jeff Garzik669a5db2006-08-29 18:12:40 -040053{
54 static const struct pci_bits sl82c105_enable_bits[] = {
55 { 0x40, 1, 0x01, 0x01 },
56 { 0x40, 1, 0x10, 0x10 }
57 };
Tejun Heocc0680a2007-08-06 18:36:23 +090058 struct ata_port *ap = link->ap;
Jeff Garzik669a5db2006-08-29 18:12:40 -040059 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
60
Alan Coxc9619222006-09-26 17:53:38 +010061 if (ap->port_no && !pci_test_config_bits(pdev, &sl82c105_enable_bits[ap->port_no]))
62 return -ENOENT;
Tejun Heo9363c382008-04-07 22:47:16 +090063 return ata_sff_prereset(link, deadline);
Jeff Garzik669a5db2006-08-29 18:12:40 -040064}
65
66
Jeff Garzik669a5db2006-08-29 18:12:40 -040067/**
68 * sl82c105_configure_piomode - set chip PIO timing
69 * @ap: ATA interface
70 * @adev: ATA device
71 * @pio: PIO mode
72 *
73 * Called to do the PIO mode setup. Our timing registers are shared
74 * so a configure_dmamode call will undo any work we do here and vice
75 * versa
76 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040077
Jeff Garzik669a5db2006-08-29 18:12:40 -040078static void sl82c105_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
79{
80 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
81 static u16 pio_timing[5] = {
82 0x50D, 0x407, 0x304, 0x242, 0x240
83 };
84 u16 dummy;
85 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
Jeff Garzik85cd7252006-08-31 00:03:49 -040086
Jeff Garzik669a5db2006-08-29 18:12:40 -040087 pci_write_config_word(pdev, timing, pio_timing[pio]);
88 /* Can we lose this oddity of the old driver */
89 pci_read_config_word(pdev, timing, &dummy);
90}
91
92/**
93 * sl82c105_set_piomode - set initial PIO mode data
94 * @ap: ATA interface
95 * @adev: ATA device
96 *
97 * Called to do the PIO mode setup. Our timing registers are shared
98 * but we want to set the PIO timing by default.
99 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400100
Jeff Garzik669a5db2006-08-29 18:12:40 -0400101static void sl82c105_set_piomode(struct ata_port *ap, struct ata_device *adev)
102{
103 sl82c105_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
104}
105
106/**
107 * sl82c105_configure_dmamode - set DMA mode in chip
108 * @ap: ATA interface
109 * @adev: ATA device
110 *
111 * Load DMA cycle times into the chip ready for a DMA transfer
112 * to occur.
113 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400114
Jeff Garzik669a5db2006-08-29 18:12:40 -0400115static void sl82c105_configure_dmamode(struct ata_port *ap, struct ata_device *adev)
116{
117 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
118 static u16 dma_timing[3] = {
119 0x707, 0x201, 0x200
120 };
121 u16 dummy;
122 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno);
123 int dma = adev->dma_mode - XFER_MW_DMA_0;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400124
Jeff Garzik669a5db2006-08-29 18:12:40 -0400125 pci_write_config_word(pdev, timing, dma_timing[dma]);
126 /* Can we lose this oddity of the old driver */
127 pci_read_config_word(pdev, timing, &dummy);
128}
129
130/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400131 * sl82c105_reset_engine - Reset the DMA engine
132 * @ap: ATA interface
133 *
134 * The sl82c105 has some serious problems with the DMA engine
Jeff Garzik85cd7252006-08-31 00:03:49 -0400135 * when transfers don't run as expected or ATAPI is used. The
Jeff Garzik669a5db2006-08-29 18:12:40 -0400136 * recommended fix is to reset the engine each use using a chip
137 * test register.
138 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400139
Jeff Garzik669a5db2006-08-29 18:12:40 -0400140static void sl82c105_reset_engine(struct ata_port *ap)
141{
142 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
143 u16 val;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400144
Jeff Garzik669a5db2006-08-29 18:12:40 -0400145 pci_read_config_word(pdev, 0x7E, &val);
146 pci_write_config_word(pdev, 0x7E, val | 4);
147 pci_write_config_word(pdev, 0x7E, val & ~4);
148}
149
150/**
151 * sl82c105_bmdma_start - DMA engine begin
152 * @qc: ATA command
153 *
154 * Reset the DMA engine each use as recommended by the errata
Jeff Garzik85cd7252006-08-31 00:03:49 -0400155 * document.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400156 *
157 * FIXME: if we switch clock at BMDMA start/end we might get better
158 * PIO performance on DMA capable devices.
159 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400160
Jeff Garzik669a5db2006-08-29 18:12:40 -0400161static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
162{
163 struct ata_port *ap = qc->ap;
164
Olaf Hering8361cd72007-02-10 21:36:14 +0100165 udelay(100);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400166 sl82c105_reset_engine(ap);
Olaf Hering8361cd72007-02-10 21:36:14 +0100167 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400168
Jeff Garzik669a5db2006-08-29 18:12:40 -0400169 /* Set the clocks for DMA */
170 sl82c105_configure_dmamode(ap, qc->dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400171 /* Activate DMA */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400172 ata_bmdma_start(qc);
173}
174
175/**
176 * sl82c105_bmdma_end - DMA engine stop
177 * @qc: ATA command
178 *
179 * Reset the DMA engine each use as recommended by the errata
180 * document.
181 *
182 * This function is also called to turn off DMA when a timeout occurs
183 * during DMA operation. In both cases we need to reset the engine,
184 * so no actual eng_timeout handler is required.
185 *
186 * We assume bmdma_stop is always called if bmdma_start as called. If
187 * not then we may need to wrap qc_issue.
188 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400189
Jeff Garzik669a5db2006-08-29 18:12:40 -0400190static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
191{
192 struct ata_port *ap = qc->ap;
193
194 ata_bmdma_stop(qc);
195 sl82c105_reset_engine(ap);
Olaf Hering8361cd72007-02-10 21:36:14 +0100196 udelay(100);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400197
Jeff Garzik669a5db2006-08-29 18:12:40 -0400198 /* This will redo the initial setup of the DMA device to matching
199 PIO timings */
Alan16728da2007-02-20 17:51:51 +0000200 sl82c105_set_piomode(ap, qc->dev);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400201}
202
Alan Cox92ba5d02008-01-28 16:08:23 +0000203/**
204 * sl82c105_qc_defer - implement serialization
205 * @qc: command
206 *
207 * We must issue one command per host not per channel because
208 * of the reset bug.
209 *
210 * Q: is the scsi host lock sufficient ?
211 */
212
213static int sl82c105_qc_defer(struct ata_queued_cmd *qc)
214{
215 struct ata_host *host = qc->ap->host;
216 struct ata_port *alt = host->ports[1 ^ qc->ap->port_no];
217 int rc;
218
Jeff Garzikc85665f2008-05-19 17:56:10 -0400219 /* First apply the usual rules */
Alan Cox92ba5d02008-01-28 16:08:23 +0000220 rc = ata_std_qc_defer(qc);
221 if (rc != 0)
222 return rc;
223
224 /* Now apply serialization rules. Only allow a command if the
225 other channel state machine is idle */
226 if (alt && alt->qc_active)
227 return ATA_DEFER_PORT;
228 return 0;
229}
230
Jeff Garzik669a5db2006-08-29 18:12:40 -0400231static struct scsi_host_template sl82c105_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900232 ATA_BMDMA_SHT(DRV_NAME),
Jeff Garzik669a5db2006-08-29 18:12:40 -0400233};
234
235static struct ata_port_operations sl82c105_port_ops = {
Tejun Heo029cfd62008-03-25 12:22:49 +0900236 .inherits = &ata_bmdma_port_ops,
237 .qc_defer = sl82c105_qc_defer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400238 .bmdma_start = sl82c105_bmdma_start,
239 .bmdma_stop = sl82c105_bmdma_stop,
Tejun Heo029cfd62008-03-25 12:22:49 +0900240 .cable_detect = ata_cable_40wire,
241 .set_piomode = sl82c105_set_piomode,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900242 .prereset = sl82c105_pre_reset,
Jeff Garzik85cd7252006-08-31 00:03:49 -0400243};
Jeff Garzik669a5db2006-08-29 18:12:40 -0400244
245/**
246 * sl82c105_bridge_revision - find bridge version
247 * @pdev: PCI device for the ATA function
248 *
249 * Locates the PCI bridge associated with the ATA function and
250 * providing it is a Winbond 553 reports the revision. If it cannot
251 * find a revision or the right device it returns -1
252 */
Jeff Garzik85cd7252006-08-31 00:03:49 -0400253
Jeff Garzik669a5db2006-08-29 18:12:40 -0400254static int sl82c105_bridge_revision(struct pci_dev *pdev)
255{
256 struct pci_dev *bridge;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400257
258 /*
259 * The bridge should be part of the same device, but function 0.
260 */
261 bridge = pci_get_slot(pdev->bus,
262 PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
263 if (!bridge)
264 return -1;
265
266 /*
267 * Make sure it is a Winbond 553 and is an ISA bridge.
268 */
269 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
270 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
271 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA) {
272 pci_dev_put(bridge);
273 return -1;
274 }
275 /*
276 * We need to find function 0's revision, not function 1
277 */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400278 pci_dev_put(bridge);
Auke Kok44c10132007-06-08 15:46:36 -0700279 return bridge->revision;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400280}
281
Jeff Garzik85cd7252006-08-31 00:03:49 -0400282
Jeff Garzik669a5db2006-08-29 18:12:40 -0400283static int sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
284{
Tejun Heo1626aeb2007-05-04 12:43:58 +0200285 static const struct ata_port_info info_dma = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400286 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400287 .pio_mask = 0x1f,
288 .mwdma_mask = 0x07,
289 .port_ops = &sl82c105_port_ops
290 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200291 static const struct ata_port_info info_early = {
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400292 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400293 .pio_mask = 0x1f,
294 .port_ops = &sl82c105_port_ops
295 };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200296 /* for now use only the first port */
297 const struct ata_port_info *ppi[] = { &info_early,
Alan Cox92ba5d02008-01-28 16:08:23 +0000298 NULL };
Jeff Garzik669a5db2006-08-29 18:12:40 -0400299 u32 val;
300 int rev;
Tejun Heof08048e2008-03-25 12:22:47 +0900301 int rc;
302
303 rc = pcim_enable_device(dev);
304 if (rc)
305 return rc;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400306
307 rev = sl82c105_bridge_revision(dev);
Jeff Garzik85cd7252006-08-31 00:03:49 -0400308
Jeff Garzik669a5db2006-08-29 18:12:40 -0400309 if (rev == -1)
310 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Unable to find bridge, disabling DMA.\n");
311 else if (rev <= 5)
312 dev_printk(KERN_WARNING, &dev->dev, "pata_sl82c105: Early bridge revision, no DMA available.\n");
Tejun Heo1626aeb2007-05-04 12:43:58 +0200313 else
314 ppi[0] = &info_dma;
Jeff Garzik85cd7252006-08-31 00:03:49 -0400315
Jeff Garzik669a5db2006-08-29 18:12:40 -0400316 pci_read_config_dword(dev, 0x40, &val);
317 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
318 pci_write_config_dword(dev, 0x40, val);
319
Tejun Heo9363c382008-04-07 22:47:16 +0900320 return ata_pci_sff_init_one(dev, ppi, &sl82c105_sht, NULL);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400321}
322
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400323static const struct pci_device_id sl82c105[] = {
324 { PCI_VDEVICE(WINBOND, PCI_DEVICE_ID_WINBOND_82C105), },
325
326 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400327};
328
329static struct pci_driver sl82c105_pci_driver = {
330 .name = DRV_NAME,
331 .id_table = sl82c105,
332 .probe = sl82c105_init_one,
333 .remove = ata_pci_remove_one
334};
335
336static int __init sl82c105_init(void)
337{
338 return pci_register_driver(&sl82c105_pci_driver);
339}
340
Jeff Garzik669a5db2006-08-29 18:12:40 -0400341static void __exit sl82c105_exit(void)
342{
343 pci_unregister_driver(&sl82c105_pci_driver);
344}
345
Jeff Garzik669a5db2006-08-29 18:12:40 -0400346MODULE_AUTHOR("Alan Cox");
347MODULE_DESCRIPTION("low-level driver for Sl82c105");
348MODULE_LICENSE("GPL");
349MODULE_DEVICE_TABLE(pci, sl82c105);
350MODULE_VERSION(DRV_VERSION);
351
352module_init(sl82c105_init);
353module_exit(sl82c105_exit);