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Magnus Damm3fb1b6a2009-01-22 09:55:59 +00001/*
2 * SuperH Timer Support - CMT
3 *
4 * Copyright (C) 2008 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000021#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/io.h>
26#include <linux/clk.h>
27#include <linux/irq.h>
28#include <linux/err.h>
29#include <linux/clocksource.h>
30#include <linux/clockchips.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090031#include <linux/sh_timer.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000033
34struct sh_cmt_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 unsigned long width; /* 16 or 32 bit version of hardware block */
38 unsigned long overflow_bit;
39 unsigned long clear_bits;
40 struct irqaction irqaction;
41 struct platform_device *pdev;
42
43 unsigned long flags;
44 unsigned long match_value;
45 unsigned long next_match_value;
46 unsigned long max_match_value;
47 unsigned long rate;
48 spinlock_t lock;
49 struct clock_event_device ced;
Magnus Damm19bdc9d2009-04-17 05:26:31 +000050 struct clocksource cs;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000051 unsigned long total_cycles;
52};
53
54static DEFINE_SPINLOCK(sh_cmt_lock);
55
56#define CMSTR -1 /* shared register */
57#define CMCSR 0 /* channel register */
58#define CMCNT 1 /* channel register */
59#define CMCOR 2 /* channel register */
60
61static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
62{
Paul Mundt46a12f72009-05-03 17:57:17 +090063 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000064 void __iomem *base = p->mapbase;
65 unsigned long offs;
66
67 if (reg_nr == CMSTR) {
68 offs = 0;
69 base -= cfg->channel_offset;
70 } else
71 offs = reg_nr;
72
73 if (p->width == 16)
74 offs <<= 1;
75 else {
76 offs <<= 2;
77 if ((reg_nr == CMCNT) || (reg_nr == CMCOR))
78 return ioread32(base + offs);
79 }
80
81 return ioread16(base + offs);
82}
83
84static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
85 unsigned long value)
86{
Paul Mundt46a12f72009-05-03 17:57:17 +090087 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +000088 void __iomem *base = p->mapbase;
89 unsigned long offs;
90
91 if (reg_nr == CMSTR) {
92 offs = 0;
93 base -= cfg->channel_offset;
94 } else
95 offs = reg_nr;
96
97 if (p->width == 16)
98 offs <<= 1;
99 else {
100 offs <<= 2;
101 if ((reg_nr == CMCNT) || (reg_nr == CMCOR)) {
102 iowrite32(value, base + offs);
103 return;
104 }
105 }
106
107 iowrite16(value, base + offs);
108}
109
110static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
111 int *has_wrapped)
112{
113 unsigned long v1, v2, v3;
Magnus Damm5b644c72009-04-28 08:17:54 +0000114 int o1, o2;
115
116 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000117
118 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
119 do {
Magnus Damm5b644c72009-04-28 08:17:54 +0000120 o2 = o1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000121 v1 = sh_cmt_read(p, CMCNT);
122 v2 = sh_cmt_read(p, CMCNT);
123 v3 = sh_cmt_read(p, CMCNT);
Magnus Damm5b644c72009-04-28 08:17:54 +0000124 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
125 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
126 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000127
Magnus Damm5b644c72009-04-28 08:17:54 +0000128 *has_wrapped = o1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000129 return v2;
130}
131
132
133static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
134{
Paul Mundt46a12f72009-05-03 17:57:17 +0900135 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000136 unsigned long flags, value;
137
138 /* start stop register shared by multiple timer channels */
139 spin_lock_irqsave(&sh_cmt_lock, flags);
140 value = sh_cmt_read(p, CMSTR);
141
142 if (start)
143 value |= 1 << cfg->timer_bit;
144 else
145 value &= ~(1 << cfg->timer_bit);
146
147 sh_cmt_write(p, CMSTR, value);
148 spin_unlock_irqrestore(&sh_cmt_lock, flags);
149}
150
151static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
152{
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000153 int ret;
154
155 /* enable clock */
156 ret = clk_enable(p->clk);
157 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900158 dev_err(&p->pdev->dev, "cannot enable clock\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000159 return ret;
160 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000161
162 /* make sure channel is disabled */
163 sh_cmt_start_stop_ch(p, 0);
164
165 /* configure channel, periodic mode and maximum timeout */
Magnus Damm3014f472009-04-29 14:50:37 +0000166 if (p->width == 16) {
167 *rate = clk_get_rate(p->clk) / 512;
168 sh_cmt_write(p, CMCSR, 0x43);
169 } else {
170 *rate = clk_get_rate(p->clk) / 8;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000171 sh_cmt_write(p, CMCSR, 0x01a4);
Magnus Damm3014f472009-04-29 14:50:37 +0000172 }
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000173
174 sh_cmt_write(p, CMCOR, 0xffffffff);
175 sh_cmt_write(p, CMCNT, 0);
176
177 /* enable channel */
178 sh_cmt_start_stop_ch(p, 1);
179 return 0;
180}
181
182static void sh_cmt_disable(struct sh_cmt_priv *p)
183{
184 /* disable channel */
185 sh_cmt_start_stop_ch(p, 0);
186
Magnus Dammbe890a12009-06-17 05:04:04 +0000187 /* disable interrupts in CMT block */
188 sh_cmt_write(p, CMCSR, 0);
189
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000190 /* stop clock */
191 clk_disable(p->clk);
192}
193
194/* private flags */
195#define FLAG_CLOCKEVENT (1 << 0)
196#define FLAG_CLOCKSOURCE (1 << 1)
197#define FLAG_REPROGRAM (1 << 2)
198#define FLAG_SKIPEVENT (1 << 3)
199#define FLAG_IRQCONTEXT (1 << 4)
200
201static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv *p,
202 int absolute)
203{
204 unsigned long new_match;
205 unsigned long value = p->next_match_value;
206 unsigned long delay = 0;
207 unsigned long now = 0;
208 int has_wrapped;
209
210 now = sh_cmt_get_counter(p, &has_wrapped);
211 p->flags |= FLAG_REPROGRAM; /* force reprogram */
212
213 if (has_wrapped) {
214 /* we're competing with the interrupt handler.
215 * -> let the interrupt handler reprogram the timer.
216 * -> interrupt number two handles the event.
217 */
218 p->flags |= FLAG_SKIPEVENT;
219 return;
220 }
221
222 if (absolute)
223 now = 0;
224
225 do {
226 /* reprogram the timer hardware,
227 * but don't save the new match value yet.
228 */
229 new_match = now + value + delay;
230 if (new_match > p->max_match_value)
231 new_match = p->max_match_value;
232
233 sh_cmt_write(p, CMCOR, new_match);
234
235 now = sh_cmt_get_counter(p, &has_wrapped);
236 if (has_wrapped && (new_match > p->match_value)) {
237 /* we are changing to a greater match value,
238 * so this wrap must be caused by the counter
239 * matching the old value.
240 * -> first interrupt reprograms the timer.
241 * -> interrupt number two handles the event.
242 */
243 p->flags |= FLAG_SKIPEVENT;
244 break;
245 }
246
247 if (has_wrapped) {
248 /* we are changing to a smaller match value,
249 * so the wrap must be caused by the counter
250 * matching the new value.
251 * -> save programmed match value.
252 * -> let isr handle the event.
253 */
254 p->match_value = new_match;
255 break;
256 }
257
258 /* be safe: verify hardware settings */
259 if (now < new_match) {
260 /* timer value is below match value, all good.
261 * this makes sure we won't miss any match events.
262 * -> save programmed match value.
263 * -> let isr handle the event.
264 */
265 p->match_value = new_match;
266 break;
267 }
268
269 /* the counter has reached a value greater
270 * than our new match value. and since the
271 * has_wrapped flag isn't set we must have
272 * programmed a too close event.
273 * -> increase delay and retry.
274 */
275 if (delay)
276 delay <<= 1;
277 else
278 delay = 1;
279
280 if (!delay)
Paul Mundt214a6072010-03-10 16:26:25 +0900281 dev_warn(&p->pdev->dev, "too long delay\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000282
283 } while (delay);
284}
285
Takashi YOSHII65ada542010-12-17 07:25:09 +0000286static void __sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
287{
288 if (delta > p->max_match_value)
289 dev_warn(&p->pdev->dev, "delta out of range\n");
290
291 p->next_match_value = delta;
292 sh_cmt_clock_event_program_verify(p, 0);
293}
294
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000295static void sh_cmt_set_next(struct sh_cmt_priv *p, unsigned long delta)
296{
297 unsigned long flags;
298
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000299 spin_lock_irqsave(&p->lock, flags);
Takashi YOSHII65ada542010-12-17 07:25:09 +0000300 __sh_cmt_set_next(p, delta);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000301 spin_unlock_irqrestore(&p->lock, flags);
302}
303
304static irqreturn_t sh_cmt_interrupt(int irq, void *dev_id)
305{
306 struct sh_cmt_priv *p = dev_id;
307
308 /* clear flags */
309 sh_cmt_write(p, CMCSR, sh_cmt_read(p, CMCSR) & p->clear_bits);
310
311 /* update clock source counter to begin with if enabled
312 * the wrap flag should be cleared by the timer specific
313 * isr before we end up here.
314 */
315 if (p->flags & FLAG_CLOCKSOURCE)
Magnus Damm43809472010-08-04 04:31:38 +0000316 p->total_cycles += p->match_value + 1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000317
318 if (!(p->flags & FLAG_REPROGRAM))
319 p->next_match_value = p->max_match_value;
320
321 p->flags |= FLAG_IRQCONTEXT;
322
323 if (p->flags & FLAG_CLOCKEVENT) {
324 if (!(p->flags & FLAG_SKIPEVENT)) {
325 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT) {
326 p->next_match_value = p->max_match_value;
327 p->flags |= FLAG_REPROGRAM;
328 }
329
330 p->ced.event_handler(&p->ced);
331 }
332 }
333
334 p->flags &= ~FLAG_SKIPEVENT;
335
336 if (p->flags & FLAG_REPROGRAM) {
337 p->flags &= ~FLAG_REPROGRAM;
338 sh_cmt_clock_event_program_verify(p, 1);
339
340 if (p->flags & FLAG_CLOCKEVENT)
341 if ((p->ced.mode == CLOCK_EVT_MODE_SHUTDOWN)
342 || (p->match_value == p->next_match_value))
343 p->flags &= ~FLAG_REPROGRAM;
344 }
345
346 p->flags &= ~FLAG_IRQCONTEXT;
347
348 return IRQ_HANDLED;
349}
350
351static int sh_cmt_start(struct sh_cmt_priv *p, unsigned long flag)
352{
353 int ret = 0;
354 unsigned long flags;
355
356 spin_lock_irqsave(&p->lock, flags);
357
358 if (!(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
359 ret = sh_cmt_enable(p, &p->rate);
360
361 if (ret)
362 goto out;
363 p->flags |= flag;
364
365 /* setup timeout if no clockevent */
366 if ((flag == FLAG_CLOCKSOURCE) && (!(p->flags & FLAG_CLOCKEVENT)))
Takashi YOSHII65ada542010-12-17 07:25:09 +0000367 __sh_cmt_set_next(p, p->max_match_value);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000368 out:
369 spin_unlock_irqrestore(&p->lock, flags);
370
371 return ret;
372}
373
374static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
375{
376 unsigned long flags;
377 unsigned long f;
378
379 spin_lock_irqsave(&p->lock, flags);
380
381 f = p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE);
382 p->flags &= ~flag;
383
384 if (f && !(p->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE)))
385 sh_cmt_disable(p);
386
387 /* adjust the timeout to maximum if only clocksource left */
388 if ((flag == FLAG_CLOCKEVENT) && (p->flags & FLAG_CLOCKSOURCE))
Takashi YOSHII65ada542010-12-17 07:25:09 +0000389 __sh_cmt_set_next(p, p->max_match_value);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000390
391 spin_unlock_irqrestore(&p->lock, flags);
392}
393
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000394static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
395{
396 return container_of(cs, struct sh_cmt_priv, cs);
397}
398
399static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
400{
401 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
402 unsigned long flags, raw;
403 unsigned long value;
404 int has_wrapped;
405
406 spin_lock_irqsave(&p->lock, flags);
407 value = p->total_cycles;
408 raw = sh_cmt_get_counter(p, &has_wrapped);
409
410 if (unlikely(has_wrapped))
Magnus Damm43809472010-08-04 04:31:38 +0000411 raw += p->match_value + 1;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000412 spin_unlock_irqrestore(&p->lock, flags);
413
414 return value + raw;
415}
416
417static int sh_cmt_clocksource_enable(struct clocksource *cs)
418{
419 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000420
421 p->total_cycles = 0;
422
Paul Mundtf4d7c352010-06-02 17:10:44 +0900423 return sh_cmt_start(p, FLAG_CLOCKSOURCE);
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000424}
425
426static void sh_cmt_clocksource_disable(struct clocksource *cs)
427{
428 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
429}
430
Magnus Dammc8162882010-02-02 14:41:40 -0800431static void sh_cmt_clocksource_resume(struct clocksource *cs)
432{
433 sh_cmt_start(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
434}
435
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000436static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
437 char *name, unsigned long rating)
438{
439 struct clocksource *cs = &p->cs;
440
441 cs->name = name;
442 cs->rating = rating;
443 cs->read = sh_cmt_clocksource_read;
444 cs->enable = sh_cmt_clocksource_enable;
445 cs->disable = sh_cmt_clocksource_disable;
Magnus Dammc8162882010-02-02 14:41:40 -0800446 cs->suspend = sh_cmt_clocksource_disable;
447 cs->resume = sh_cmt_clocksource_resume;
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000448 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
449 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
Paul Mundtf4d7c352010-06-02 17:10:44 +0900450
451 /* clk_get_rate() needs an enabled clock */
452 clk_enable(p->clk);
Magnus Damm38409d72010-08-02 09:24:05 +0000453 p->rate = clk_get_rate(p->clk) / ((p->width == 16) ? 512 : 8);
Paul Mundtf4d7c352010-06-02 17:10:44 +0900454 clk_disable(p->clk);
455
456 /* TODO: calculate good shift from rate and counter bit width */
Paul Mundt5967d332010-06-22 16:41:31 +0900457 cs->shift = 0;
Paul Mundtf4d7c352010-06-02 17:10:44 +0900458 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
459
Paul Mundt214a6072010-03-10 16:26:25 +0900460 dev_info(&p->pdev->dev, "used as clock source\n");
Paul Mundtf4d7c352010-06-02 17:10:44 +0900461
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000462 clocksource_register(cs);
Paul Mundtf4d7c352010-06-02 17:10:44 +0900463
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000464 return 0;
465}
466
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000467static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
468{
469 return container_of(ced, struct sh_cmt_priv, ced);
470}
471
472static void sh_cmt_clock_event_start(struct sh_cmt_priv *p, int periodic)
473{
474 struct clock_event_device *ced = &p->ced;
475
476 sh_cmt_start(p, FLAG_CLOCKEVENT);
477
478 /* TODO: calculate good shift from rate and counter bit width */
479
480 ced->shift = 32;
481 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
482 ced->max_delta_ns = clockevent_delta2ns(p->max_match_value, ced);
483 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced);
484
485 if (periodic)
Magnus Damm43809472010-08-04 04:31:38 +0000486 sh_cmt_set_next(p, ((p->rate + HZ/2) / HZ) - 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000487 else
488 sh_cmt_set_next(p, p->max_match_value);
489}
490
491static void sh_cmt_clock_event_mode(enum clock_event_mode mode,
492 struct clock_event_device *ced)
493{
494 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
495
496 /* deal with old setting first */
497 switch (ced->mode) {
498 case CLOCK_EVT_MODE_PERIODIC:
499 case CLOCK_EVT_MODE_ONESHOT:
500 sh_cmt_stop(p, FLAG_CLOCKEVENT);
501 break;
502 default:
503 break;
504 }
505
506 switch (mode) {
507 case CLOCK_EVT_MODE_PERIODIC:
Paul Mundt214a6072010-03-10 16:26:25 +0900508 dev_info(&p->pdev->dev, "used for periodic clock events\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000509 sh_cmt_clock_event_start(p, 1);
510 break;
511 case CLOCK_EVT_MODE_ONESHOT:
Paul Mundt214a6072010-03-10 16:26:25 +0900512 dev_info(&p->pdev->dev, "used for oneshot clock events\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000513 sh_cmt_clock_event_start(p, 0);
514 break;
515 case CLOCK_EVT_MODE_SHUTDOWN:
516 case CLOCK_EVT_MODE_UNUSED:
517 sh_cmt_stop(p, FLAG_CLOCKEVENT);
518 break;
519 default:
520 break;
521 }
522}
523
524static int sh_cmt_clock_event_next(unsigned long delta,
525 struct clock_event_device *ced)
526{
527 struct sh_cmt_priv *p = ced_to_sh_cmt(ced);
528
529 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
530 if (likely(p->flags & FLAG_IRQCONTEXT))
Magnus Damm43809472010-08-04 04:31:38 +0000531 p->next_match_value = delta - 1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000532 else
Magnus Damm43809472010-08-04 04:31:38 +0000533 sh_cmt_set_next(p, delta - 1);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000534
535 return 0;
536}
537
538static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
539 char *name, unsigned long rating)
540{
541 struct clock_event_device *ced = &p->ced;
542
543 memset(ced, 0, sizeof(*ced));
544
545 ced->name = name;
546 ced->features = CLOCK_EVT_FEAT_PERIODIC;
547 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
548 ced->rating = rating;
549 ced->cpumask = cpumask_of(0);
550 ced->set_next_event = sh_cmt_clock_event_next;
551 ced->set_mode = sh_cmt_clock_event_mode;
552
Paul Mundt214a6072010-03-10 16:26:25 +0900553 dev_info(&p->pdev->dev, "used for clock events\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000554 clockevents_register_device(ced);
555}
556
Paul Mundtd1fcc0a2009-05-03 18:05:42 +0900557static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
558 unsigned long clockevent_rating,
559 unsigned long clocksource_rating)
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000560{
561 if (p->width == (sizeof(p->max_match_value) * 8))
562 p->max_match_value = ~0;
563 else
564 p->max_match_value = (1 << p->width) - 1;
565
566 p->match_value = p->max_match_value;
567 spin_lock_init(&p->lock);
568
569 if (clockevent_rating)
570 sh_cmt_register_clockevent(p, name, clockevent_rating);
571
Magnus Damm19bdc9d2009-04-17 05:26:31 +0000572 if (clocksource_rating)
573 sh_cmt_register_clocksource(p, name, clocksource_rating);
574
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000575 return 0;
576}
577
578static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
579{
Paul Mundt46a12f72009-05-03 17:57:17 +0900580 struct sh_timer_config *cfg = pdev->dev.platform_data;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000581 struct resource *res;
582 int irq, ret;
583 ret = -ENXIO;
584
585 memset(p, 0, sizeof(*p));
586 p->pdev = pdev;
587
588 if (!cfg) {
589 dev_err(&p->pdev->dev, "missing platform data\n");
590 goto err0;
591 }
592
593 platform_set_drvdata(pdev, p);
594
595 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
596 if (!res) {
597 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
598 goto err0;
599 }
600
601 irq = platform_get_irq(p->pdev, 0);
602 if (irq < 0) {
603 dev_err(&p->pdev->dev, "failed to get irq\n");
604 goto err0;
605 }
606
607 /* map memory, let mapbase point to our channel */
608 p->mapbase = ioremap_nocache(res->start, resource_size(res));
609 if (p->mapbase == NULL) {
Paul Mundt214a6072010-03-10 16:26:25 +0900610 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000611 goto err0;
612 }
613
614 /* request irq using setup_irq() (too early for request_irq()) */
Paul Mundt214a6072010-03-10 16:26:25 +0900615 p->irqaction.name = dev_name(&p->pdev->dev);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000616 p->irqaction.handler = sh_cmt_interrupt;
617 p->irqaction.dev_id = p;
Paul Mundtfecf0662010-04-15 11:59:28 +0900618 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
619 IRQF_IRQPOLL | IRQF_NOBALANCING;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000620
621 /* get hold of clock */
Paul Mundtc2a25e82010-03-29 16:55:43 +0900622 p->clk = clk_get(&p->pdev->dev, "cmt_fck");
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000623 if (IS_ERR(p->clk)) {
Magnus Damm03ff8582010-10-13 07:36:38 +0000624 dev_err(&p->pdev->dev, "cannot get clock\n");
625 ret = PTR_ERR(p->clk);
626 goto err1;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000627 }
628
629 if (resource_size(res) == 6) {
630 p->width = 16;
631 p->overflow_bit = 0x80;
Magnus Damm3014f472009-04-29 14:50:37 +0000632 p->clear_bits = ~0x80;
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000633 } else {
634 p->width = 32;
635 p->overflow_bit = 0x8000;
636 p->clear_bits = ~0xc000;
637 }
638
Paul Mundt214a6072010-03-10 16:26:25 +0900639 ret = sh_cmt_register(p, (char *)dev_name(&p->pdev->dev),
Paul Mundtda64c2a2010-02-25 16:37:46 +0900640 cfg->clockevent_rating,
641 cfg->clocksource_rating);
642 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900643 dev_err(&p->pdev->dev, "registration failed\n");
Paul Mundtda64c2a2010-02-25 16:37:46 +0900644 goto err1;
645 }
646
647 ret = setup_irq(irq, &p->irqaction);
648 if (ret) {
Paul Mundt214a6072010-03-10 16:26:25 +0900649 dev_err(&p->pdev->dev, "failed to request irq %d\n", irq);
Paul Mundtda64c2a2010-02-25 16:37:46 +0900650 goto err1;
651 }
652
653 return 0;
654
655err1:
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000656 iounmap(p->mapbase);
Paul Mundtda64c2a2010-02-25 16:37:46 +0900657err0:
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000658 return ret;
659}
660
661static int __devinit sh_cmt_probe(struct platform_device *pdev)
662{
663 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
664 int ret;
665
Magnus Damme475eed2009-04-15 10:50:04 +0000666 if (p) {
Paul Mundt214a6072010-03-10 16:26:25 +0900667 dev_info(&pdev->dev, "kept as earlytimer\n");
Magnus Damme475eed2009-04-15 10:50:04 +0000668 return 0;
669 }
670
Magnus Damm8e0b8422009-04-28 08:19:50 +0000671 p = kmalloc(sizeof(*p), GFP_KERNEL);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000672 if (p == NULL) {
673 dev_err(&pdev->dev, "failed to allocate driver data\n");
674 return -ENOMEM;
675 }
676
677 ret = sh_cmt_setup(p, pdev);
678 if (ret) {
Magnus Damm8e0b8422009-04-28 08:19:50 +0000679 kfree(p);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000680 platform_set_drvdata(pdev, NULL);
681 }
682 return ret;
683}
684
685static int __devexit sh_cmt_remove(struct platform_device *pdev)
686{
687 return -EBUSY; /* cannot unregister clockevent and clocksource */
688}
689
690static struct platform_driver sh_cmt_device_driver = {
691 .probe = sh_cmt_probe,
692 .remove = __devexit_p(sh_cmt_remove),
693 .driver = {
694 .name = "sh_cmt",
695 }
696};
697
698static int __init sh_cmt_init(void)
699{
700 return platform_driver_register(&sh_cmt_device_driver);
701}
702
703static void __exit sh_cmt_exit(void)
704{
705 platform_driver_unregister(&sh_cmt_device_driver);
706}
707
Magnus Damme475eed2009-04-15 10:50:04 +0000708early_platform_init("earlytimer", &sh_cmt_device_driver);
Magnus Damm3fb1b6a2009-01-22 09:55:59 +0000709module_init(sh_cmt_init);
710module_exit(sh_cmt_exit);
711
712MODULE_AUTHOR("Magnus Damm");
713MODULE_DESCRIPTION("SuperH CMT Timer Driver");
714MODULE_LICENSE("GPL v2");