blob: 59892126d1758f9d0e0821fa88ff62094a0c6e74 [file] [log] [blame]
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001/*
2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 *
Nicolas Ferre9102d872012-06-12 10:44:55 +020012 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
Nicolas Ferredc78baa2009-07-03 19:24:33 +020015 */
16
Ludovic Desroches62971b22013-06-13 10:39:39 +020017#include <dt-bindings/dma/at91.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020018#include <linux/clk.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/interrupt.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Nicolas Ferrec5115952011-10-17 14:56:41 +020026#include <linux/of.h>
27#include <linux/of_device.h>
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +000028#include <linux/of_dma.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020029
30#include "at_hdmac_regs.h"
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Nicolas Ferredc78baa2009-07-03 19:24:33 +020032
33/*
34 * Glossary
35 * --------
36 *
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
40 */
41
42#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
Nicolas Ferreae14d4b2011-04-30 16:57:49 +020043#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
Ludovic Desroches816070e2015-01-06 17:36:26 +010045#define ATC_DMA_BUSWIDTHS\
46 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
47 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
48 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
49 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
Nicolas Ferredc78baa2009-07-03 19:24:33 +020050
51/*
52 * Initial number of descriptors to allocate for each channel. This could
53 * be increased during dma usage.
54 */
55static unsigned int init_nr_desc_per_channel = 64;
56module_param(init_nr_desc_per_channel, uint, 0644);
57MODULE_PARM_DESC(init_nr_desc_per_channel,
58 "initial descriptors per channel (default: 64)");
59
60
61/* prototypes */
62static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
Elen Songd48de6f2013-05-10 11:01:46 +080063static void atc_issue_pending(struct dma_chan *chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +020064
65
66/*----------------------------------------------------------------------*/
67
Torsten Fleischer265567f2015-02-23 17:54:11 +010068static inline unsigned int atc_get_xfer_width(dma_addr_t src, dma_addr_t dst,
69 size_t len)
70{
71 unsigned int width;
72
73 if (!((src | dst | len) & 3))
74 width = 2;
75 else if (!((src | dst | len) & 1))
76 width = 1;
77 else
78 width = 0;
79
80 return width;
81}
82
Nicolas Ferredc78baa2009-07-03 19:24:33 +020083static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
84{
85 return list_first_entry(&atchan->active_list,
86 struct at_desc, desc_node);
87}
88
89static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
90{
91 return list_first_entry(&atchan->queue,
92 struct at_desc, desc_node);
93}
94
95/**
Uwe Kleine-König421f91d2010-06-11 12:17:00 +020096 * atc_alloc_descriptor - allocate and return an initialized descriptor
Nicolas Ferredc78baa2009-07-03 19:24:33 +020097 * @chan: the channel to allocate descriptors for
98 * @gfp_flags: GFP allocation flags
99 *
100 * Note: The ack-bit is positioned in the descriptor flag at creation time
101 * to make initial allocation more convenient. This bit will be cleared
102 * and control will be given to client at usage time (during
103 * preparation functions).
104 */
105static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
106 gfp_t gfp_flags)
107{
108 struct at_desc *desc = NULL;
109 struct at_dma *atdma = to_at_dma(chan->device);
110 dma_addr_t phys;
111
112 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
113 if (desc) {
114 memset(desc, 0, sizeof(struct at_desc));
Dan Williams285a3c72009-09-08 17:53:03 -0700115 INIT_LIST_HEAD(&desc->tx_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200116 dma_async_tx_descriptor_init(&desc->txd, chan);
117 /* txd.flags will be overwritten in prep functions */
118 desc->txd.flags = DMA_CTRL_ACK;
119 desc->txd.tx_submit = atc_tx_submit;
120 desc->txd.phys = phys;
121 }
122
123 return desc;
124}
125
126/**
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200127 * atc_desc_get - get an unused descriptor from free_list
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200128 * @atchan: channel we want a new descriptor for
129 */
130static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
131{
132 struct at_desc *desc, *_desc;
133 struct at_desc *ret = NULL;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000134 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200135 unsigned int i = 0;
136 LIST_HEAD(tmp_list);
137
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000138 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200139 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
140 i++;
141 if (async_tx_test_ack(&desc->txd)) {
142 list_del(&desc->desc_node);
143 ret = desc;
144 break;
145 }
146 dev_dbg(chan2dev(&atchan->chan_common),
147 "desc %p not ACKed\n", desc);
148 }
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000149 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200150 dev_vdbg(chan2dev(&atchan->chan_common),
151 "scanned %u descriptors on freelist\n", i);
152
153 /* no more descriptor available in initial pool: create one more */
154 if (!ret) {
155 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
156 if (ret) {
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000157 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200158 atchan->descs_allocated++;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000159 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200160 } else {
161 dev_err(chan2dev(&atchan->chan_common),
162 "not enough descriptors available\n");
163 }
164 }
165
166 return ret;
167}
168
169/**
170 * atc_desc_put - move a descriptor, including any children, to the free list
171 * @atchan: channel we work on
172 * @desc: descriptor, at the head of a chain, to move to free list
173 */
174static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
175{
176 if (desc) {
177 struct at_desc *child;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000178 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200179
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000180 spin_lock_irqsave(&atchan->lock, flags);
Dan Williams285a3c72009-09-08 17:53:03 -0700181 list_for_each_entry(child, &desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200182 dev_vdbg(chan2dev(&atchan->chan_common),
183 "moving child desc %p to freelist\n",
184 child);
Dan Williams285a3c72009-09-08 17:53:03 -0700185 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200186 dev_vdbg(chan2dev(&atchan->chan_common),
187 "moving desc %p to freelist\n", desc);
188 list_add(&desc->desc_node, &atchan->free_list);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000189 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200190 }
191}
192
193/**
Masanari Iidad73111c2012-08-04 23:37:53 +0900194 * atc_desc_chain - build chain adding a descriptor
195 * @first: address of first descriptor of the chain
196 * @prev: address of previous descriptor of the chain
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200197 * @desc: descriptor to queue
198 *
199 * Called from prep_* functions
200 */
201static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
202 struct at_desc *desc)
203{
204 if (!(*first)) {
205 *first = desc;
206 } else {
207 /* inform the HW lli about chaining */
208 (*prev)->lli.dscr = desc->txd.phys;
209 /* insert the link descriptor to the LD ring */
210 list_add_tail(&desc->desc_node,
211 &(*first)->tx_list);
212 }
213 *prev = desc;
214}
215
216/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200217 * atc_dostart - starts the DMA engine for real
218 * @atchan: the channel we want to start
219 * @first: first descriptor in the list we want to begin with
220 *
221 * Called with atchan->lock held and bh disabled
222 */
223static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
224{
225 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
226
227 /* ASSERT: channel is idle */
228 if (atc_chan_is_enabled(atchan)) {
229 dev_err(chan2dev(&atchan->chan_common),
230 "BUG: Attempted to start non-idle channel\n");
231 dev_err(chan2dev(&atchan->chan_common),
232 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
233 channel_readl(atchan, SADDR),
234 channel_readl(atchan, DADDR),
235 channel_readl(atchan, CTRLA),
236 channel_readl(atchan, CTRLB),
237 channel_readl(atchan, DSCR));
238
239 /* The tasklet will hopefully advance the queue... */
240 return;
241 }
242
243 vdbg_dump_regs(atchan);
244
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200245 channel_writel(atchan, SADDR, 0);
246 channel_writel(atchan, DADDR, 0);
247 channel_writel(atchan, CTRLA, 0);
248 channel_writel(atchan, CTRLB, 0);
249 channel_writel(atchan, DSCR, first->txd.phys);
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200250 channel_writel(atchan, SPIP, ATC_SPIP_HOLE(first->src_hole) |
251 ATC_SPIP_BOUNDARY(first->boundary));
252 channel_writel(atchan, DPIP, ATC_DPIP_HOLE(first->dst_hole) |
253 ATC_DPIP_BOUNDARY(first->boundary));
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200254 dma_writel(atdma, CHER, atchan->mask);
255
256 vdbg_dump_regs(atchan);
257}
258
Elen Songd48de6f2013-05-10 11:01:46 +0800259/*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100260 * atc_get_desc_by_cookie - get the descriptor of a cookie
261 * @atchan: the DMA channel
262 * @cookie: the cookie to get the descriptor for
Elen Songd48de6f2013-05-10 11:01:46 +0800263 */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100264static struct at_desc *atc_get_desc_by_cookie(struct at_dma_chan *atchan,
265 dma_cookie_t cookie)
Elen Songd48de6f2013-05-10 11:01:46 +0800266{
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100267 struct at_desc *desc, *_desc;
268
269 list_for_each_entry_safe(desc, _desc, &atchan->queue, desc_node) {
270 if (desc->txd.cookie == cookie)
271 return desc;
272 }
Elen Songd48de6f2013-05-10 11:01:46 +0800273
274 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100275 if (desc->txd.cookie == cookie)
276 return desc;
Elen Songd48de6f2013-05-10 11:01:46 +0800277 }
278
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100279 return NULL;
Elen Songd48de6f2013-05-10 11:01:46 +0800280}
281
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100282/**
283 * atc_calc_bytes_left - calculates the number of bytes left according to the
284 * value read from CTRLA.
285 *
286 * @current_len: the number of bytes left before reading CTRLA
287 * @ctrla: the value of CTRLA
288 * @desc: the descriptor containing the transfer width
Elen Songd48de6f2013-05-10 11:01:46 +0800289 */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100290static inline int atc_calc_bytes_left(int current_len, u32 ctrla,
291 struct at_desc *desc)
292{
293 return current_len - ((ctrla & ATC_BTSIZE_MAX) << desc->tx_width);
294}
295
296/**
297 * atc_calc_bytes_left_from_reg - calculates the number of bytes left according
298 * to the current value of CTRLA.
299 *
300 * @current_len: the number of bytes left before reading CTRLA
301 * @atchan: the channel to read CTRLA for
302 * @desc: the descriptor containing the transfer width
303 */
304static inline int atc_calc_bytes_left_from_reg(int current_len,
305 struct at_dma_chan *atchan, struct at_desc *desc)
306{
307 u32 ctrla = channel_readl(atchan, CTRLA);
308
309 return atc_calc_bytes_left(current_len, ctrla, desc);
310}
311
312/**
313 * atc_get_bytes_left - get the number of bytes residue for a cookie
314 * @chan: DMA channel
315 * @cookie: transaction identifier to check status of
316 */
317static int atc_get_bytes_left(struct dma_chan *chan, dma_cookie_t cookie)
Elen Songd48de6f2013-05-10 11:01:46 +0800318{
319 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Elen Songd48de6f2013-05-10 11:01:46 +0800320 struct at_desc *desc_first = atc_first_active(atchan);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100321 struct at_desc *desc;
322 int ret;
323 u32 ctrla, dscr;
Elen Songd48de6f2013-05-10 11:01:46 +0800324
325 /*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100326 * If the cookie doesn't match to the currently running transfer then
327 * we can return the total length of the associated DMA transfer,
328 * because it is still queued.
Elen Songd48de6f2013-05-10 11:01:46 +0800329 */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100330 desc = atc_get_desc_by_cookie(atchan, cookie);
331 if (desc == NULL)
332 return -EINVAL;
333 else if (desc != desc_first)
334 return desc->total_len;
Elen Songd48de6f2013-05-10 11:01:46 +0800335
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100336 /* cookie matches to the currently running transfer */
337 ret = desc_first->total_len;
Alexandre Belloni6758dda2014-08-01 18:51:46 +0200338
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100339 if (desc_first->lli.dscr) {
340 /* hardware linked list transfer */
Alexandre Belloni6758dda2014-08-01 18:51:46 +0200341
Elen Songd48de6f2013-05-10 11:01:46 +0800342 /*
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100343 * Calculate the residue by removing the length of the child
344 * descriptors already transferred from the total length.
345 * To get the current child descriptor we can use the value of
346 * the channel's DSCR register and compare it against the value
347 * of the hardware linked list structure of each child
348 * descriptor.
Elen Songd48de6f2013-05-10 11:01:46 +0800349 */
Elen Songd48de6f2013-05-10 11:01:46 +0800350
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100351 ctrla = channel_readl(atchan, CTRLA);
352 rmb(); /* ensure CTRLA is read before DSCR */
353 dscr = channel_readl(atchan, DSCR);
354
355 /* for the first descriptor we can be more accurate */
356 if (desc_first->lli.dscr == dscr)
357 return atc_calc_bytes_left(ret, ctrla, desc_first);
358
359 ret -= desc_first->len;
360 list_for_each_entry(desc, &desc_first->tx_list, desc_node) {
361 if (desc->lli.dscr == dscr)
362 break;
363
364 ret -= desc->len;
365 }
366
367 /*
368 * For the last descriptor in the chain we can calculate
369 * the remaining bytes using the channel's register.
370 * Note that the transfer width of the first and last
371 * descriptor may differ.
372 */
373 if (!desc->lli.dscr)
374 ret = atc_calc_bytes_left_from_reg(ret, atchan, desc);
375 } else {
376 /* single transfer */
377 ret = atc_calc_bytes_left_from_reg(ret, atchan, desc_first);
378 }
379
Elen Songd48de6f2013-05-10 11:01:46 +0800380 return ret;
381}
382
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200383/**
384 * atc_chain_complete - finish work for one transaction chain
385 * @atchan: channel we work on
386 * @desc: descriptor at the head of the chain we want do complete
387 *
388 * Called with atchan->lock held and bh disabled */
389static void
390atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
391{
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200392 struct dma_async_tx_descriptor *txd = &desc->txd;
393
394 dev_vdbg(chan2dev(&atchan->chan_common),
395 "descriptor %u complete\n", txd->cookie);
396
Vinod Kould4116052012-05-11 11:48:21 +0530397 /* mark the descriptor as complete for non cyclic cases only */
398 if (!atc_chan_is_cyclic(atchan))
399 dma_cookie_complete(txd);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200400
401 /* move children to free_list */
Dan Williams285a3c72009-09-08 17:53:03 -0700402 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200403 /* move myself to free_list */
404 list_move(&desc->desc_node, &atchan->free_list);
405
Dan Williamsd38a8c62013-10-18 19:35:23 +0200406 dma_descriptor_unmap(txd);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200407 /* for cyclic transfers,
408 * no need to replay callback function while stopping */
Nicolas Ferre3c477482011-07-25 21:09:23 +0000409 if (!atc_chan_is_cyclic(atchan)) {
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200410 dma_async_tx_callback callback = txd->callback;
411 void *param = txd->callback_param;
412
413 /*
414 * The API requires that no submissions are done from a
415 * callback, so we don't need to drop the lock here
416 */
417 if (callback)
418 callback(param);
419 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200420
421 dma_run_dependencies(txd);
422}
423
424/**
425 * atc_complete_all - finish work for all transactions
426 * @atchan: channel to complete transactions for
427 *
428 * Eventually submit queued descriptors if any
429 *
430 * Assume channel is idle while calling this function
431 * Called with atchan->lock held and bh disabled
432 */
433static void atc_complete_all(struct at_dma_chan *atchan)
434{
435 struct at_desc *desc, *_desc;
436 LIST_HEAD(list);
437
438 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
439
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200440 /*
441 * Submit queued descriptors ASAP, i.e. before we go through
442 * the completed ones.
443 */
444 if (!list_empty(&atchan->queue))
445 atc_dostart(atchan, atc_first_queued(atchan));
446 /* empty active_list now it is completed */
447 list_splice_init(&atchan->active_list, &list);
448 /* empty queue list by moving descriptors (if any) to active_list */
449 list_splice_init(&atchan->queue, &atchan->active_list);
450
451 list_for_each_entry_safe(desc, _desc, &list, desc_node)
452 atc_chain_complete(atchan, desc);
453}
454
455/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200456 * atc_advance_work - at the end of a transaction, move forward
457 * @atchan: channel where the transaction ended
458 *
459 * Called with atchan->lock held and bh disabled
460 */
461static void atc_advance_work(struct at_dma_chan *atchan)
462{
463 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
464
Ludovic Desrochesd202f052013-04-18 09:52:59 +0200465 if (atc_chan_is_enabled(atchan))
466 return;
467
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200468 if (list_empty(&atchan->active_list) ||
469 list_is_singular(&atchan->active_list)) {
470 atc_complete_all(atchan);
471 } else {
472 atc_chain_complete(atchan, atc_first_active(atchan));
473 /* advance work */
474 atc_dostart(atchan, atc_first_active(atchan));
475 }
476}
477
478
479/**
480 * atc_handle_error - handle errors reported by DMA controller
481 * @atchan: channel where error occurs
482 *
483 * Called with atchan->lock held and bh disabled
484 */
485static void atc_handle_error(struct at_dma_chan *atchan)
486{
487 struct at_desc *bad_desc;
488 struct at_desc *child;
489
490 /*
491 * The descriptor currently at the head of the active list is
492 * broked. Since we don't have any way to report errors, we'll
493 * just have to scream loudly and try to carry on.
494 */
495 bad_desc = atc_first_active(atchan);
496 list_del_init(&bad_desc->desc_node);
497
498 /* As we are stopped, take advantage to push queued descriptors
499 * in active_list */
500 list_splice_init(&atchan->queue, atchan->active_list.prev);
501
502 /* Try to restart the controller */
503 if (!list_empty(&atchan->active_list))
504 atc_dostart(atchan, atc_first_active(atchan));
505
506 /*
507 * KERN_CRITICAL may seem harsh, but since this only happens
508 * when someone submits a bad physical address in a
509 * descriptor, we should consider ourselves lucky that the
510 * controller flagged an error instead of scribbling over
511 * random memory locations.
512 */
513 dev_crit(chan2dev(&atchan->chan_common),
514 "Bad descriptor submitted for DMA!\n");
515 dev_crit(chan2dev(&atchan->chan_common),
516 " cookie: %d\n", bad_desc->txd.cookie);
517 atc_dump_lli(atchan, &bad_desc->lli);
Dan Williams285a3c72009-09-08 17:53:03 -0700518 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200519 atc_dump_lli(atchan, &child->lli);
520
521 /* Pretend the descriptor completed successfully */
522 atc_chain_complete(atchan, bad_desc);
523}
524
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200525/**
526 * atc_handle_cyclic - at the end of a period, run callback function
527 * @atchan: channel used for cyclic operations
528 *
529 * Called with atchan->lock held and bh disabled
530 */
531static void atc_handle_cyclic(struct at_dma_chan *atchan)
532{
533 struct at_desc *first = atc_first_active(atchan);
534 struct dma_async_tx_descriptor *txd = &first->txd;
535 dma_async_tx_callback callback = txd->callback;
536 void *param = txd->callback_param;
537
538 dev_vdbg(chan2dev(&atchan->chan_common),
539 "new cyclic period llp 0x%08x\n",
540 channel_readl(atchan, DSCR));
541
542 if (callback)
543 callback(param);
544}
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200545
546/*-- IRQ & Tasklet ---------------------------------------------------*/
547
548static void atc_tasklet(unsigned long data)
549{
550 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000551 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200552
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000553 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200554 if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200555 atc_handle_error(atchan);
Nicolas Ferre3c477482011-07-25 21:09:23 +0000556 else if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200557 atc_handle_cyclic(atchan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200558 else
559 atc_advance_work(atchan);
560
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000561 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200562}
563
564static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
565{
566 struct at_dma *atdma = (struct at_dma *)dev_id;
567 struct at_dma_chan *atchan;
568 int i;
569 u32 status, pending, imr;
570 int ret = IRQ_NONE;
571
572 do {
573 imr = dma_readl(atdma, EBCIMR);
574 status = dma_readl(atdma, EBCISR);
575 pending = status & imr;
576
577 if (!pending)
578 break;
579
580 dev_vdbg(atdma->dma_common.dev,
581 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
582 status, imr, pending);
583
584 for (i = 0; i < atdma->dma_common.chancnt; i++) {
585 atchan = &atdma->chan[i];
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200586 if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200587 if (pending & AT_DMA_ERR(i)) {
588 /* Disable channel on AHB error */
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +0200589 dma_writel(atdma, CHDR,
590 AT_DMA_RES(i) | atchan->mask);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200591 /* Give information to tasklet */
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200592 set_bit(ATC_IS_ERROR, &atchan->status);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200593 }
594 tasklet_schedule(&atchan->tasklet);
595 ret = IRQ_HANDLED;
596 }
597 }
598
599 } while (pending);
600
601 return ret;
602}
603
604
605/*-- DMA Engine API --------------------------------------------------*/
606
607/**
608 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
609 * @desc: descriptor at the head of the transaction chain
610 *
611 * Queue chain if DMA engine is working already
612 *
613 * Cookie increment and adding to active_list or queue must be atomic
614 */
615static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
616{
617 struct at_desc *desc = txd_to_at_desc(tx);
618 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
619 dma_cookie_t cookie;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000620 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200621
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000622 spin_lock_irqsave(&atchan->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000623 cookie = dma_cookie_assign(tx);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200624
625 if (list_empty(&atchan->active_list)) {
626 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
627 desc->txd.cookie);
628 atc_dostart(atchan, desc);
629 list_add_tail(&desc->desc_node, &atchan->active_list);
630 } else {
631 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
632 desc->txd.cookie);
633 list_add_tail(&desc->desc_node, &atchan->queue);
634 }
635
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000636 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200637
638 return cookie;
639}
640
641/**
Maxime Ripard5abecfa2015-05-27 16:01:53 +0200642 * atc_prep_dma_interleaved - prepare memory to memory interleaved operation
643 * @chan: the channel to prepare operation on
644 * @xt: Interleaved transfer template
645 * @flags: tx descriptor status flags
646 */
647static struct dma_async_tx_descriptor *
648atc_prep_dma_interleaved(struct dma_chan *chan,
649 struct dma_interleaved_template *xt,
650 unsigned long flags)
651{
652 struct at_dma_chan *atchan = to_at_dma_chan(chan);
653 struct data_chunk *first = xt->sgl;
654 struct at_desc *desc = NULL;
655 size_t xfer_count;
656 unsigned int dwidth;
657 u32 ctrla;
658 u32 ctrlb;
659 size_t len = 0;
660 int i;
661
662 dev_info(chan2dev(chan),
663 "%s: src=0x%08x, dest=0x%08x, numf=%d, frame_size=%d, flags=0x%lx\n",
664 __func__, xt->src_start, xt->dst_start, xt->numf,
665 xt->frame_size, flags);
666
667 if (unlikely(!xt || xt->numf != 1 || !xt->frame_size))
668 return NULL;
669
670 /*
671 * The controller can only "skip" X bytes every Y bytes, so we
672 * need to make sure we are given a template that fit that
673 * description, ie a template with chunks that always have the
674 * same size, with the same ICGs.
675 */
676 for (i = 0; i < xt->frame_size; i++) {
677 struct data_chunk *chunk = xt->sgl + i;
678
679 if ((chunk->size != xt->sgl->size) ||
680 (dmaengine_get_dst_icg(xt, chunk) != dmaengine_get_dst_icg(xt, first)) ||
681 (dmaengine_get_src_icg(xt, chunk) != dmaengine_get_src_icg(xt, first))) {
682 dev_err(chan2dev(chan),
683 "%s: the controller can transfer only identical chunks\n",
684 __func__);
685 return NULL;
686 }
687
688 len += chunk->size;
689 }
690
691 dwidth = atc_get_xfer_width(xt->src_start,
692 xt->dst_start, len);
693
694 xfer_count = len >> dwidth;
695 if (xfer_count > ATC_BTSIZE_MAX) {
696 dev_err(chan2dev(chan), "%s: buffer is too big\n", __func__);
697 return NULL;
698 }
699
700 ctrla = ATC_SRC_WIDTH(dwidth) |
701 ATC_DST_WIDTH(dwidth);
702
703 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
704 | ATC_SRC_ADDR_MODE_INCR
705 | ATC_DST_ADDR_MODE_INCR
706 | ATC_SRC_PIP
707 | ATC_DST_PIP
708 | ATC_FC_MEM2MEM;
709
710 /* create the transfer */
711 desc = atc_desc_get(atchan);
712 if (!desc) {
713 dev_err(chan2dev(chan),
714 "%s: couldn't allocate our descriptor\n", __func__);
715 return NULL;
716 }
717
718 desc->lli.saddr = xt->src_start;
719 desc->lli.daddr = xt->dst_start;
720 desc->lli.ctrla = ctrla | xfer_count;
721 desc->lli.ctrlb = ctrlb;
722
723 desc->boundary = first->size >> dwidth;
724 desc->dst_hole = (dmaengine_get_dst_icg(xt, first) >> dwidth) + 1;
725 desc->src_hole = (dmaengine_get_src_icg(xt, first) >> dwidth) + 1;
726
727 desc->txd.cookie = -EBUSY;
728 desc->total_len = desc->len = len;
729 desc->tx_width = dwidth;
730
731 /* set end-of-link to the last link descriptor of list*/
732 set_desc_eol(desc);
733
734 desc->txd.flags = flags; /* client is in control of this ack */
735
736 return &desc->txd;
737}
738
739/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200740 * atc_prep_dma_memcpy - prepare a memcpy operation
741 * @chan: the channel to prepare operation on
742 * @dest: operation virtual destination address
743 * @src: operation virtual source address
744 * @len: operation length
745 * @flags: tx descriptor status flags
746 */
747static struct dma_async_tx_descriptor *
748atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
749 size_t len, unsigned long flags)
750{
751 struct at_dma_chan *atchan = to_at_dma_chan(chan);
752 struct at_desc *desc = NULL;
753 struct at_desc *first = NULL;
754 struct at_desc *prev = NULL;
755 size_t xfer_count;
756 size_t offset;
757 unsigned int src_width;
758 unsigned int dst_width;
759 u32 ctrla;
760 u32 ctrlb;
761
762 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
763 dest, src, len, flags);
764
765 if (unlikely(!len)) {
766 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
767 return NULL;
768 }
769
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200770 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200771 | ATC_SRC_ADDR_MODE_INCR
772 | ATC_DST_ADDR_MODE_INCR
773 | ATC_FC_MEM2MEM;
774
775 /*
776 * We can be a lot more clever here, but this should take care
777 * of the most common optimization.
778 */
Torsten Fleischer265567f2015-02-23 17:54:11 +0100779 src_width = dst_width = atc_get_xfer_width(src, dest, len);
780
781 ctrla = ATC_SRC_WIDTH(src_width) |
782 ATC_DST_WIDTH(dst_width);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200783
784 for (offset = 0; offset < len; offset += xfer_count << src_width) {
785 xfer_count = min_t(size_t, (len - offset) >> src_width,
786 ATC_BTSIZE_MAX);
787
788 desc = atc_desc_get(atchan);
789 if (!desc)
790 goto err_desc_get;
791
792 desc->lli.saddr = src + offset;
793 desc->lli.daddr = dest + offset;
794 desc->lli.ctrla = ctrla | xfer_count;
795 desc->lli.ctrlb = ctrlb;
796
797 desc->txd.cookie = 0;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100798 desc->len = xfer_count << src_width;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200799
Nicolas Ferree257e152011-05-06 19:56:53 +0200800 atc_desc_chain(&first, &prev, desc);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200801 }
802
803 /* First descriptor of the chain embedds additional information */
804 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100805 first->total_len = len;
806
807 /* set transfer width for the calculation of the residue */
Elen Songd088c332013-05-10 11:00:50 +0800808 first->tx_width = src_width;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100809 prev->tx_width = src_width;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200810
811 /* set end-of-link to the last link descriptor of list*/
812 set_desc_eol(desc);
813
Nicolas Ferre568f7f02011-01-12 15:39:09 +0100814 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200815
816 return &first->txd;
817
818err_desc_get:
819 atc_desc_put(atchan, first);
820 return NULL;
821}
822
Nicolas Ferre808347f2009-07-22 20:04:45 +0200823
824/**
825 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
826 * @chan: DMA channel
827 * @sgl: scatterlist to transfer to/from
828 * @sg_len: number of entries in @scatterlist
829 * @direction: DMA direction
830 * @flags: tx descriptor status flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500831 * @context: transaction context (ignored)
Nicolas Ferre808347f2009-07-22 20:04:45 +0200832 */
833static struct dma_async_tx_descriptor *
834atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530835 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500836 unsigned long flags, void *context)
Nicolas Ferre808347f2009-07-22 20:04:45 +0200837{
838 struct at_dma_chan *atchan = to_at_dma_chan(chan);
839 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100840 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200841 struct at_desc *first = NULL;
842 struct at_desc *prev = NULL;
843 u32 ctrla;
844 u32 ctrlb;
845 dma_addr_t reg;
846 unsigned int reg_width;
847 unsigned int mem_width;
848 unsigned int i;
849 struct scatterlist *sg;
850 size_t total_len = 0;
851
Nicolas Ferrecc52a102011-04-30 16:57:47 +0200852 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
853 sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530854 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Nicolas Ferre808347f2009-07-22 20:04:45 +0200855 flags);
856
857 if (unlikely(!atslave || !sg_len)) {
Nicolas Ferrec618a9b2012-09-11 17:21:44 +0200858 dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
Nicolas Ferre808347f2009-07-22 20:04:45 +0200859 return NULL;
860 }
861
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +0200862 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
863 | ATC_DCSIZE(sconfig->dst_maxburst);
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200864 ctrlb = ATC_IEN;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200865
866 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +0530867 case DMA_MEM_TO_DEV:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100868 reg_width = convert_buswidth(sconfig->dst_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200869 ctrla |= ATC_DST_WIDTH(reg_width);
870 ctrlb |= ATC_DST_ADDR_MODE_FIXED
871 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200872 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000873 | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100874 reg = sconfig->dst_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200875 for_each_sg(sgl, sg, sg_len, i) {
876 struct at_desc *desc;
877 u32 len;
878 u32 mem;
879
880 desc = atc_desc_get(atchan);
881 if (!desc)
882 goto err_desc_get;
883
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +0100884 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200885 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +0200886 if (unlikely(!len)) {
887 dev_dbg(chan2dev(chan),
888 "prep_slave_sg: sg(%d) data length is zero\n", i);
889 goto err;
890 }
Nicolas Ferre808347f2009-07-22 20:04:45 +0200891 mem_width = 2;
892 if (unlikely(mem & 3 || len & 3))
893 mem_width = 0;
894
895 desc->lli.saddr = mem;
896 desc->lli.daddr = reg;
897 desc->lli.ctrla = ctrla
898 | ATC_SRC_WIDTH(mem_width)
899 | len >> mem_width;
900 desc->lli.ctrlb = ctrlb;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100901 desc->len = len;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200902
Nicolas Ferree257e152011-05-06 19:56:53 +0200903 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200904 total_len += len;
905 }
906 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530907 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100908 reg_width = convert_buswidth(sconfig->src_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200909 ctrla |= ATC_SRC_WIDTH(reg_width);
910 ctrlb |= ATC_DST_ADDR_MODE_INCR
911 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200912 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000913 | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200914
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100915 reg = sconfig->src_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200916 for_each_sg(sgl, sg, sg_len, i) {
917 struct at_desc *desc;
918 u32 len;
919 u32 mem;
920
921 desc = atc_desc_get(atchan);
922 if (!desc)
923 goto err_desc_get;
924
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +0100925 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200926 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +0200927 if (unlikely(!len)) {
928 dev_dbg(chan2dev(chan),
929 "prep_slave_sg: sg(%d) data length is zero\n", i);
930 goto err;
931 }
Nicolas Ferre808347f2009-07-22 20:04:45 +0200932 mem_width = 2;
933 if (unlikely(mem & 3 || len & 3))
934 mem_width = 0;
935
936 desc->lli.saddr = reg;
937 desc->lli.daddr = mem;
938 desc->lli.ctrla = ctrla
939 | ATC_DST_WIDTH(mem_width)
Nicolas Ferre59a609d2010-12-13 13:48:41 +0100940 | len >> reg_width;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200941 desc->lli.ctrlb = ctrlb;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100942 desc->len = len;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200943
Nicolas Ferree257e152011-05-06 19:56:53 +0200944 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200945 total_len += len;
946 }
947 break;
948 default:
949 return NULL;
950 }
951
952 /* set end-of-link to the last link descriptor of list*/
953 set_desc_eol(prev);
954
955 /* First descriptor of the chain embedds additional information */
956 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100957 first->total_len = total_len;
958
959 /* set transfer width for the calculation of the residue */
Elen Songd088c332013-05-10 11:00:50 +0800960 first->tx_width = reg_width;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +0100961 prev->tx_width = reg_width;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200962
Nicolas Ferre568f7f02011-01-12 15:39:09 +0100963 /* first link descriptor of list is responsible of flags */
964 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferre808347f2009-07-22 20:04:45 +0200965
966 return &first->txd;
967
968err_desc_get:
969 dev_err(chan2dev(chan), "not enough descriptors available\n");
Nicolas Ferrec4567972012-09-11 17:21:45 +0200970err:
Nicolas Ferre808347f2009-07-22 20:04:45 +0200971 atc_desc_put(atchan, first);
972 return NULL;
973}
974
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200975/**
Torsten Fleischer265567f2015-02-23 17:54:11 +0100976 * atc_prep_dma_sg - prepare memory to memory scather-gather operation
977 * @chan: the channel to prepare operation on
978 * @dst_sg: destination scatterlist
979 * @dst_nents: number of destination scatterlist entries
980 * @src_sg: source scatterlist
981 * @src_nents: number of source scatterlist entries
982 * @flags: tx descriptor status flags
983 */
984static struct dma_async_tx_descriptor *
985atc_prep_dma_sg(struct dma_chan *chan,
986 struct scatterlist *dst_sg, unsigned int dst_nents,
987 struct scatterlist *src_sg, unsigned int src_nents,
988 unsigned long flags)
989{
990 struct at_dma_chan *atchan = to_at_dma_chan(chan);
991 struct at_desc *desc = NULL;
992 struct at_desc *first = NULL;
993 struct at_desc *prev = NULL;
994 unsigned int src_width;
995 unsigned int dst_width;
996 size_t xfer_count;
997 u32 ctrla;
998 u32 ctrlb;
999 size_t dst_len = 0, src_len = 0;
1000 dma_addr_t dst = 0, src = 0;
1001 size_t len = 0, total_len = 0;
1002
1003 if (unlikely(dst_nents == 0 || src_nents == 0))
1004 return NULL;
1005
1006 if (unlikely(dst_sg == NULL || src_sg == NULL))
1007 return NULL;
1008
1009 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
1010 | ATC_SRC_ADDR_MODE_INCR
1011 | ATC_DST_ADDR_MODE_INCR
1012 | ATC_FC_MEM2MEM;
1013
1014 /*
1015 * loop until there is either no more source or no more destination
1016 * scatterlist entry
1017 */
1018 while (true) {
1019
1020 /* prepare the next transfer */
1021 if (dst_len == 0) {
1022
1023 /* no more destination scatterlist entries */
1024 if (!dst_sg || !dst_nents)
1025 break;
1026
1027 dst = sg_dma_address(dst_sg);
1028 dst_len = sg_dma_len(dst_sg);
1029
1030 dst_sg = sg_next(dst_sg);
1031 dst_nents--;
1032 }
1033
1034 if (src_len == 0) {
1035
1036 /* no more source scatterlist entries */
1037 if (!src_sg || !src_nents)
1038 break;
1039
1040 src = sg_dma_address(src_sg);
1041 src_len = sg_dma_len(src_sg);
1042
1043 src_sg = sg_next(src_sg);
1044 src_nents--;
1045 }
1046
1047 len = min_t(size_t, src_len, dst_len);
1048 if (len == 0)
1049 continue;
1050
1051 /* take care for the alignment */
1052 src_width = dst_width = atc_get_xfer_width(src, dst, len);
1053
1054 ctrla = ATC_SRC_WIDTH(src_width) |
1055 ATC_DST_WIDTH(dst_width);
1056
1057 /*
1058 * The number of transfers to set up refer to the source width
1059 * that depends on the alignment.
1060 */
1061 xfer_count = len >> src_width;
1062 if (xfer_count > ATC_BTSIZE_MAX) {
1063 xfer_count = ATC_BTSIZE_MAX;
1064 len = ATC_BTSIZE_MAX << src_width;
1065 }
1066
1067 /* create the transfer */
1068 desc = atc_desc_get(atchan);
1069 if (!desc)
1070 goto err_desc_get;
1071
1072 desc->lli.saddr = src;
1073 desc->lli.daddr = dst;
1074 desc->lli.ctrla = ctrla | xfer_count;
1075 desc->lli.ctrlb = ctrlb;
1076
1077 desc->txd.cookie = 0;
1078 desc->len = len;
1079
1080 /*
1081 * Although we only need the transfer width for the first and
1082 * the last descriptor, its easier to set it to all descriptors.
1083 */
1084 desc->tx_width = src_width;
1085
1086 atc_desc_chain(&first, &prev, desc);
1087
1088 /* update the lengths and addresses for the next loop cycle */
1089 dst_len -= len;
1090 src_len -= len;
1091 dst += len;
1092 src += len;
1093
1094 total_len += len;
1095 }
1096
1097 /* First descriptor of the chain embedds additional information */
1098 first->txd.cookie = -EBUSY;
1099 first->total_len = total_len;
1100
1101 /* set end-of-link to the last link descriptor of list*/
1102 set_desc_eol(desc);
1103
1104 first->txd.flags = flags; /* client is in control of this ack */
1105
1106 return &first->txd;
1107
1108err_desc_get:
1109 atc_desc_put(atchan, first);
1110 return NULL;
1111}
1112
1113/**
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001114 * atc_dma_cyclic_check_values
1115 * Check for too big/unaligned periods and unaligned DMA buffer
1116 */
1117static int
1118atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001119 size_t period_len)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001120{
1121 if (period_len > (ATC_BTSIZE_MAX << reg_width))
1122 goto err_out;
1123 if (unlikely(period_len & ((1 << reg_width) - 1)))
1124 goto err_out;
1125 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1126 goto err_out;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001127
1128 return 0;
1129
1130err_out:
1131 return -EINVAL;
1132}
1133
1134/**
Masanari Iidad73111c2012-08-04 23:37:53 +09001135 * atc_dma_cyclic_fill_desc - Fill one period descriptor
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001136 */
1137static int
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001138atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001139 unsigned int period_index, dma_addr_t buf_addr,
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001140 unsigned int reg_width, size_t period_len,
1141 enum dma_transfer_direction direction)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001142{
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001143 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001144 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
1145 u32 ctrla;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001146
1147 /* prepare common CRTLA value */
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +02001148 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
1149 | ATC_DCSIZE(sconfig->dst_maxburst)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001150 | ATC_DST_WIDTH(reg_width)
1151 | ATC_SRC_WIDTH(reg_width)
1152 | period_len >> reg_width;
1153
1154 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +05301155 case DMA_MEM_TO_DEV:
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001156 desc->lli.saddr = buf_addr + (period_len * period_index);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001157 desc->lli.daddr = sconfig->dst_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001158 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001159 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001160 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001161 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001162 | ATC_SIF(atchan->mem_if)
1163 | ATC_DIF(atchan->per_if);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001164 desc->len = period_len;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001165 break;
1166
Vinod Kouldb8196d2011-10-13 22:34:23 +05301167 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001168 desc->lli.saddr = sconfig->src_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001169 desc->lli.daddr = buf_addr + (period_len * period_index);
1170 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001171 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001172 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +02001173 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001174 | ATC_SIF(atchan->per_if)
1175 | ATC_DIF(atchan->mem_if);
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001176 desc->len = period_len;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001177 break;
1178
1179 default:
1180 return -EINVAL;
1181 }
1182
1183 return 0;
1184}
1185
1186/**
1187 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
1188 * @chan: the DMA channel to prepare
1189 * @buf_addr: physical DMA address where the buffer starts
1190 * @buf_len: total number of bytes for the entire buffer
1191 * @period_len: number of bytes for each period
1192 * @direction: transfer direction, to or from device
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +03001193 * @flags: tx descriptor status flags
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001194 */
1195static struct dma_async_tx_descriptor *
1196atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -05001197 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02001198 unsigned long flags)
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001199{
1200 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1201 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001202 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001203 struct at_desc *first = NULL;
1204 struct at_desc *prev = NULL;
1205 unsigned long was_cyclic;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001206 unsigned int reg_width;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001207 unsigned int periods = buf_len / period_len;
1208 unsigned int i;
1209
1210 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
Vinod Kouldb8196d2011-10-13 22:34:23 +05301211 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001212 buf_addr,
1213 periods, buf_len, period_len);
1214
1215 if (unlikely(!atslave || !buf_len || !period_len)) {
1216 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
1217 return NULL;
1218 }
1219
1220 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
1221 if (was_cyclic) {
1222 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
1223 return NULL;
1224 }
1225
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001226 if (unlikely(!is_slave_direction(direction)))
1227 goto err_out;
1228
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001229 if (sconfig->direction == DMA_MEM_TO_DEV)
1230 reg_width = convert_buswidth(sconfig->dst_addr_width);
1231 else
1232 reg_width = convert_buswidth(sconfig->src_addr_width);
1233
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001234 /* Check for too big/unaligned periods and unaligned DMA buffer */
Andy Shevchenko0e7264c2013-01-10 10:52:57 +02001235 if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001236 goto err_out;
1237
1238 /* build cyclic linked list */
1239 for (i = 0; i < periods; i++) {
1240 struct at_desc *desc;
1241
1242 desc = atc_desc_get(atchan);
1243 if (!desc)
1244 goto err_desc_get;
1245
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001246 if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
1247 reg_width, period_len, direction))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001248 goto err_desc_get;
1249
1250 atc_desc_chain(&first, &prev, desc);
1251 }
1252
1253 /* lets make a cyclic list */
1254 prev->lli.dscr = first->txd.phys;
1255
1256 /* First descriptor of the chain embedds additional information */
1257 first->txd.cookie = -EBUSY;
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001258 first->total_len = buf_len;
Elen Songd088c332013-05-10 11:00:50 +08001259 first->tx_width = reg_width;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001260
1261 return &first->txd;
1262
1263err_desc_get:
1264 dev_err(chan2dev(chan), "not enough descriptors available\n");
1265 atc_desc_put(atchan, first);
1266err_out:
1267 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1268 return NULL;
1269}
1270
Maxime Ripard4facfe72014-11-17 14:42:06 +01001271static int atc_config(struct dma_chan *chan,
1272 struct dma_slave_config *sconfig)
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001273{
1274 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1275
Maxime Ripard4facfe72014-11-17 14:42:06 +01001276 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1277
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001278 /* Check if it is chan is configured for slave transfers */
1279 if (!chan->private)
1280 return -EINVAL;
1281
1282 memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
1283
1284 convert_burst(&atchan->dma_sconfig.src_maxburst);
1285 convert_burst(&atchan->dma_sconfig.dst_maxburst);
1286
1287 return 0;
1288}
1289
Maxime Ripard4facfe72014-11-17 14:42:06 +01001290static int atc_pause(struct dma_chan *chan)
Nicolas Ferre808347f2009-07-22 20:04:45 +02001291{
1292 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1293 struct at_dma *atdma = to_at_dma(chan->device);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001294 int chan_id = atchan->chan_common.chan_id;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001295 unsigned long flags;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001296
Nicolas Ferre808347f2009-07-22 20:04:45 +02001297 LIST_HEAD(list);
1298
Maxime Ripard4facfe72014-11-17 14:42:06 +01001299 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001300
Maxime Ripard4facfe72014-11-17 14:42:06 +01001301 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001302
Maxime Ripard4facfe72014-11-17 14:42:06 +01001303 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
1304 set_bit(ATC_IS_PAUSED, &atchan->status);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001305
Maxime Ripard4facfe72014-11-17 14:42:06 +01001306 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001307
Maxime Ripard4facfe72014-11-17 14:42:06 +01001308 return 0;
1309}
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001310
Maxime Ripard4facfe72014-11-17 14:42:06 +01001311static int atc_resume(struct dma_chan *chan)
1312{
1313 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1314 struct at_dma *atdma = to_at_dma(chan->device);
1315 int chan_id = atchan->chan_common.chan_id;
1316 unsigned long flags;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001317
Maxime Ripard4facfe72014-11-17 14:42:06 +01001318 LIST_HEAD(list);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001319
Maxime Ripard4facfe72014-11-17 14:42:06 +01001320 dev_vdbg(chan2dev(chan), "%s\n", __func__);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001321
Maxime Ripard4facfe72014-11-17 14:42:06 +01001322 if (!atc_chan_is_paused(atchan))
1323 return 0;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001324
Maxime Ripard4facfe72014-11-17 14:42:06 +01001325 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001326
Maxime Ripard4facfe72014-11-17 14:42:06 +01001327 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
1328 clear_bit(ATC_IS_PAUSED, &atchan->status);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001329
Maxime Ripard4facfe72014-11-17 14:42:06 +01001330 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001331
Maxime Ripard4facfe72014-11-17 14:42:06 +01001332 return 0;
1333}
1334
1335static int atc_terminate_all(struct dma_chan *chan)
1336{
1337 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1338 struct at_dma *atdma = to_at_dma(chan->device);
1339 int chan_id = atchan->chan_common.chan_id;
1340 struct at_desc *desc, *_desc;
1341 unsigned long flags;
1342
1343 LIST_HEAD(list);
1344
1345 dev_vdbg(chan2dev(chan), "%s\n", __func__);
1346
1347 /*
1348 * This is only called when something went wrong elsewhere, so
1349 * we don't really care about the data. Just disable the
1350 * channel. We still have to poll the channel enable bit due
1351 * to AHB/HSB limitations.
1352 */
1353 spin_lock_irqsave(&atchan->lock, flags);
1354
1355 /* disabling channel: must also remove suspend state */
1356 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
1357
1358 /* confirm that this channel is disabled */
1359 while (dma_readl(atdma, CHSR) & atchan->mask)
1360 cpu_relax();
1361
1362 /* active_list entries will end up before queued entries */
1363 list_splice_init(&atchan->queue, &list);
1364 list_splice_init(&atchan->active_list, &list);
1365
1366 /* Flush all pending and queued descriptors */
1367 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1368 atc_chain_complete(atchan, desc);
1369
1370 clear_bit(ATC_IS_PAUSED, &atchan->status);
1371 /* if channel dedicated to cyclic operations, free it */
1372 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1373
1374 spin_unlock_irqrestore(&atchan->lock, flags);
Yong Wangb0ebeb92010-08-05 10:40:08 +08001375
Linus Walleijc3635c72010-03-26 16:44:01 -07001376 return 0;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001377}
1378
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001379/**
Linus Walleij07934482010-03-26 16:50:49 -07001380 * atc_tx_status - poll for transaction completion
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001381 * @chan: DMA channel
1382 * @cookie: transaction identifier to check status of
Linus Walleij07934482010-03-26 16:50:49 -07001383 * @txstate: if not %NULL updated with transaction state
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001384 *
Linus Walleij07934482010-03-26 16:50:49 -07001385 * If @txstate is passed in, upon return it reflect the driver
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001386 * internal state and can be used with dma_async_is_complete() to check
1387 * the status of multiple cookies without re-checking hardware state.
1388 */
1389static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -07001390atc_tx_status(struct dma_chan *chan,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001391 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -07001392 struct dma_tx_state *txstate)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001393{
1394 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001395 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001396 enum dma_status ret;
Elen Songd48de6f2013-05-10 11:01:46 +08001397 int bytes = 0;
1398
1399 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul6d203d12013-10-16 13:34:35 +05301400 if (ret == DMA_COMPLETE)
Elen Songd48de6f2013-05-10 11:01:46 +08001401 return ret;
1402 /*
1403 * There's no point calculating the residue if there's
1404 * no txstate to store the value.
1405 */
1406 if (!txstate)
1407 return DMA_ERROR;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001408
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001409 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001410
Elen Songd48de6f2013-05-10 11:01:46 +08001411 /* Get number of bytes left in the active transactions */
Torsten Fleischerbdf6c792015-02-23 17:54:10 +01001412 bytes = atc_get_bytes_left(chan, cookie);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00001413
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001414 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001415
Elen Songd48de6f2013-05-10 11:01:46 +08001416 if (unlikely(bytes < 0)) {
1417 dev_vdbg(chan2dev(chan), "get residual bytes error\n");
1418 return DMA_ERROR;
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001419 } else {
Elen Songd48de6f2013-05-10 11:01:46 +08001420 dma_set_residue(txstate, bytes);
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001421 }
Nicolas Ferre543aabc2011-05-06 19:56:51 +02001422
Elen Songd48de6f2013-05-10 11:01:46 +08001423 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
1424 ret, cookie, bytes);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001425
1426 return ret;
1427}
1428
1429/**
1430 * atc_issue_pending - try to finish work
1431 * @chan: target DMA channel
1432 */
1433static void atc_issue_pending(struct dma_chan *chan)
1434{
1435 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001436 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001437
1438 dev_vdbg(chan2dev(chan), "issue_pending\n");
1439
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001440 /* Not needed for cyclic transfers */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001441 if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001442 return;
1443
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001444 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochesd202f052013-04-18 09:52:59 +02001445 atc_advance_work(atchan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001446 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001447}
1448
1449/**
1450 * atc_alloc_chan_resources - allocate resources for DMA channel
1451 * @chan: allocate descriptor resources for this channel
1452 * @client: current client requesting the channel be ready for requests
1453 *
1454 * return - the number of allocated descriptors
1455 */
1456static int atc_alloc_chan_resources(struct dma_chan *chan)
1457{
1458 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1459 struct at_dma *atdma = to_at_dma(chan->device);
1460 struct at_desc *desc;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001461 struct at_dma_slave *atslave;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001462 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001463 int i;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001464 u32 cfg;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001465 LIST_HEAD(tmp_list);
1466
1467 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1468
1469 /* ASSERT: channel is idle */
1470 if (atc_chan_is_enabled(atchan)) {
1471 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1472 return -EIO;
1473 }
1474
Nicolas Ferre808347f2009-07-22 20:04:45 +02001475 cfg = ATC_DEFAULT_CFG;
1476
1477 atslave = chan->private;
1478 if (atslave) {
1479 /*
1480 * We need controller-specific data to set up slave
1481 * transfers.
1482 */
1483 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
1484
Nicolas Ferreea7e7902013-05-10 15:19:13 +02001485 /* if cfg configuration specified take it instead of default */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001486 if (atslave->cfg)
1487 cfg = atslave->cfg;
1488 }
1489
1490 /* have we already been set up?
1491 * reconfigure channel but no need to reallocate descriptors */
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001492 if (!list_empty(&atchan->free_list))
1493 return atchan->descs_allocated;
1494
1495 /* Allocate initial pool of descriptors */
1496 for (i = 0; i < init_nr_desc_per_channel; i++) {
1497 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
1498 if (!desc) {
1499 dev_err(atdma->dma_common.dev,
1500 "Only %d initial descriptors\n", i);
1501 break;
1502 }
1503 list_add_tail(&desc->desc_node, &tmp_list);
1504 }
1505
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001506 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001507 atchan->descs_allocated = i;
1508 list_splice(&tmp_list, &atchan->free_list);
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001509 dma_cookie_init(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001510 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001511
1512 /* channel parameters */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001513 channel_writel(atchan, CFG, cfg);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001514
1515 dev_dbg(chan2dev(chan),
1516 "alloc_chan_resources: allocated %d descriptors\n",
1517 atchan->descs_allocated);
1518
1519 return atchan->descs_allocated;
1520}
1521
1522/**
1523 * atc_free_chan_resources - free all channel resources
1524 * @chan: DMA channel
1525 */
1526static void atc_free_chan_resources(struct dma_chan *chan)
1527{
1528 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1529 struct at_dma *atdma = to_at_dma(chan->device);
1530 struct at_desc *desc, *_desc;
1531 LIST_HEAD(list);
1532
1533 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
1534 atchan->descs_allocated);
1535
1536 /* ASSERT: channel is idle */
1537 BUG_ON(!list_empty(&atchan->active_list));
1538 BUG_ON(!list_empty(&atchan->queue));
1539 BUG_ON(atc_chan_is_enabled(atchan));
1540
1541 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
1542 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1543 list_del(&desc->desc_node);
1544 /* free link descriptor */
1545 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
1546 }
1547 list_splice_init(&atchan->free_list, &list);
1548 atchan->descs_allocated = 0;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001549 atchan->status = 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001550
1551 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1552}
1553
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001554#ifdef CONFIG_OF
1555static bool at_dma_filter(struct dma_chan *chan, void *slave)
1556{
1557 struct at_dma_slave *atslave = slave;
1558
1559 if (atslave->dma_dev == chan->device->dev) {
1560 chan->private = atslave;
1561 return true;
1562 } else {
1563 return false;
1564 }
1565}
1566
1567static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1568 struct of_dma *of_dma)
1569{
1570 struct dma_chan *chan;
1571 struct at_dma_chan *atchan;
1572 struct at_dma_slave *atslave;
1573 dma_cap_mask_t mask;
1574 unsigned int per_id;
1575 struct platform_device *dmac_pdev;
1576
1577 if (dma_spec->args_count != 2)
1578 return NULL;
1579
1580 dmac_pdev = of_find_device_by_node(dma_spec->np);
1581
1582 dma_cap_zero(mask);
1583 dma_cap_set(DMA_SLAVE, mask);
1584
1585 atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
1586 if (!atslave)
1587 return NULL;
Ludovic Desroches62971b22013-06-13 10:39:39 +02001588
1589 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001590 /*
1591 * We can fill both SRC_PER and DST_PER, one of these fields will be
1592 * ignored depending on DMA transfer direction.
1593 */
Ludovic Desroches62971b22013-06-13 10:39:39 +02001594 per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
1595 atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
Nicolas Ferre6c227702013-05-10 15:19:15 +02001596 | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
Ludovic Desroches62971b22013-06-13 10:39:39 +02001597 /*
1598 * We have to translate the value we get from the device tree since
1599 * the half FIFO configuration value had to be 0 to keep backward
1600 * compatibility.
1601 */
1602 switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
1603 case AT91_DMA_CFG_FIFOCFG_ALAP:
1604 atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
1605 break;
1606 case AT91_DMA_CFG_FIFOCFG_ASAP:
1607 atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
1608 break;
1609 case AT91_DMA_CFG_FIFOCFG_HALF:
1610 default:
1611 atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
1612 }
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001613 atslave->dma_dev = &dmac_pdev->dev;
1614
1615 chan = dma_request_channel(mask, at_dma_filter, atslave);
1616 if (!chan)
1617 return NULL;
1618
1619 atchan = to_at_dma_chan(chan);
1620 atchan->per_if = dma_spec->args[0] & 0xff;
1621 atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
1622
1623 return chan;
1624}
1625#else
1626static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1627 struct of_dma *of_dma)
1628{
1629 return NULL;
1630}
1631#endif
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001632
1633/*-- Module Management -----------------------------------------------*/
1634
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001635/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1636static struct at_dma_platform_data at91sam9rl_config = {
1637 .nr_channels = 2,
1638};
1639static struct at_dma_platform_data at91sam9g45_config = {
1640 .nr_channels = 8,
1641};
1642
Nicolas Ferrec5115952011-10-17 14:56:41 +02001643#if defined(CONFIG_OF)
1644static const struct of_device_id atmel_dma_dt_ids[] = {
1645 {
1646 .compatible = "atmel,at91sam9rl-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001647 .data = &at91sam9rl_config,
Nicolas Ferrec5115952011-10-17 14:56:41 +02001648 }, {
1649 .compatible = "atmel,at91sam9g45-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001650 .data = &at91sam9g45_config,
Nicolas Ferredcc81732011-11-22 11:55:53 +01001651 }, {
1652 /* sentinel */
1653 }
Nicolas Ferrec5115952011-10-17 14:56:41 +02001654};
1655
1656MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1657#endif
1658
Nicolas Ferre0ab88a02011-11-22 11:55:52 +01001659static const struct platform_device_id atdma_devtypes[] = {
Nicolas Ferre67348452011-10-17 14:56:40 +02001660 {
1661 .name = "at91sam9rl_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001662 .driver_data = (unsigned long) &at91sam9rl_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001663 }, {
1664 .name = "at91sam9g45_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001665 .driver_data = (unsigned long) &at91sam9g45_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001666 }, {
1667 /* sentinel */
1668 }
1669};
1670
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001671static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001672 struct platform_device *pdev)
Nicolas Ferrec5115952011-10-17 14:56:41 +02001673{
1674 if (pdev->dev.of_node) {
1675 const struct of_device_id *match;
1676 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1677 if (match == NULL)
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001678 return NULL;
1679 return match->data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001680 }
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001681 return (struct at_dma_platform_data *)
1682 platform_get_device_id(pdev)->driver_data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001683}
1684
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001685/**
1686 * at_dma_off - disable DMA controller
1687 * @atdma: the Atmel HDAMC device
1688 */
1689static void at_dma_off(struct at_dma *atdma)
1690{
1691 dma_writel(atdma, EN, 0);
1692
1693 /* disable all interrupts */
1694 dma_writel(atdma, EBCIDR, -1L);
1695
1696 /* confirm that all channels are disabled */
1697 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1698 cpu_relax();
1699}
1700
1701static int __init at_dma_probe(struct platform_device *pdev)
1702{
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001703 struct resource *io;
1704 struct at_dma *atdma;
1705 size_t size;
1706 int irq;
1707 int err;
1708 int i;
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001709 const struct at_dma_platform_data *plat_dat;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001710
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001711 /* setup platform data for each SoC */
1712 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
Torsten Fleischer265567f2015-02-23 17:54:11 +01001713 dma_cap_set(DMA_SG, at91sam9rl_config.cap_mask);
Maxime Ripard5abecfa2015-05-27 16:01:53 +02001714 dma_cap_set(DMA_INTERLEAVE, at91sam9g45_config.cap_mask);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001715 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
1716 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
Torsten Fleischer265567f2015-02-23 17:54:11 +01001717 dma_cap_set(DMA_SG, at91sam9g45_config.cap_mask);
Nicolas Ferre67348452011-10-17 14:56:40 +02001718
1719 /* get DMA parameters from controller type */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001720 plat_dat = at_dma_get_driver_data(pdev);
1721 if (!plat_dat)
1722 return -ENODEV;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001723
1724 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1725 if (!io)
1726 return -EINVAL;
1727
1728 irq = platform_get_irq(pdev, 0);
1729 if (irq < 0)
1730 return irq;
1731
1732 size = sizeof(struct at_dma);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001733 size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001734 atdma = kzalloc(size, GFP_KERNEL);
1735 if (!atdma)
1736 return -ENOMEM;
1737
Nicolas Ferre67348452011-10-17 14:56:40 +02001738 /* discover transaction capabilities */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001739 atdma->dma_common.cap_mask = plat_dat->cap_mask;
1740 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001741
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07001742 size = resource_size(io);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001743 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1744 err = -EBUSY;
1745 goto err_kfree;
1746 }
1747
1748 atdma->regs = ioremap(io->start, size);
1749 if (!atdma->regs) {
1750 err = -ENOMEM;
1751 goto err_release_r;
1752 }
1753
1754 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1755 if (IS_ERR(atdma->clk)) {
1756 err = PTR_ERR(atdma->clk);
1757 goto err_clk;
1758 }
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001759 err = clk_prepare_enable(atdma->clk);
1760 if (err)
1761 goto err_clk_prepare;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001762
1763 /* force dma off, just in case */
1764 at_dma_off(atdma);
1765
1766 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1767 if (err)
1768 goto err_irq;
1769
1770 platform_set_drvdata(pdev, atdma);
1771
1772 /* create a pool of consistent memory blocks for hardware descriptors */
1773 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
1774 &pdev->dev, sizeof(struct at_desc),
1775 4 /* word alignment */, 0);
1776 if (!atdma->dma_desc_pool) {
1777 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1778 err = -ENOMEM;
1779 goto err_pool_create;
1780 }
1781
1782 /* clear any pending interrupt */
1783 while (dma_readl(atdma, EBCISR))
1784 cpu_relax();
1785
1786 /* initialize channels related values */
1787 INIT_LIST_HEAD(&atdma->dma_common.channels);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001788 for (i = 0; i < plat_dat->nr_channels; i++) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001789 struct at_dma_chan *atchan = &atdma->chan[i];
1790
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001791 atchan->mem_if = AT_DMA_MEM_IF;
1792 atchan->per_if = AT_DMA_PER_IF;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001793 atchan->chan_common.device = &atdma->dma_common;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001794 dma_cookie_init(&atchan->chan_common);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001795 list_add_tail(&atchan->chan_common.device_node,
1796 &atdma->dma_common.channels);
1797
1798 atchan->ch_regs = atdma->regs + ch_regs(i);
1799 spin_lock_init(&atchan->lock);
1800 atchan->mask = 1 << i;
1801
1802 INIT_LIST_HEAD(&atchan->active_list);
1803 INIT_LIST_HEAD(&atchan->queue);
1804 INIT_LIST_HEAD(&atchan->free_list);
1805
1806 tasklet_init(&atchan->tasklet, atc_tasklet,
1807 (unsigned long)atchan);
Nikolaus Vossbda3a472012-01-17 10:28:33 +01001808 atc_enable_chan_irq(atdma, i);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001809 }
1810
1811 /* set base routines */
1812 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
1813 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07001814 atdma->dma_common.device_tx_status = atc_tx_status;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001815 atdma->dma_common.device_issue_pending = atc_issue_pending;
1816 atdma->dma_common.dev = &pdev->dev;
1817
1818 /* set prep routines based on capability */
Maxime Ripard5abecfa2015-05-27 16:01:53 +02001819 if (dma_has_cap(DMA_INTERLEAVE, atdma->dma_common.cap_mask))
1820 atdma->dma_common.device_prep_interleaved_dma = atc_prep_dma_interleaved;
1821
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001822 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
1823 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
1824
Nicolas Ferred7db8082011-08-05 11:43:44 +00001825 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
Nicolas Ferre808347f2009-07-22 20:04:45 +02001826 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
Nicolas Ferred7db8082011-08-05 11:43:44 +00001827 /* controller can do slave DMA: can trigger cyclic transfers */
1828 dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001829 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
Maxime Ripard4facfe72014-11-17 14:42:06 +01001830 atdma->dma_common.device_config = atc_config;
1831 atdma->dma_common.device_pause = atc_pause;
1832 atdma->dma_common.device_resume = atc_resume;
1833 atdma->dma_common.device_terminate_all = atc_terminate_all;
Ludovic Desroches816070e2015-01-06 17:36:26 +01001834 atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS;
1835 atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS;
1836 atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1837 atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
Nicolas Ferred7db8082011-08-05 11:43:44 +00001838 }
Nicolas Ferre808347f2009-07-22 20:04:45 +02001839
Torsten Fleischer265567f2015-02-23 17:54:11 +01001840 if (dma_has_cap(DMA_SG, atdma->dma_common.cap_mask))
1841 atdma->dma_common.device_prep_dma_sg = atc_prep_dma_sg;
1842
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001843 dma_writel(atdma, EN, AT_DMA_ENABLE);
1844
Torsten Fleischer265567f2015-02-23 17:54:11 +01001845 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s%s), %d channels\n",
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001846 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1847 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
Torsten Fleischer265567f2015-02-23 17:54:11 +01001848 dma_has_cap(DMA_SG, atdma->dma_common.cap_mask) ? "sg-cpy " : "",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001849 plat_dat->nr_channels);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001850
1851 dma_async_device_register(&atdma->dma_common);
1852
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001853 /*
1854 * Do not return an error if the dmac node is not present in order to
1855 * not break the existing way of requesting channel with
1856 * dma_request_channel().
1857 */
1858 if (pdev->dev.of_node) {
1859 err = of_dma_controller_register(pdev->dev.of_node,
1860 at_dma_xlate, atdma);
1861 if (err) {
1862 dev_err(&pdev->dev, "could not register of_dma_controller\n");
1863 goto err_of_dma_controller_register;
1864 }
1865 }
1866
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001867 return 0;
1868
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001869err_of_dma_controller_register:
1870 dma_async_device_unregister(&atdma->dma_common);
1871 dma_pool_destroy(atdma->dma_desc_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001872err_pool_create:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001873 free_irq(platform_get_irq(pdev, 0), atdma);
1874err_irq:
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001875 clk_disable_unprepare(atdma->clk);
1876err_clk_prepare:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001877 clk_put(atdma->clk);
1878err_clk:
1879 iounmap(atdma->regs);
1880 atdma->regs = NULL;
1881err_release_r:
1882 release_mem_region(io->start, size);
1883err_kfree:
1884 kfree(atdma);
1885 return err;
1886}
1887
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001888static int at_dma_remove(struct platform_device *pdev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001889{
1890 struct at_dma *atdma = platform_get_drvdata(pdev);
1891 struct dma_chan *chan, *_chan;
1892 struct resource *io;
1893
1894 at_dma_off(atdma);
1895 dma_async_device_unregister(&atdma->dma_common);
1896
1897 dma_pool_destroy(atdma->dma_desc_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001898 free_irq(platform_get_irq(pdev, 0), atdma);
1899
1900 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1901 device_node) {
1902 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1903
1904 /* Disable interrupts */
Nikolaus Vossbda3a472012-01-17 10:28:33 +01001905 atc_disable_chan_irq(atdma, chan->chan_id);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001906
1907 tasklet_kill(&atchan->tasklet);
1908 list_del(&chan->device_node);
1909 }
1910
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001911 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001912 clk_put(atdma->clk);
1913
1914 iounmap(atdma->regs);
1915 atdma->regs = NULL;
1916
1917 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07001918 release_mem_region(io->start, resource_size(io));
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001919
1920 kfree(atdma);
1921
1922 return 0;
1923}
1924
1925static void at_dma_shutdown(struct platform_device *pdev)
1926{
1927 struct at_dma *atdma = platform_get_drvdata(pdev);
1928
1929 at_dma_off(platform_get_drvdata(pdev));
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001930 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001931}
1932
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001933static int at_dma_prepare(struct device *dev)
1934{
1935 struct platform_device *pdev = to_platform_device(dev);
1936 struct at_dma *atdma = platform_get_drvdata(pdev);
1937 struct dma_chan *chan, *_chan;
1938
1939 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1940 device_node) {
1941 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1942 /* wait for transaction completion (except in cyclic case) */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001943 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001944 return -EAGAIN;
1945 }
1946 return 0;
1947}
1948
1949static void atc_suspend_cyclic(struct at_dma_chan *atchan)
1950{
1951 struct dma_chan *chan = &atchan->chan_common;
1952
1953 /* Channel should be paused by user
1954 * do it anyway even if it is not done already */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001955 if (!atc_chan_is_paused(atchan)) {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001956 dev_warn(chan2dev(chan),
1957 "cyclic channel not paused, should be done by channel user\n");
Maxime Ripard4facfe72014-11-17 14:42:06 +01001958 atc_pause(chan);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001959 }
1960
1961 /* now preserve additional data for cyclic operations */
1962 /* next descriptor address in the cyclic list */
1963 atchan->save_dscr = channel_readl(atchan, DSCR);
1964
1965 vdbg_dump_regs(atchan);
1966}
1967
Dan Williams33f82d12009-09-10 00:06:44 +02001968static int at_dma_suspend_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001969{
Dan Williams33f82d12009-09-10 00:06:44 +02001970 struct platform_device *pdev = to_platform_device(dev);
1971 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001972 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001973
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001974 /* preserve data */
1975 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1976 device_node) {
1977 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1978
Nicolas Ferre3c477482011-07-25 21:09:23 +00001979 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001980 atc_suspend_cyclic(atchan);
1981 atchan->save_cfg = channel_readl(atchan, CFG);
1982 }
1983 atdma->save_imr = dma_readl(atdma, EBCIMR);
1984
1985 /* disable DMA controller */
1986 at_dma_off(atdma);
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001987 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001988 return 0;
1989}
1990
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001991static void atc_resume_cyclic(struct at_dma_chan *atchan)
1992{
1993 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
1994
1995 /* restore channel status for cyclic descriptors list:
1996 * next descriptor in the cyclic list at the time of suspend */
1997 channel_writel(atchan, SADDR, 0);
1998 channel_writel(atchan, DADDR, 0);
1999 channel_writel(atchan, CTRLA, 0);
2000 channel_writel(atchan, CTRLB, 0);
2001 channel_writel(atchan, DSCR, atchan->save_dscr);
2002 dma_writel(atdma, CHER, atchan->mask);
2003
2004 /* channel pause status should be removed by channel user
2005 * We cannot take the initiative to do it here */
2006
2007 vdbg_dump_regs(atchan);
2008}
2009
Dan Williams33f82d12009-09-10 00:06:44 +02002010static int at_dma_resume_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002011{
Dan Williams33f82d12009-09-10 00:06:44 +02002012 struct platform_device *pdev = to_platform_device(dev);
2013 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002014 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002015
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002016 /* bring back DMA controller */
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02002017 clk_prepare_enable(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002018 dma_writel(atdma, EN, AT_DMA_ENABLE);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002019
2020 /* clear any pending interrupt */
2021 while (dma_readl(atdma, EBCISR))
2022 cpu_relax();
2023
2024 /* restore saved data */
2025 dma_writel(atdma, EBCIER, atdma->save_imr);
2026 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
2027 device_node) {
2028 struct at_dma_chan *atchan = to_at_dma_chan(chan);
2029
2030 channel_writel(atchan, CFG, atchan->save_cfg);
Nicolas Ferre3c477482011-07-25 21:09:23 +00002031 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002032 atc_resume_cyclic(atchan);
2033 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002034 return 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002035}
2036
Alexey Dobriyan47145212009-12-14 18:00:08 -08002037static const struct dev_pm_ops at_dma_dev_pm_ops = {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00002038 .prepare = at_dma_prepare,
Dan Williams33f82d12009-09-10 00:06:44 +02002039 .suspend_noirq = at_dma_suspend_noirq,
2040 .resume_noirq = at_dma_resume_noirq,
2041};
2042
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002043static struct platform_driver at_dma_driver = {
Maxin B. John1d1bbd32013-02-20 02:07:04 +02002044 .remove = at_dma_remove,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002045 .shutdown = at_dma_shutdown,
Nicolas Ferre67348452011-10-17 14:56:40 +02002046 .id_table = atdma_devtypes,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002047 .driver = {
2048 .name = "at_hdmac",
Dan Williams33f82d12009-09-10 00:06:44 +02002049 .pm = &at_dma_dev_pm_ops,
Nicolas Ferrec5115952011-10-17 14:56:41 +02002050 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002051 },
2052};
2053
2054static int __init at_dma_init(void)
2055{
2056 return platform_driver_probe(&at_dma_driver, at_dma_probe);
2057}
Eric Xu93d0bec2011-01-12 15:39:08 +01002058subsys_initcall(at_dma_init);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02002059
2060static void __exit at_dma_exit(void)
2061{
2062 platform_driver_unregister(&at_dma_driver);
2063}
2064module_exit(at_dma_exit);
2065
2066MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
2067MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
2068MODULE_LICENSE("GPL");
2069MODULE_ALIAS("platform:at_hdmac");