Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 1 | /* |
| 2 | * include/asm-powerpc/ucc_fast.h |
| 3 | * |
| 4 | * Internal header file for UCC FAST unit routines. |
| 5 | * |
| 6 | * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved. |
| 7 | * |
| 8 | * Authors: Shlomi Gridish <gridish@freescale.com> |
| 9 | * Li Yang <leoli@freescale.com> |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify it |
| 12 | * under the terms of the GNU General Public License as published by the |
| 13 | * Free Software Foundation; either version 2 of the License, or (at your |
| 14 | * option) any later version. |
| 15 | */ |
| 16 | #ifndef __UCC_FAST_H__ |
| 17 | #define __UCC_FAST_H__ |
| 18 | |
| 19 | #include <linux/kernel.h> |
| 20 | |
| 21 | #include <asm/immap_qe.h> |
| 22 | #include <asm/qe.h> |
| 23 | |
| 24 | #include "ucc.h" |
| 25 | |
| 26 | /* Receive BD's status */ |
| 27 | #define R_E 0x80000000 /* buffer empty */ |
| 28 | #define R_W 0x20000000 /* wrap bit */ |
| 29 | #define R_I 0x10000000 /* interrupt on reception */ |
| 30 | #define R_L 0x08000000 /* last */ |
| 31 | #define R_F 0x04000000 /* first */ |
| 32 | |
| 33 | /* transmit BD's status */ |
| 34 | #define T_R 0x80000000 /* ready bit */ |
| 35 | #define T_W 0x20000000 /* wrap bit */ |
| 36 | #define T_I 0x10000000 /* interrupt on completion */ |
| 37 | #define T_L 0x08000000 /* last */ |
| 38 | |
| 39 | /* Rx Data buffer must be 4 bytes aligned in most cases */ |
| 40 | #define UCC_FAST_RX_ALIGN 4 |
| 41 | #define UCC_FAST_MRBLR_ALIGNMENT 4 |
| 42 | #define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8 |
| 43 | |
| 44 | /* Sizes */ |
| 45 | #define UCC_FAST_URFS_MIN_VAL 0x88 |
| 46 | #define UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR 8 |
| 47 | |
| 48 | /* ucc_fast_channel_protocol_mode - UCC FAST mode */ |
| 49 | enum ucc_fast_channel_protocol_mode { |
| 50 | UCC_FAST_PROTOCOL_MODE_HDLC = 0x00000000, |
| 51 | UCC_FAST_PROTOCOL_MODE_RESERVED01 = 0x00000001, |
| 52 | UCC_FAST_PROTOCOL_MODE_RESERVED_QMC = 0x00000002, |
| 53 | UCC_FAST_PROTOCOL_MODE_RESERVED02 = 0x00000003, |
| 54 | UCC_FAST_PROTOCOL_MODE_RESERVED_UART = 0x00000004, |
| 55 | UCC_FAST_PROTOCOL_MODE_RESERVED03 = 0x00000005, |
| 56 | UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_1 = 0x00000006, |
| 57 | UCC_FAST_PROTOCOL_MODE_RESERVED_EX_MAC_2 = 0x00000007, |
| 58 | UCC_FAST_PROTOCOL_MODE_RESERVED_BISYNC = 0x00000008, |
| 59 | UCC_FAST_PROTOCOL_MODE_RESERVED04 = 0x00000009, |
| 60 | UCC_FAST_PROTOCOL_MODE_ATM = 0x0000000A, |
| 61 | UCC_FAST_PROTOCOL_MODE_RESERVED05 = 0x0000000B, |
| 62 | UCC_FAST_PROTOCOL_MODE_ETHERNET = 0x0000000C, |
| 63 | UCC_FAST_PROTOCOL_MODE_RESERVED06 = 0x0000000D, |
| 64 | UCC_FAST_PROTOCOL_MODE_POS = 0x0000000E, |
| 65 | UCC_FAST_PROTOCOL_MODE_RESERVED07 = 0x0000000F |
| 66 | }; |
| 67 | |
| 68 | /* ucc_fast_transparent_txrx - UCC Fast Transparent TX & RX */ |
| 69 | enum ucc_fast_transparent_txrx { |
| 70 | UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL = 0x00000000, |
| 71 | UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_TRANSPARENT = 0x18000000 |
| 72 | }; |
| 73 | |
| 74 | /* UCC fast diagnostic mode */ |
| 75 | enum ucc_fast_diag_mode { |
| 76 | UCC_FAST_DIAGNOSTIC_NORMAL = 0x0, |
| 77 | UCC_FAST_DIAGNOSTIC_LOCAL_LOOP_BACK = 0x40000000, |
| 78 | UCC_FAST_DIAGNOSTIC_AUTO_ECHO = 0x80000000, |
| 79 | UCC_FAST_DIAGNOSTIC_LOOP_BACK_AND_ECHO = 0xC0000000 |
| 80 | }; |
| 81 | |
| 82 | /* UCC fast Sync length (transparent mode only) */ |
| 83 | enum ucc_fast_sync_len { |
| 84 | UCC_FAST_SYNC_LEN_NOT_USED = 0x0, |
| 85 | UCC_FAST_SYNC_LEN_AUTOMATIC = 0x00004000, |
| 86 | UCC_FAST_SYNC_LEN_8_BIT = 0x00008000, |
| 87 | UCC_FAST_SYNC_LEN_16_BIT = 0x0000C000 |
| 88 | }; |
| 89 | |
| 90 | /* UCC fast RTS mode */ |
| 91 | enum ucc_fast_ready_to_send { |
| 92 | UCC_FAST_SEND_IDLES_BETWEEN_FRAMES = 0x00000000, |
| 93 | UCC_FAST_SEND_FLAGS_BETWEEN_FRAMES = 0x00002000 |
| 94 | }; |
| 95 | |
| 96 | /* UCC fast receiver decoding mode */ |
| 97 | enum ucc_fast_rx_decoding_method { |
| 98 | UCC_FAST_RX_ENCODING_NRZ = 0x00000000, |
| 99 | UCC_FAST_RX_ENCODING_NRZI = 0x00000800, |
| 100 | UCC_FAST_RX_ENCODING_RESERVED0 = 0x00001000, |
| 101 | UCC_FAST_RX_ENCODING_RESERVED1 = 0x00001800 |
| 102 | }; |
| 103 | |
| 104 | /* UCC fast transmitter encoding mode */ |
| 105 | enum ucc_fast_tx_encoding_method { |
| 106 | UCC_FAST_TX_ENCODING_NRZ = 0x00000000, |
| 107 | UCC_FAST_TX_ENCODING_NRZI = 0x00000100, |
| 108 | UCC_FAST_TX_ENCODING_RESERVED0 = 0x00000200, |
| 109 | UCC_FAST_TX_ENCODING_RESERVED1 = 0x00000300 |
| 110 | }; |
| 111 | |
| 112 | /* UCC fast CRC length */ |
| 113 | enum ucc_fast_transparent_tcrc { |
| 114 | UCC_FAST_16_BIT_CRC = 0x00000000, |
| 115 | UCC_FAST_CRC_RESERVED0 = 0x00000040, |
| 116 | UCC_FAST_32_BIT_CRC = 0x00000080, |
| 117 | UCC_FAST_CRC_RESERVED1 = 0x000000C0 |
| 118 | }; |
| 119 | |
| 120 | /* Fast UCC initialization structure */ |
| 121 | struct ucc_fast_info { |
| 122 | int ucc_num; |
| 123 | enum qe_clock rx_clock; |
| 124 | enum qe_clock tx_clock; |
| 125 | u32 regs; |
| 126 | int irq; |
| 127 | u32 uccm_mask; |
| 128 | int bd_mem_part; |
| 129 | int brkpt_support; |
| 130 | int grant_support; |
| 131 | int tsa; |
| 132 | int cdp; |
| 133 | int cds; |
| 134 | int ctsp; |
| 135 | int ctss; |
| 136 | int tci; |
| 137 | int txsy; |
| 138 | int rtsm; |
| 139 | int revd; |
| 140 | int rsyn; |
| 141 | u16 max_rx_buf_length; |
| 142 | u16 urfs; |
| 143 | u16 urfet; |
| 144 | u16 urfset; |
| 145 | u16 utfs; |
| 146 | u16 utfet; |
| 147 | u16 utftt; |
| 148 | u16 ufpt; |
| 149 | enum ucc_fast_channel_protocol_mode mode; |
| 150 | enum ucc_fast_transparent_txrx ttx_trx; |
| 151 | enum ucc_fast_tx_encoding_method tenc; |
| 152 | enum ucc_fast_rx_decoding_method renc; |
| 153 | enum ucc_fast_transparent_tcrc tcrc; |
| 154 | enum ucc_fast_sync_len synl; |
| 155 | }; |
| 156 | |
| 157 | struct ucc_fast_private { |
| 158 | struct ucc_fast_info *uf_info; |
| 159 | struct ucc_fast *uf_regs; /* a pointer to memory map of UCC regs. */ |
| 160 | u32 *p_ucce; /* a pointer to the event register in memory. */ |
| 161 | u32 *p_uccm; /* a pointer to the mask register in memory. */ |
Michael Reiss | d5b9049 | 2007-04-13 01:26:19 -0500 | [diff] [blame] | 162 | #ifdef CONFIG_UGETH_TX_ON_DEMAND |
| 163 | u16 *p_utodr; /* pointer to the transmit on demand register */ |
| 164 | #endif |
Li Yang | 9865853 | 2006-10-03 23:10:46 -0500 | [diff] [blame] | 165 | int enabled_tx; /* Whether channel is enabled for Tx (ENT) */ |
| 166 | int enabled_rx; /* Whether channel is enabled for Rx (ENR) */ |
| 167 | int stopped_tx; /* Whether channel has been stopped for Tx |
| 168 | (STOP_TX, etc.) */ |
| 169 | int stopped_rx; /* Whether channel has been stopped for Rx */ |
| 170 | u32 ucc_fast_tx_virtual_fifo_base_offset;/* pointer to base of Tx |
| 171 | virtual fifo */ |
| 172 | u32 ucc_fast_rx_virtual_fifo_base_offset;/* pointer to base of Rx |
| 173 | virtual fifo */ |
| 174 | #ifdef STATISTICS |
| 175 | u32 tx_frames; /* Transmitted frames counter. */ |
| 176 | u32 rx_frames; /* Received frames counter (only frames |
| 177 | passed to application). */ |
| 178 | u32 tx_discarded; /* Discarded tx frames counter (frames that |
| 179 | were discarded by the driver due to errors). |
| 180 | */ |
| 181 | u32 rx_discarded; /* Discarded rx frames counter (frames that |
| 182 | were discarded by the driver due to errors). |
| 183 | */ |
| 184 | #endif /* STATISTICS */ |
| 185 | u16 mrblr; /* maximum receive buffer length */ |
| 186 | }; |
| 187 | |
| 188 | /* ucc_fast_init |
| 189 | * Initializes Fast UCC according to user provided parameters. |
| 190 | * |
| 191 | * uf_info - (In) pointer to the fast UCC info structure. |
| 192 | * uccf_ret - (Out) pointer to the fast UCC structure. |
| 193 | */ |
| 194 | int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret); |
| 195 | |
| 196 | /* ucc_fast_free |
| 197 | * Frees all resources for fast UCC. |
| 198 | * |
| 199 | * uccf - (In) pointer to the fast UCC structure. |
| 200 | */ |
| 201 | void ucc_fast_free(struct ucc_fast_private * uccf); |
| 202 | |
| 203 | /* ucc_fast_enable |
| 204 | * Enables a fast UCC port. |
| 205 | * This routine enables Tx and/or Rx through the General UCC Mode Register. |
| 206 | * |
| 207 | * uccf - (In) pointer to the fast UCC structure. |
| 208 | * mode - (In) TX, RX, or both. |
| 209 | */ |
| 210 | void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode); |
| 211 | |
| 212 | /* ucc_fast_disable |
| 213 | * Disables a fast UCC port. |
| 214 | * This routine disables Tx and/or Rx through the General UCC Mode Register. |
| 215 | * |
| 216 | * uccf - (In) pointer to the fast UCC structure. |
| 217 | * mode - (In) TX, RX, or both. |
| 218 | */ |
| 219 | void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode); |
| 220 | |
| 221 | /* ucc_fast_irq |
| 222 | * Handles interrupts on fast UCC. |
| 223 | * Called from the general interrupt routine to handle interrupts on fast UCC. |
| 224 | * |
| 225 | * uccf - (In) pointer to the fast UCC structure. |
| 226 | */ |
| 227 | void ucc_fast_irq(struct ucc_fast_private * uccf); |
| 228 | |
| 229 | /* ucc_fast_transmit_on_demand |
| 230 | * Immediately forces a poll of the transmitter for data to be sent. |
| 231 | * Typically, the hardware performs a periodic poll for data that the |
| 232 | * transmit routine has set up to be transmitted. In cases where |
| 233 | * this polling cycle is not soon enough, this optional routine can |
| 234 | * be invoked to force a poll right away, instead. Proper use for |
| 235 | * each transmission for which this functionality is desired is to |
| 236 | * call the transmit routine and then this routine right after. |
| 237 | * |
| 238 | * uccf - (In) pointer to the fast UCC structure. |
| 239 | */ |
| 240 | void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf); |
| 241 | |
| 242 | u32 ucc_fast_get_qe_cr_subblock(int uccf_num); |
| 243 | |
| 244 | void ucc_fast_dump_regs(struct ucc_fast_private * uccf); |
| 245 | |
| 246 | #endif /* __UCC_FAST_H__ */ |