| Suneel Garapati | 12ece40 | 2015-08-19 15:23:21 +0530 | [diff] [blame] | 1 | * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock |
| 2 | |
| 3 | RTC controller for the Xilinx Zynq MPSoC Real Time Clock |
| 4 | Separate IRQ lines for seconds and alarm |
| 5 | |
| 6 | Required properties: |
| 7 | - compatible: Should be "xlnx,zynqmp-rtc" |
| 8 | - reg: Physical base address of the controller and length |
| 9 | of memory mapped region. |
| 10 | - interrupts: IRQ lines for the RTC. |
| 11 | - interrupt-names: interrupt line names eg. "sec" "alarm" |
| 12 | |
| 13 | Optional: |
| 14 | - calibration: calibration value for 1 sec period which will |
| 15 | be programmed directly to calibration register |
| 16 | |
| 17 | Example: |
| 18 | rtc: rtc@ffa60000 { |
| 19 | compatible = "xlnx,zynqmp-rtc"; |
| 20 | reg = <0x0 0xffa60000 0x100>; |
| 21 | interrupt-parent = <&gic>; |
| 22 | interrupts = <0 26 4>, <0 27 4>; |
| 23 | interrupt-names = "alarm", "sec"; |
| 24 | calibration = <0x198233>; |
| 25 | }; |