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Ben Skeggsebb945a2012-07-20 08:17:34 +10001/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <core/object.h>
26#include <core/client.h>
27#include <core/device.h>
28#include <core/class.h>
29
30#include <subdev/fb.h>
31#include <subdev/vm.h>
32#include <subdev/instmem.h>
33
34#include <engine/software.h>
35
36#include "nouveau_drm.h"
37#include "nouveau_dma.h"
38#include "nouveau_bo.h"
39#include "nouveau_chan.h"
40#include "nouveau_fence.h"
41#include "nouveau_abi16.h"
42
43MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
44static int nouveau_vram_pushbuf;
45module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
46
47int
48nouveau_channel_idle(struct nouveau_channel *chan)
49{
50 struct nouveau_drm *drm = chan->drm;
51 struct nouveau_fence *fence = NULL;
52 int ret;
53
54 ret = nouveau_fence_new(chan, &fence);
55 if (!ret) {
56 ret = nouveau_fence_wait(fence, false, false);
57 nouveau_fence_unref(&fence);
58 }
59
60 if (ret)
61 NV_ERROR(drm, "failed to idle channel 0x%08x\n", chan->handle);
62 return ret;
63}
64
65void
66nouveau_channel_del(struct nouveau_channel **pchan)
67{
68 struct nouveau_channel *chan = *pchan;
69 if (chan) {
70 struct nouveau_object *client = nv_object(chan->cli);
71 if (chan->fence) {
72 nouveau_channel_idle(chan);
73 nouveau_fence(chan->drm)->context_del(chan);
74 }
75 nouveau_object_del(client, NVDRM_DEVICE, chan->handle);
76 nouveau_object_del(client, NVDRM_DEVICE, chan->push.handle);
77 nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
78 nouveau_bo_unmap(chan->push.buffer);
79 nouveau_bo_ref(NULL, &chan->push.buffer);
80 kfree(chan);
81 }
82 *pchan = NULL;
83}
84
85static int
86nouveau_channel_prep(struct nouveau_drm *drm, struct nouveau_cli *cli,
87 u32 parent, u32 handle, u32 size,
88 struct nouveau_channel **pchan)
89{
90 struct nouveau_device *device = nv_device(drm->device);
91 struct nouveau_instmem *imem = nouveau_instmem(device);
92 struct nouveau_vmmgr *vmm = nouveau_vmmgr(device);
93 struct nouveau_fb *pfb = nouveau_fb(device);
94 struct nouveau_client *client = &cli->base;
95 struct nv_dma_class args = {};
96 struct nouveau_channel *chan;
97 struct nouveau_object *push;
98 u32 target;
99 int ret;
100
101 chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
102 if (!chan)
103 return -ENOMEM;
104
105 chan->cli = cli;
106 chan->drm = drm;
107 chan->handle = handle;
108
109 /* allocate memory for dma push buffer */
110 target = TTM_PL_FLAG_TT;
111 if (nouveau_vram_pushbuf)
112 target = TTM_PL_FLAG_VRAM;
113
114 ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL,
115 &chan->push.buffer);
116 if (ret == 0) {
117 ret = nouveau_bo_pin(chan->push.buffer, target);
118 if (ret == 0)
119 ret = nouveau_bo_map(chan->push.buffer);
120 }
121
122 if (ret) {
123 nouveau_channel_del(pchan);
124 return ret;
125 }
126
127 /* create dma object covering the *entire* memory space that the
128 * pushbuf lives in, this is because the GEM code requires that
129 * we be able to call out to other (indirect) push buffers
130 */
131 chan->push.vma.offset = chan->push.buffer->bo.offset;
132 chan->push.handle = NVDRM_PUSH | (handle & 0xffff);
133
134 if (device->card_type >= NV_50) {
135 ret = nouveau_bo_vma_add(chan->push.buffer, client->vm,
136 &chan->push.vma);
137 if (ret) {
138 nouveau_channel_del(pchan);
139 return ret;
140 }
141
142 args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM;
143 args.start = 0;
144 args.limit = client->vm->vmm->limit - 1;
145 } else
146 if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
147 u64 limit = pfb->ram.size - imem->reserved - 1;
148 if (device->card_type == NV_04) {
149 /* nv04 vram pushbuf hack, retarget to its location in
150 * the framebuffer bar rather than direct vram access..
151 * nfi why this exists, it came from the -nv ddx.
152 */
153 args.flags = NV_DMA_TARGET_PCI | NV_DMA_ACCESS_RDWR;
154 args.start = pci_resource_start(device->pdev, 1);
155 args.limit = args.start + limit;
156 } else {
157 args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR;
158 args.start = 0;
159 args.limit = limit;
160 }
161 } else {
162 if (chan->drm->agp.stat == ENABLED) {
163 args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR;
164 args.start = chan->drm->agp.base;
165 args.limit = chan->drm->agp.base +
166 chan->drm->agp.size - 1;
167 } else {
168 args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR;
169 args.start = 0;
170 args.limit = vmm->limit - 1;
171 }
172 }
173
174 ret = nouveau_object_new(nv_object(chan->cli), parent,
175 chan->push.handle, 0x0002,
176 &args, sizeof(args), &push);
177 if (ret) {
178 nouveau_channel_del(pchan);
179 return ret;
180 }
181
182 return 0;
183}
184
Marcin Slusarz5b8a43a2012-08-19 23:00:00 +0200185static int
Ben Skeggsebb945a2012-07-20 08:17:34 +1000186nouveau_channel_ind(struct nouveau_drm *drm, struct nouveau_cli *cli,
Ben Skeggs49981042012-08-06 19:38:25 +1000187 u32 parent, u32 handle, u32 engine,
188 struct nouveau_channel **pchan)
Ben Skeggsebb945a2012-07-20 08:17:34 +1000189{
Ben Skeggsc97f8c92012-08-19 16:03:00 +1000190 static const u16 oclasses[] = { NVE0_CHANNEL_IND_CLASS,
191 NVC0_CHANNEL_IND_CLASS,
192 NV84_CHANNEL_IND_CLASS,
193 NV50_CHANNEL_IND_CLASS,
194 0 };
Ben Skeggsebb945a2012-07-20 08:17:34 +1000195 const u16 *oclass = oclasses;
Ben Skeggsdbff2de2012-08-06 18:16:37 +1000196 struct nve0_channel_ind_class args;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000197 struct nouveau_channel *chan;
198 int ret;
199
200 /* allocate dma push buffer */
201 ret = nouveau_channel_prep(drm, cli, parent, handle, 0x12000, &chan);
202 *pchan = chan;
203 if (ret)
204 return ret;
205
206 /* create channel object */
207 args.pushbuf = chan->push.handle;
208 args.ioffset = 0x10000 + chan->push.vma.offset;
209 args.ilength = 0x02000;
Ben Skeggs49981042012-08-06 19:38:25 +1000210 args.engine = engine;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000211
212 do {
213 ret = nouveau_object_new(nv_object(cli), parent, handle,
214 *oclass++, &args, sizeof(args),
215 &chan->object);
216 if (ret == 0)
217 return ret;
218 } while (*oclass);
219
220 nouveau_channel_del(pchan);
221 return ret;
222}
223
224static int
225nouveau_channel_dma(struct nouveau_drm *drm, struct nouveau_cli *cli,
226 u32 parent, u32 handle, struct nouveau_channel **pchan)
227{
Ben Skeggsc97f8c92012-08-19 16:03:00 +1000228 static const u16 oclasses[] = { NV40_CHANNEL_DMA_CLASS,
229 NV17_CHANNEL_DMA_CLASS,
230 NV10_CHANNEL_DMA_CLASS,
231 NV03_CHANNEL_DMA_CLASS,
232 0 };
Ben Skeggsebb945a2012-07-20 08:17:34 +1000233 const u16 *oclass = oclasses;
Ben Skeggsa7c6e752012-08-14 15:02:29 +1000234 struct nv03_channel_dma_class args;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000235 struct nouveau_channel *chan;
236 int ret;
237
238 /* allocate dma push buffer */
239 ret = nouveau_channel_prep(drm, cli, parent, handle, 0x10000, &chan);
240 *pchan = chan;
241 if (ret)
242 return ret;
243
244 /* create channel object */
245 args.pushbuf = chan->push.handle;
246 args.offset = chan->push.vma.offset;
247
248 do {
249 ret = nouveau_object_new(nv_object(cli), parent, handle,
250 *oclass++, &args, sizeof(args),
251 &chan->object);
252 if (ret == 0)
253 return ret;
254 } while (ret && *oclass);
255
256 nouveau_channel_del(pchan);
257 return ret;
258}
259
260static int
261nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
262{
263 struct nouveau_client *client = nv_client(chan->cli);
264 struct nouveau_device *device = nv_device(chan->drm->device);
265 struct nouveau_instmem *imem = nouveau_instmem(device);
266 struct nouveau_vmmgr *vmm = nouveau_vmmgr(device);
267 struct nouveau_fb *pfb = nouveau_fb(device);
268 struct nouveau_software_chan *swch;
269 struct nouveau_object *object;
270 struct nv_dma_class args;
271 int ret, i;
272
Ben Skeggsebb945a2012-07-20 08:17:34 +1000273 /* allocate dma objects to cover all allowed vram, and gart */
274 if (device->card_type < NV_C0) {
275 if (device->card_type >= NV_50) {
276 args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM;
277 args.start = 0;
278 args.limit = client->vm->vmm->limit - 1;
279 } else {
280 args.flags = NV_DMA_TARGET_VRAM | NV_DMA_ACCESS_RDWR;
281 args.start = 0;
282 args.limit = pfb->ram.size - imem->reserved - 1;
283 }
284
285 ret = nouveau_object_new(nv_object(client), chan->handle, vram,
286 0x003d, &args, sizeof(args), &object);
287 if (ret)
288 return ret;
289
290 if (device->card_type >= NV_50) {
291 args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_VM;
292 args.start = 0;
293 args.limit = client->vm->vmm->limit - 1;
294 } else
295 if (chan->drm->agp.stat == ENABLED) {
296 args.flags = NV_DMA_TARGET_AGP | NV_DMA_ACCESS_RDWR;
297 args.start = chan->drm->agp.base;
298 args.limit = chan->drm->agp.base +
299 chan->drm->agp.size - 1;
300 } else {
301 args.flags = NV_DMA_TARGET_VM | NV_DMA_ACCESS_RDWR;
302 args.start = 0;
303 args.limit = vmm->limit - 1;
304 }
305
306 ret = nouveau_object_new(nv_object(client), chan->handle, gart,
307 0x003d, &args, sizeof(args), &object);
308 if (ret)
309 return ret;
Ben Skeggs49981042012-08-06 19:38:25 +1000310
311 chan->vram = vram;
312 chan->gart = gart;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000313 }
314
315 /* initialise dma tracking parameters */
Ben Skeggs503b0f12012-08-14 14:53:51 +1000316 switch (nv_hclass(chan->object) & 0x00ff) {
317 case 0x006b:
Ben Skeggsebb945a2012-07-20 08:17:34 +1000318 case 0x006e:
319 chan->user_put = 0x40;
320 chan->user_get = 0x44;
321 chan->dma.max = (0x10000 / 4) - 2;
322 break;
323 default:
324 chan->user_put = 0x40;
325 chan->user_get = 0x44;
326 chan->user_get_hi = 0x60;
327 chan->dma.ib_base = 0x10000 / 4;
328 chan->dma.ib_max = (0x02000 / 8) - 1;
329 chan->dma.ib_put = 0;
330 chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
331 chan->dma.max = chan->dma.ib_base;
332 break;
333 }
334
335 chan->dma.put = 0;
336 chan->dma.cur = chan->dma.put;
337 chan->dma.free = chan->dma.max - chan->dma.cur;
338
339 ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
340 if (ret)
341 return ret;
342
343 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
344 OUT_RING(chan, 0x00000000);
345
346 /* allocate software object class (used for fences on <= nv05, and
347 * to signal flip completion), bind it to a subchannel.
348 */
Ben Skeggs49981042012-08-06 19:38:25 +1000349 if (chan != chan->drm->cechan) {
350 ret = nouveau_object_new(nv_object(client), chan->handle,
351 NvSw, nouveau_abi16_swclass(chan->drm),
352 NULL, 0, &object);
353 if (ret)
354 return ret;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000355
Ben Skeggs49981042012-08-06 19:38:25 +1000356 swch = (void *)object->parent;
357 swch->flip = nouveau_flip_complete;
358 swch->flip_data = chan;
359 }
Ben Skeggsebb945a2012-07-20 08:17:34 +1000360
361 if (device->card_type < NV_C0) {
362 ret = RING_SPACE(chan, 2);
363 if (ret)
364 return ret;
365
366 BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
367 OUT_RING (chan, NvSw);
368 FIRE_RING (chan);
369 }
370
371 /* initialise synchronisation */
372 return nouveau_fence(chan->drm)->context_new(chan);
373}
374
375int
376nouveau_channel_new(struct nouveau_drm *drm, struct nouveau_cli *cli,
Ben Skeggs49981042012-08-06 19:38:25 +1000377 u32 parent, u32 handle, u32 arg0, u32 arg1,
Ben Skeggsebb945a2012-07-20 08:17:34 +1000378 struct nouveau_channel **pchan)
379{
380 int ret;
381
Ben Skeggs49981042012-08-06 19:38:25 +1000382 ret = nouveau_channel_ind(drm, cli, parent, handle, arg0, pchan);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000383 if (ret) {
384 NV_DEBUG(drm, "ib channel create, %d\n", ret);
385 ret = nouveau_channel_dma(drm, cli, parent, handle, pchan);
386 if (ret) {
387 NV_DEBUG(drm, "dma channel create, %d\n", ret);
388 return ret;
389 }
390 }
391
Ben Skeggs49981042012-08-06 19:38:25 +1000392 ret = nouveau_channel_init(*pchan, arg0, arg1);
Ben Skeggsebb945a2012-07-20 08:17:34 +1000393 if (ret) {
394 NV_ERROR(drm, "channel failed to initialise, %d\n", ret);
395 nouveau_channel_del(pchan);
396 return ret;
397 }
398
399 return 0;
400}