blob: 85e874a973370facfa5a2e84cd10894279833be2 [file] [log] [blame]
Rob Herring21278ae2014-06-10 09:06:10 -05001menuconfig ARCH_SIRF
Masahiro Yamadae3246542015-11-16 12:06:10 +09002 bool "CSR SiRF"
3 depends on ARCH_MULTI_V7
Barry Songe7eda912014-01-10 03:15:42 +00004 select ARCH_HAS_RESET_CONTROLLER
Arnd Bergmannef2b1d72015-11-28 23:56:47 +01005 select RESET_CONTROLLER
Arnd Bergmanncf82e0e2013-03-19 17:45:37 +01006 select GENERIC_IRQ_CHIP
Linus Walleij5c34a4e2016-06-02 14:10:16 +02007 select GPIOLIB
Uwe Kleine-Königce816fa2014-04-07 15:39:19 -07008 select NO_IOPORT_MAP
Guo Zengb1999472015-04-14 11:55:55 +00009 select REGMAP
Arnd Bergmanncf82e0e2013-03-19 17:45:37 +010010 select PINCTRL
11 select PINCTRL_SIRF
12 help
13 Support for CSR SiRFprimaII/Marco/Polo platforms
14
Barry Song156a0992012-08-23 13:41:58 +080015if ARCH_SIRF
16
Zhiwu Song4cba0582015-01-04 17:53:37 +080017comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
Barry Songd4fe49e2013-03-18 15:04:38 +080018
19config ARCH_ATLAS6
20 bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
21 default y
Barry Songd4fe49e2013-03-18 15:04:38 +080022 select SIRF_IRQ
23 help
24 Support for CSR SiRFSoC ARM Cortex A9 Platform
Barry Song156a0992012-08-23 13:41:58 +080025
Zhiwu Song4cba0582015-01-04 17:53:37 +080026config ARCH_ATLAS7
27 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
28 default y
29 select ARM_GIC
30 select CPU_V7
Daniel Lezcanob56d5d22016-06-03 13:11:39 +020031 select ATLAS7_TIMER
Zhiwu Song4cba0582015-01-04 17:53:37 +080032 select HAVE_ARM_SCU if SMP
33 select HAVE_SMP
Zhiwu Song4cba0582015-01-04 17:53:37 +080034 help
35 Support for CSR SiRFSoC ARM Cortex A7 Platform
36
Barry Song156a0992012-08-23 13:41:58 +080037config ARCH_PRIMA2
38 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
39 default y
Barry Songc1e3c112012-08-23 13:41:59 +080040 select SIRF_IRQ
Russell Kingb1b3f492012-10-06 17:12:25 +010041 select ZONE_DMA
Daniel Lezcanof3550d42016-06-03 14:28:38 +020042 select PRIMA2_TIMER
Barry Song156a0992012-08-23 13:41:58 +080043 help
44 Support for CSR SiRFSoC ARM Cortex A9 Platform
45
Barry Songc1e3c112012-08-23 13:41:59 +080046config SIRF_IRQ
47 bool
48
Barry Song156a0992012-08-23 13:41:58 +080049endif