blob: 80445ed33d9529d81d0f908d2b359192988c4986 [file] [log] [blame]
Joseph Lo0b25e252012-10-31 17:41:15 +08001/*
2 * CPU idle driver for Tegra CPUs
3 *
4 * Copyright (c) 2010-2012, NVIDIA Corporation.
5 * Copyright (c) 2011 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 * Gary King <gking@nvidia.com>
8 *
9 * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/cpuidle.h>
Joseph Lod457ef352012-10-31 17:41:17 +080025#include <linux/cpu_pm.h>
26#include <linux/clockchips.h>
Prashant Gaikwad89572c72013-01-11 13:16:21 +053027#include <linux/clk/tegra.h>
Joseph Lo0b25e252012-10-31 17:41:15 +080028
29#include <asm/cpuidle.h>
Joseph Lod457ef352012-10-31 17:41:17 +080030#include <asm/proc-fns.h>
31#include <asm/suspend.h>
32#include <asm/smp_plat.h>
33
34#include "pm.h"
35#include "sleep.h"
36
37#ifdef CONFIG_PM_SLEEP
38static int tegra30_idle_lp2(struct cpuidle_device *dev,
39 struct cpuidle_driver *drv,
40 int index);
41#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080042
43static struct cpuidle_driver tegra_idle_driver = {
44 .name = "tegra_idle",
45 .owner = THIS_MODULE,
46 .en_core_tk_irqen = 1,
Joseph Lod457ef352012-10-31 17:41:17 +080047#ifdef CONFIG_PM_SLEEP
48 .state_count = 2,
49#else
Joseph Lo0b25e252012-10-31 17:41:15 +080050 .state_count = 1,
Joseph Lod457ef352012-10-31 17:41:17 +080051#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080052 .states = {
53 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
Joseph Lod457ef352012-10-31 17:41:17 +080054#ifdef CONFIG_PM_SLEEP
55 [1] = {
56 .enter = tegra30_idle_lp2,
57 .exit_latency = 2000,
58 .target_residency = 2200,
59 .power_usage = 0,
60 .flags = CPUIDLE_FLAG_TIME_VALID,
61 .name = "powered-down",
62 .desc = "CPU power gated",
63 },
64#endif
Joseph Lo0b25e252012-10-31 17:41:15 +080065 },
66};
67
68static DEFINE_PER_CPU(struct cpuidle_device, tegra_idle_device);
69
Joseph Lod457ef352012-10-31 17:41:17 +080070#ifdef CONFIG_PM_SLEEP
Joseph Lod5529202012-10-31 17:41:21 +080071static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
72 struct cpuidle_driver *drv,
73 int index)
74{
75 struct cpuidle_state *state = &drv->states[index];
76 u32 cpu_on_time = state->exit_latency;
77 u32 cpu_off_time = state->target_residency - state->exit_latency;
78
79 /* All CPUs entering LP2 is not working.
80 * Don't let CPU0 enter LP2 when any secondary CPU is online.
81 */
82 if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
83 cpu_do_idle();
84 return false;
85 }
86
87 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
88
89 tegra_idle_lp2_last(cpu_on_time, cpu_off_time);
90
91 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
92
93 return true;
94}
95
Joseph Lod457ef352012-10-31 17:41:17 +080096#ifdef CONFIG_SMP
97static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
98 struct cpuidle_driver *drv,
99 int index)
100{
101 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
102
103 smp_wmb();
104
Joseph Lod457ef352012-10-31 17:41:17 +0800105 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
106
Joseph Lod457ef352012-10-31 17:41:17 +0800107 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
108
109 return true;
110}
111#else
112static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
113 struct cpuidle_driver *drv,
114 int index)
115{
116 return true;
117}
118#endif
119
Joseph Lo8c627fa2013-01-04 17:32:21 +0800120static int tegra30_idle_lp2(struct cpuidle_device *dev,
121 struct cpuidle_driver *drv,
122 int index)
Joseph Lod457ef352012-10-31 17:41:17 +0800123{
124 u32 cpu = is_smp() ? cpu_logical_map(dev->cpu) : dev->cpu;
125 bool entered_lp2 = false;
Joseph Lod5529202012-10-31 17:41:21 +0800126 bool last_cpu;
Joseph Lod457ef352012-10-31 17:41:17 +0800127
128 local_fiq_disable();
129
Joseph Lod5529202012-10-31 17:41:21 +0800130 last_cpu = tegra_set_cpu_in_lp2(cpu);
Joseph Lod457ef352012-10-31 17:41:17 +0800131 cpu_pm_enter();
132
Joseph Lod5529202012-10-31 17:41:21 +0800133 if (cpu == 0) {
134 if (last_cpu)
135 entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
136 index);
137 else
138 cpu_do_idle();
139 } else {
Joseph Lod457ef352012-10-31 17:41:17 +0800140 entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
Joseph Lod5529202012-10-31 17:41:21 +0800141 }
Joseph Lod457ef352012-10-31 17:41:17 +0800142
143 cpu_pm_exit();
144 tegra_clear_cpu_in_lp2(cpu);
145
146 local_fiq_enable();
147
148 smp_rmb();
149
150 return (entered_lp2) ? index : 0;
151}
152#endif
153
Joseph Lo0b25e252012-10-31 17:41:15 +0800154int __init tegra30_cpuidle_init(void)
155{
156 int ret;
157 unsigned int cpu;
158 struct cpuidle_device *dev;
159 struct cpuidle_driver *drv = &tegra_idle_driver;
160
Joseph Lod5529202012-10-31 17:41:21 +0800161#ifdef CONFIG_PM_SLEEP
162 tegra_tear_down_cpu = tegra30_tear_down_cpu;
163#endif
164
Joseph Lo0b25e252012-10-31 17:41:15 +0800165 ret = cpuidle_register_driver(&tegra_idle_driver);
166 if (ret) {
167 pr_err("CPUidle driver registration failed\n");
168 return ret;
169 }
170
171 for_each_possible_cpu(cpu) {
172 dev = &per_cpu(tegra_idle_device, cpu);
173 dev->cpu = cpu;
174
175 dev->state_count = drv->state_count;
176 ret = cpuidle_register_device(dev);
177 if (ret) {
178 pr_err("CPU%u: CPUidle device registration failed\n",
179 cpu);
180 return ret;
181 }
182 }
183 return 0;
184}