Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 1 | #include <linux/sizes.h> |
| 2 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 3 | #include "ddk750_help.h" |
| 4 | #include "ddk750_reg.h" |
| 5 | #include "ddk750_chip.h" |
| 6 | #include "ddk750_power.h" |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 7 | |
Supriya Karanth | 6fa7db8 | 2015-03-12 01:11:00 +0900 | [diff] [blame] | 8 | logical_chip_type_t getChipType(void) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 9 | { |
| 10 | unsigned short physicalID; |
| 11 | char physicalRev; |
| 12 | logical_chip_type_t chip; |
| 13 | |
Juston Li | 5ee35ea | 2015-06-12 03:17:22 -0700 | [diff] [blame] | 14 | physicalID = devId750; /* either 0x718 or 0x750 */ |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 15 | physicalRev = revId750; |
| 16 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 17 | if (physicalID == 0x718) |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 18 | chip = SM718; |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 19 | else if (physicalID == 0x750) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 20 | chip = SM750; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 21 | /* SM750 and SM750LE are different in their revision ID only. */ |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 22 | if (physicalRev == SM750LE_REVISION_ID) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 23 | chip = SM750LE; |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 24 | } else |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 25 | chip = SM_UNKNOWN; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 26 | |
| 27 | return chip; |
| 28 | } |
| 29 | |
Mike Rapoport | 7092d76 | 2015-10-13 09:26:45 +0300 | [diff] [blame] | 30 | static unsigned int get_mxclk_freq(void) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 31 | { |
Mike Rapoport | 7751e0e | 2015-10-13 09:26:44 +0300 | [diff] [blame] | 32 | unsigned int pll_reg; |
| 33 | unsigned int M, N, OD, POD; |
| 34 | |
Helen Fornazier | 82736d2 | 2015-03-26 14:09:16 -0300 | [diff] [blame] | 35 | if (getChipType() == SM750LE) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 36 | return MHz(130); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 37 | |
Mike Rapoport | 7751e0e | 2015-10-13 09:26:44 +0300 | [diff] [blame] | 38 | pll_reg = PEEK32(MXCLK_PLL_CTRL); |
| 39 | M = FIELD_GET(pll_reg, PANEL_PLL_CTRL, M); |
| 40 | N = FIELD_GET(pll_reg, PANEL_PLL_CTRL, N); |
| 41 | OD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, OD); |
| 42 | POD = FIELD_GET(pll_reg, PANEL_PLL_CTRL, POD); |
| 43 | |
| 44 | return DEFAULT_INPUT_CLOCK * M / N / (1 << OD) / (1 << POD); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 45 | } |
| 46 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 47 | /* |
| 48 | * This function set up the main chip clock. |
| 49 | * |
| 50 | * Input: Frequency to be set. |
| 51 | */ |
Mike Rapoport | fb6f37a | 2015-09-30 08:24:54 +0300 | [diff] [blame] | 52 | static void setChipClock(unsigned int frequency) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 53 | { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 54 | pll_value_t pll; |
| 55 | unsigned int ulActualMxClk; |
Mike Rapoport | cfac7d6 | 2015-10-22 09:38:39 +0300 | [diff] [blame] | 56 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 57 | /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ |
| 58 | if (getChipType() == SM750LE) |
| 59 | return; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 60 | |
Amitoj Kaur Chawla | 59f0840 | 2015-04-02 23:01:04 +0530 | [diff] [blame] | 61 | if (frequency) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 62 | /* |
| 63 | * Set up PLL, a structure to hold the value to be set in clocks. |
| 64 | */ |
| 65 | pll.inputFreq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ |
| 66 | pll.clockType = MXCLK_PLL; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 67 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 68 | /* |
| 69 | * Call calcPllValue() to fill up the other fields for PLL structure. |
| 70 | * Sometime, the chip cannot set up the exact clock required by User. |
| 71 | * Return value from calcPllValue() gives the actual possible clock. |
| 72 | */ |
| 73 | ulActualMxClk = calcPllValue(frequency, &pll); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 74 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 75 | /* Master Clock Control: MXCLK_PLL */ |
| 76 | POKE32(MXCLK_PLL_CTRL, formatPllReg(&pll)); |
| 77 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 78 | } |
| 79 | |
Mike Rapoport | fb6f37a | 2015-09-30 08:24:54 +0300 | [diff] [blame] | 80 | static void setMemoryClock(unsigned int frequency) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 81 | { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 82 | unsigned int ulReg, divisor; |
Mike Rapoport | cfac7d6 | 2015-10-22 09:38:39 +0300 | [diff] [blame] | 83 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 84 | /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ |
| 85 | if (getChipType() == SM750LE) |
| 86 | return; |
Mike Rapoport | cfac7d6 | 2015-10-22 09:38:39 +0300 | [diff] [blame] | 87 | |
Amitoj Kaur Chawla | 59f0840 | 2015-04-02 23:01:04 +0530 | [diff] [blame] | 88 | if (frequency) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 89 | /* Set the frequency to the maximum frequency that the DDR Memory can take |
| 90 | which is 336MHz. */ |
| 91 | if (frequency > MHz(336)) |
| 92 | frequency = MHz(336); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 93 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 94 | /* Calculate the divisor */ |
Mike Rapoport | b02f924 | 2015-10-13 09:26:46 +0300 | [diff] [blame] | 95 | divisor = roundedDiv(get_mxclk_freq(), frequency); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 96 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 97 | /* Set the corresponding divisor in the register. */ |
| 98 | ulReg = PEEK32(CURRENT_GATE); |
Helen Fornazier | c107243 | 2015-03-26 14:09:17 -0300 | [diff] [blame] | 99 | switch (divisor) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 100 | default: |
| 101 | case 1: |
| 102 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_1); |
| 103 | break; |
| 104 | case 2: |
| 105 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_2); |
| 106 | break; |
| 107 | case 3: |
| 108 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_3); |
| 109 | break; |
| 110 | case 4: |
| 111 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, M2XCLK, DIV_4); |
| 112 | break; |
| 113 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 114 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 115 | setCurrentGate(ulReg); |
| 116 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 117 | } |
| 118 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 119 | /* |
| 120 | * This function set up the master clock (MCLK). |
| 121 | * |
| 122 | * Input: Frequency to be set. |
| 123 | * |
| 124 | * NOTE: |
| 125 | * The maximum frequency the engine can run is 168MHz. |
| 126 | */ |
Mike Rapoport | fb6f37a | 2015-09-30 08:24:54 +0300 | [diff] [blame] | 127 | static void setMasterClock(unsigned int frequency) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 128 | { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 129 | unsigned int ulReg, divisor; |
Mike Rapoport | cfac7d6 | 2015-10-22 09:38:39 +0300 | [diff] [blame] | 130 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 131 | /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */ |
| 132 | if (getChipType() == SM750LE) |
| 133 | return; |
Mike Rapoport | cfac7d6 | 2015-10-22 09:38:39 +0300 | [diff] [blame] | 134 | |
Amitoj Kaur Chawla | 59f0840 | 2015-04-02 23:01:04 +0530 | [diff] [blame] | 135 | if (frequency) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 136 | /* Set the frequency to the maximum frequency that the SM750 engine can |
| 137 | run, which is about 190 MHz. */ |
| 138 | if (frequency > MHz(190)) |
| 139 | frequency = MHz(190); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 140 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 141 | /* Calculate the divisor */ |
Mike Rapoport | b02f924 | 2015-10-13 09:26:46 +0300 | [diff] [blame] | 142 | divisor = roundedDiv(get_mxclk_freq(), frequency); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 143 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 144 | /* Set the corresponding divisor in the register. */ |
| 145 | ulReg = PEEK32(CURRENT_GATE); |
Helen Fornazier | c107243 | 2015-03-26 14:09:17 -0300 | [diff] [blame] | 146 | switch (divisor) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 147 | default: |
| 148 | case 3: |
| 149 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_3); |
| 150 | break; |
| 151 | case 4: |
| 152 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_4); |
| 153 | break; |
| 154 | case 6: |
| 155 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_6); |
| 156 | break; |
| 157 | case 8: |
| 158 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, MCLK, DIV_8); |
| 159 | break; |
| 160 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 161 | |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 162 | setCurrentGate(ulReg); |
| 163 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 164 | } |
| 165 | |
Supriya Karanth | 6fa7db8 | 2015-03-12 01:11:00 +0900 | [diff] [blame] | 166 | unsigned int ddk750_getVMSize(void) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 167 | { |
| 168 | unsigned int reg; |
| 169 | unsigned int data; |
| 170 | |
| 171 | /* sm750le only use 64 mb memory*/ |
Helen Fornazier | 82736d2 | 2015-03-26 14:09:16 -0300 | [diff] [blame] | 172 | if (getChipType() == SM750LE) |
Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 173 | return SZ_64M; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 174 | |
| 175 | /* for 750,always use power mode0*/ |
| 176 | reg = PEEK32(MODE0_GATE); |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 177 | reg = FIELD_SET(reg, MODE0_GATE, GPIO, ON); |
| 178 | POKE32(MODE0_GATE, reg); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 179 | |
| 180 | /* get frame buffer size from GPIO */ |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 181 | reg = FIELD_GET(PEEK32(MISC_CTRL), MISC_CTRL, LOCALMEM_SIZE); |
Helen Fornazier | c107243 | 2015-03-26 14:09:17 -0300 | [diff] [blame] | 182 | switch (reg) { |
Helen Fornazier | ae59c46 | 2015-03-26 14:09:19 -0300 | [diff] [blame] | 183 | case MISC_CTRL_LOCALMEM_SIZE_8M: |
Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 184 | data = SZ_8M; break; /* 8 Mega byte */ |
Helen Fornazier | ae59c46 | 2015-03-26 14:09:19 -0300 | [diff] [blame] | 185 | case MISC_CTRL_LOCALMEM_SIZE_16M: |
Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 186 | data = SZ_16M; break; /* 16 Mega byte */ |
Helen Fornazier | ae59c46 | 2015-03-26 14:09:19 -0300 | [diff] [blame] | 187 | case MISC_CTRL_LOCALMEM_SIZE_32M: |
Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 188 | data = SZ_32M; break; /* 32 Mega byte */ |
Helen Fornazier | ae59c46 | 2015-03-26 14:09:19 -0300 | [diff] [blame] | 189 | case MISC_CTRL_LOCALMEM_SIZE_64M: |
Mike Rapoport | 4cf26d8 | 2015-09-22 12:01:17 +0300 | [diff] [blame] | 190 | data = SZ_64M; break; /* 64 Mega byte */ |
Helen Fornazier | ae59c46 | 2015-03-26 14:09:19 -0300 | [diff] [blame] | 191 | default: |
Amitoj Kaur Chawla | e261e69 | 2015-04-02 22:57:55 +0530 | [diff] [blame] | 192 | data = 0; |
| 193 | break; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 194 | } |
| 195 | return data; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 196 | } |
| 197 | |
Helen Fornazier | f8da055 | 2015-03-26 14:09:20 -0300 | [diff] [blame] | 198 | int ddk750_initHw(initchip_param_t *pInitParam) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 199 | { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 200 | unsigned int ulReg; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 201 | |
Juston Li | 8332d94 | 2015-07-14 21:14:32 -0700 | [diff] [blame] | 202 | if (pInitParam->powerMode != 0) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 203 | pInitParam->powerMode = 0; |
| 204 | setPowerMode(pInitParam->powerMode); |
| 205 | |
| 206 | /* Enable display power gate & LOCALMEM power gate*/ |
| 207 | ulReg = PEEK32(CURRENT_GATE); |
| 208 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, DISPLAY, ON); |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 209 | ulReg = FIELD_SET(ulReg, CURRENT_GATE, LOCALMEM, ON); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 210 | setCurrentGate(ulReg); |
| 211 | |
Helen Fornazier | 82736d2 | 2015-03-26 14:09:16 -0300 | [diff] [blame] | 212 | if (getChipType() != SM750LE) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 213 | /* set panel pll and graphic mode via mmio_88 */ |
| 214 | ulReg = PEEK32(VGA_CONFIGURATION); |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 215 | ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, PLL, PANEL); |
| 216 | ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, MODE, GRAPHIC); |
| 217 | POKE32(VGA_CONFIGURATION, ulReg); |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 218 | } else { |
Amitoj Kaur Chawla | 31296ba | 2015-04-08 22:25:06 +0530 | [diff] [blame] | 219 | #if defined(__i386__) || defined(__x86_64__) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 220 | /* set graphic mode via IO method */ |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 221 | outb_p(0x88, 0x3d4); |
| 222 | outb_p(0x06, 0x3d5); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 223 | #endif |
| 224 | } |
| 225 | |
| 226 | /* Set the Main Chip Clock */ |
| 227 | setChipClock(MHz((unsigned int)pInitParam->chipClock)); |
| 228 | |
| 229 | /* Set up memory clock. */ |
| 230 | setMemoryClock(MHz(pInitParam->memClock)); |
| 231 | |
| 232 | /* Set up master clock */ |
| 233 | setMasterClock(MHz(pInitParam->masterClock)); |
| 234 | |
| 235 | |
| 236 | /* Reset the memory controller. If the memory controller is not reset in SM750, |
| 237 | the system might hang when sw accesses the memory. |
| 238 | The memory should be resetted after changing the MXCLK. |
| 239 | */ |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 240 | if (pInitParam->resetMemory == 1) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 241 | ulReg = PEEK32(MISC_CTRL); |
| 242 | ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, RESET); |
| 243 | POKE32(MISC_CTRL, ulReg); |
| 244 | |
| 245 | ulReg = FIELD_SET(ulReg, MISC_CTRL, LOCALMEM_RESET, NORMAL); |
| 246 | POKE32(MISC_CTRL, ulReg); |
| 247 | } |
| 248 | |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 249 | if (pInitParam->setAllEngOff == 1) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 250 | enable2DEngine(0); |
| 251 | |
| 252 | /* Disable Overlay, if a former application left it on */ |
| 253 | ulReg = PEEK32(VIDEO_DISPLAY_CTRL); |
| 254 | ulReg = FIELD_SET(ulReg, VIDEO_DISPLAY_CTRL, PLANE, DISABLE); |
| 255 | POKE32(VIDEO_DISPLAY_CTRL, ulReg); |
| 256 | |
| 257 | /* Disable video alpha, if a former application left it on */ |
| 258 | ulReg = PEEK32(VIDEO_ALPHA_DISPLAY_CTRL); |
| 259 | ulReg = FIELD_SET(ulReg, VIDEO_ALPHA_DISPLAY_CTRL, PLANE, DISABLE); |
| 260 | POKE32(VIDEO_ALPHA_DISPLAY_CTRL, ulReg); |
| 261 | |
| 262 | /* Disable alpha plane, if a former application left it on */ |
| 263 | ulReg = PEEK32(ALPHA_DISPLAY_CTRL); |
| 264 | ulReg = FIELD_SET(ulReg, ALPHA_DISPLAY_CTRL, PLANE, DISABLE); |
| 265 | POKE32(ALPHA_DISPLAY_CTRL, ulReg); |
| 266 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 267 | /* Disable DMA Channel, if a former application left it on */ |
| 268 | ulReg = PEEK32(DMA_ABORT_INTERRUPT); |
| 269 | ulReg = FIELD_SET(ulReg, DMA_ABORT_INTERRUPT, ABORT_1, ABORT); |
| 270 | POKE32(DMA_ABORT_INTERRUPT, ulReg); |
| 271 | |
| 272 | /* Disable DMA Power, if a former application left it on */ |
| 273 | enableDMA(0); |
| 274 | } |
| 275 | |
| 276 | /* We can add more initialization as needed. */ |
| 277 | |
| 278 | return 0; |
| 279 | } |
| 280 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 281 | /* |
| 282 | monk liu @ 4/6/2011: |
| 283 | re-write the calculatePLL function of ddk750. |
| 284 | the original version function does not use some mathematics tricks and shortcut |
| 285 | when it doing the calculation of the best N,M,D combination |
| 286 | I think this version gives a little upgrade in speed |
| 287 | |
| 288 | 750 pll clock formular: |
| 289 | Request Clock = (Input Clock * M )/(N * X) |
| 290 | |
| 291 | Input Clock = 14318181 hz |
| 292 | X = 2 power D |
| 293 | D ={0,1,2,3,4,5,6} |
| 294 | M = {1,...,255} |
| 295 | N = {2,...,15} |
| 296 | */ |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 297 | unsigned int calcPllValue(unsigned int request_orig, pll_value_t *pll) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 298 | { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 299 | /* as sm750 register definition, N located in 2,15 and M located in 1,255 */ |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 300 | int N, M, X, d; |
Amitoj Kaur Chawla | 43ce0b5 | 2015-10-10 02:14:27 +0530 | [diff] [blame] | 301 | int mini_diff; |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 302 | unsigned int RN, quo, rem, fl_quo; |
| 303 | unsigned int input, request; |
| 304 | unsigned int tmpClock, ret; |
Mike Rapoport | a61dc13 | 2015-10-22 09:38:40 +0300 | [diff] [blame] | 305 | const int max_OD = 3; |
| 306 | int max_d; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 307 | |
Helen Fornazier | 9767fc5 | 2015-03-26 14:09:14 -0300 | [diff] [blame] | 308 | if (getChipType() == SM750LE) { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 309 | /* SM750LE don't have prgrammable PLL and M/N values to work on. |
| 310 | Just return the requested clock. */ |
| 311 | return request_orig; |
| 312 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 313 | |
| 314 | ret = 0; |
Amitoj Kaur Chawla | 43ce0b5 | 2015-10-10 02:14:27 +0530 | [diff] [blame] | 315 | mini_diff = ~0; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 316 | request = request_orig / 1000; |
| 317 | input = pll->inputFreq / 1000; |
| 318 | |
| 319 | /* for MXCLK register , no POD provided, so need be treated differently */ |
Mike Rapoport | a61dc13 | 2015-10-22 09:38:40 +0300 | [diff] [blame] | 320 | if (pll->clockType == MXCLK_PLL) |
| 321 | max_d = 3; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 322 | |
Helen Fornazier | ce02a16a | 2015-03-26 14:09:15 -0300 | [diff] [blame] | 323 | for (N = 15; N > 1; N--) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 324 | /* RN will not exceed maximum long if @request <= 285 MHZ (for 32bit cpu) */ |
| 325 | RN = N * request; |
| 326 | quo = RN / input; |
| 327 | rem = RN % input;/* rem always small than 14318181 */ |
Juston Li | 6ab5b6d | 2015-07-14 21:14:40 -0700 | [diff] [blame] | 328 | fl_quo = (rem * 10000 / input); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 329 | |
Mike Rapoport | a61dc13 | 2015-10-22 09:38:40 +0300 | [diff] [blame] | 330 | for (d = max_d; d >= 0; d--) { |
| 331 | X = (1 << d); |
Amitoj Kaur Chawla | f40917e | 2015-10-04 20:12:30 +0530 | [diff] [blame] | 332 | M = quo * X; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 333 | M += fl_quo * X / 10000; |
| 334 | /* round step */ |
Amitoj Kaur Chawla | 07387cb | 2015-10-04 20:18:32 +0530 | [diff] [blame] | 335 | M += (fl_quo * X % 10000) > 5000 ? 1 : 0; |
Helen Fornazier | 82736d2 | 2015-03-26 14:09:16 -0300 | [diff] [blame] | 336 | if (M < 256 && M > 0) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 337 | unsigned int diff; |
Juston Li | 40403c1 | 2015-07-14 21:14:48 -0700 | [diff] [blame] | 338 | |
Juston Li | 6ab5b6d | 2015-07-14 21:14:40 -0700 | [diff] [blame] | 339 | tmpClock = pll->inputFreq * M / N / X; |
Helen Fornazier | c04051f | 2015-03-26 14:09:18 -0300 | [diff] [blame] | 340 | diff = absDiff(tmpClock, request_orig); |
Amitoj Kaur Chawla | 43ce0b5 | 2015-10-10 02:14:27 +0530 | [diff] [blame] | 341 | if (diff < mini_diff) { |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 342 | pll->M = M; |
| 343 | pll->N = N; |
Mike Rapoport | a61dc13 | 2015-10-22 09:38:40 +0300 | [diff] [blame] | 344 | pll->POD = 0; |
| 345 | if (d > max_OD) |
| 346 | pll->POD = d - max_OD; |
| 347 | pll->OD = d - pll->POD; |
Amitoj Kaur Chawla | 43ce0b5 | 2015-10-10 02:14:27 +0530 | [diff] [blame] | 348 | mini_diff = diff; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 349 | ret = tmpClock; |
| 350 | } |
| 351 | } |
| 352 | } |
| 353 | } |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 354 | return ret; |
| 355 | } |
| 356 | |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 357 | unsigned int formatPllReg(pll_value_t *pPLL) |
| 358 | { |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 359 | unsigned int ulPllReg = 0; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 360 | |
| 361 | /* Note that all PLL's have the same format. Here, we just use Panel PLL parameter |
| 362 | to work out the bit fields in the register. |
| 363 | On returning a 32 bit number, the value can be applied to any PLL in the calling function. |
| 364 | */ |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 365 | ulPllReg = |
Juston Li | 7f0ebcc | 2015-07-14 21:14:31 -0700 | [diff] [blame] | 366 | FIELD_SET(0, PANEL_PLL_CTRL, BYPASS, OFF) |
| 367 | | FIELD_SET(0, PANEL_PLL_CTRL, POWER, ON) |
| 368 | | FIELD_SET(0, PANEL_PLL_CTRL, INPUT, OSC) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 369 | #ifndef VALIDATION_CHIP |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 370 | | FIELD_VALUE(0, PANEL_PLL_CTRL, POD, pPLL->POD) |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 371 | #endif |
Ragavendra Nagraj | de99bef | 2015-03-18 02:37:42 -0700 | [diff] [blame] | 372 | | FIELD_VALUE(0, PANEL_PLL_CTRL, OD, pPLL->OD) |
| 373 | | FIELD_VALUE(0, PANEL_PLL_CTRL, N, pPLL->N) |
| 374 | | FIELD_VALUE(0, PANEL_PLL_CTRL, M, pPLL->M); |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 375 | |
Isaac Assegai | 63de0eb | 2015-05-24 22:48:42 -0700 | [diff] [blame] | 376 | return ulPllReg; |
Sudip Mukherjee | 81dee67 | 2015-03-03 16:21:06 +0530 | [diff] [blame] | 377 | } |
| 378 | |
| 379 | |