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Oder Chiou1319b2f2014-04-28 19:59:10 +08001/*
2 * rt5645.c -- RT5645 ALSA SoC audio codec driver
3 *
4 * Copyright 2013 Realtek Semiconductor Corp.
5 * Author: Bard Liao <bardliao@realtek.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
Oder Chiouf3fa1bb2014-09-19 19:15:45 +080020#include <linux/gpio.h>
Oder Chiou1319b2f2014-04-28 19:59:10 +080021#include <sound/core.h>
22#include <sound/pcm.h>
23#include <sound/pcm_params.h>
24#include <sound/jack.h>
25#include <sound/soc.h>
26#include <sound/soc-dapm.h>
27#include <sound/initval.h>
28#include <sound/tlv.h>
29
Oder Chiou49ef7922014-05-20 15:01:53 +080030#include "rl6231.h"
Oder Chiou1319b2f2014-04-28 19:59:10 +080031#include "rt5645.h"
32
33#define RT5645_DEVICE_ID 0x6308
Bard Liao5c4ca992015-01-21 20:50:15 +080034#define RT5650_DEVICE_ID 0x6419
Oder Chiou1319b2f2014-04-28 19:59:10 +080035
36#define RT5645_PR_RANGE_BASE (0xff + 1)
37#define RT5645_PR_SPACING 0x100
38
39#define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
40
41static const struct regmap_range_cfg rt5645_ranges[] = {
42 {
43 .name = "PR",
44 .range_min = RT5645_PR_BASE,
45 .range_max = RT5645_PR_BASE + 0xf8,
46 .selector_reg = RT5645_PRIV_INDEX,
47 .selector_mask = 0xff,
48 .selector_shift = 0x0,
49 .window_start = RT5645_PRIV_DATA,
50 .window_len = 0x1,
51 },
52};
53
54static const struct reg_default init_list[] = {
55 {RT5645_PR_BASE + 0x3d, 0x3600},
Oder Chiou4809b962014-05-08 14:47:36 +080056 {RT5645_PR_BASE + 0x1c, 0xfd20},
57 {RT5645_PR_BASE + 0x20, 0x611f},
58 {RT5645_PR_BASE + 0x21, 0x4040},
59 {RT5645_PR_BASE + 0x23, 0x0004},
Oder Chiou1319b2f2014-04-28 19:59:10 +080060};
61#define RT5645_INIT_REG_LEN ARRAY_SIZE(init_list)
62
Bard Liao5c4ca992015-01-21 20:50:15 +080063static const struct reg_default rt5650_init_list[] = {
64 {0xf6, 0x0100},
65};
66
Oder Chiou1319b2f2014-04-28 19:59:10 +080067static const struct reg_default rt5645_reg[] = {
68 { 0x00, 0x0000 },
69 { 0x01, 0xc8c8 },
70 { 0x02, 0xc8c8 },
71 { 0x03, 0xc8c8 },
72 { 0x0a, 0x0002 },
73 { 0x0b, 0x2827 },
74 { 0x0c, 0xe000 },
75 { 0x0d, 0x0000 },
76 { 0x0e, 0x0000 },
77 { 0x0f, 0x0808 },
78 { 0x14, 0x3333 },
79 { 0x16, 0x4b00 },
80 { 0x18, 0x018b },
81 { 0x19, 0xafaf },
82 { 0x1a, 0xafaf },
83 { 0x1b, 0x0001 },
84 { 0x1c, 0x2f2f },
85 { 0x1d, 0x2f2f },
86 { 0x1e, 0x0000 },
87 { 0x20, 0x0000 },
88 { 0x27, 0x7060 },
89 { 0x28, 0x7070 },
90 { 0x29, 0x8080 },
91 { 0x2a, 0x5656 },
92 { 0x2b, 0x5454 },
93 { 0x2c, 0xaaa0 },
Bard Liao5c4ca992015-01-21 20:50:15 +080094 { 0x2d, 0x0000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +080095 { 0x2f, 0x1002 },
96 { 0x31, 0x5000 },
97 { 0x32, 0x0000 },
98 { 0x33, 0x0000 },
99 { 0x34, 0x0000 },
100 { 0x35, 0x0000 },
101 { 0x3b, 0x0000 },
102 { 0x3c, 0x007f },
103 { 0x3d, 0x0000 },
104 { 0x3e, 0x007f },
105 { 0x3f, 0x0000 },
106 { 0x40, 0x001f },
107 { 0x41, 0x0000 },
108 { 0x42, 0x001f },
109 { 0x45, 0x6000 },
110 { 0x46, 0x003e },
111 { 0x47, 0x003e },
112 { 0x48, 0xf807 },
113 { 0x4a, 0x0004 },
114 { 0x4d, 0x0000 },
115 { 0x4e, 0x0000 },
116 { 0x4f, 0x01ff },
117 { 0x50, 0x0000 },
118 { 0x51, 0x0000 },
119 { 0x52, 0x01ff },
120 { 0x53, 0xf000 },
121 { 0x56, 0x0111 },
122 { 0x57, 0x0064 },
123 { 0x58, 0xef0e },
124 { 0x59, 0xf0f0 },
125 { 0x5a, 0xef0e },
126 { 0x5b, 0xf0f0 },
127 { 0x5c, 0xef0e },
128 { 0x5d, 0xf0f0 },
129 { 0x5e, 0xf000 },
130 { 0x5f, 0x0000 },
131 { 0x61, 0x0300 },
132 { 0x62, 0x0000 },
133 { 0x63, 0x00c2 },
134 { 0x64, 0x0000 },
135 { 0x65, 0x0000 },
136 { 0x66, 0x0000 },
137 { 0x6a, 0x0000 },
138 { 0x6c, 0x0aaa },
139 { 0x70, 0x8000 },
140 { 0x71, 0x8000 },
141 { 0x72, 0x8000 },
142 { 0x73, 0x7770 },
143 { 0x74, 0x3e00 },
144 { 0x75, 0x2409 },
145 { 0x76, 0x000a },
146 { 0x77, 0x0c00 },
147 { 0x78, 0x0000 },
Fang, Yang Adf078d22014-10-28 18:36:36 -0300148 { 0x79, 0x0123 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800149 { 0x80, 0x0000 },
150 { 0x81, 0x0000 },
151 { 0x82, 0x0000 },
152 { 0x83, 0x0000 },
153 { 0x84, 0x0000 },
154 { 0x85, 0x0000 },
155 { 0x8a, 0x0000 },
156 { 0x8e, 0x0004 },
157 { 0x8f, 0x1100 },
158 { 0x90, 0x0646 },
159 { 0x91, 0x0c06 },
160 { 0x93, 0x0000 },
161 { 0x94, 0x0200 },
162 { 0x95, 0x0000 },
163 { 0x9a, 0x2184 },
164 { 0x9b, 0x010a },
165 { 0x9c, 0x0aea },
166 { 0x9d, 0x000c },
167 { 0x9e, 0x0400 },
168 { 0xa0, 0xa0a8 },
169 { 0xa1, 0x0059 },
170 { 0xa2, 0x0001 },
171 { 0xae, 0x6000 },
172 { 0xaf, 0x0000 },
173 { 0xb0, 0x6000 },
174 { 0xb1, 0x0000 },
175 { 0xb2, 0x0000 },
176 { 0xb3, 0x001f },
177 { 0xb4, 0x020c },
178 { 0xb5, 0x1f00 },
179 { 0xb6, 0x0000 },
180 { 0xbb, 0x0000 },
181 { 0xbc, 0x0000 },
182 { 0xbd, 0x0000 },
183 { 0xbe, 0x0000 },
184 { 0xbf, 0x3100 },
185 { 0xc0, 0x0000 },
186 { 0xc1, 0x0000 },
187 { 0xc2, 0x0000 },
188 { 0xc3, 0x2000 },
189 { 0xcd, 0x0000 },
190 { 0xce, 0x0000 },
191 { 0xcf, 0x1813 },
192 { 0xd0, 0x0690 },
193 { 0xd1, 0x1c17 },
194 { 0xd3, 0xb320 },
195 { 0xd4, 0x0000 },
196 { 0xd6, 0x0400 },
197 { 0xd9, 0x0809 },
198 { 0xda, 0x0000 },
199 { 0xdb, 0x0003 },
200 { 0xdc, 0x0049 },
201 { 0xdd, 0x001b },
Bard Liao5c4ca992015-01-21 20:50:15 +0800202 { 0xdf, 0x0008 },
203 { 0xe0, 0x4000 },
Oder Chiou1319b2f2014-04-28 19:59:10 +0800204 { 0xe6, 0x8000 },
205 { 0xe7, 0x0200 },
206 { 0xec, 0xb300 },
207 { 0xed, 0x0000 },
208 { 0xf0, 0x001f },
209 { 0xf1, 0x020c },
210 { 0xf2, 0x1f00 },
211 { 0xf3, 0x0000 },
212 { 0xf4, 0x4000 },
213 { 0xf8, 0x0000 },
214 { 0xf9, 0x0000 },
215 { 0xfa, 0x2060 },
216 { 0xfb, 0x4040 },
217 { 0xfc, 0x0000 },
218 { 0xfd, 0x0002 },
219 { 0xfe, 0x10ec },
220 { 0xff, 0x6308 },
221};
222
223static int rt5645_reset(struct snd_soc_codec *codec)
224{
225 return snd_soc_write(codec, RT5645_RESET, 0);
226}
227
228static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
229{
230 int i;
231
232 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
233 if (reg >= rt5645_ranges[i].range_min &&
234 reg <= rt5645_ranges[i].range_max) {
235 return true;
236 }
237 }
238
239 switch (reg) {
240 case RT5645_RESET:
241 case RT5645_PRIV_DATA:
242 case RT5645_IN1_CTRL1:
243 case RT5645_IN1_CTRL2:
244 case RT5645_IN1_CTRL3:
245 case RT5645_A_JD_CTRL1:
246 case RT5645_ADC_EQ_CTRL1:
247 case RT5645_EQ_CTRL1:
248 case RT5645_ALC_CTRL_1:
249 case RT5645_IRQ_CTRL2:
250 case RT5645_IRQ_CTRL3:
251 case RT5645_INT_IRQ_ST:
252 case RT5645_IL_CMD:
Bard Liao5c4ca992015-01-21 20:50:15 +0800253 case RT5650_4BTN_IL_CMD1:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800254 case RT5645_VENDOR_ID:
255 case RT5645_VENDOR_ID1:
256 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800257 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800258 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800259 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800260 }
261}
262
263static bool rt5645_readable_register(struct device *dev, unsigned int reg)
264{
265 int i;
266
267 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
268 if (reg >= rt5645_ranges[i].range_min &&
269 reg <= rt5645_ranges[i].range_max) {
270 return true;
271 }
272 }
273
274 switch (reg) {
275 case RT5645_RESET:
276 case RT5645_SPK_VOL:
277 case RT5645_HP_VOL:
278 case RT5645_LOUT1:
279 case RT5645_IN1_CTRL1:
280 case RT5645_IN1_CTRL2:
281 case RT5645_IN1_CTRL3:
282 case RT5645_IN2_CTRL:
283 case RT5645_INL1_INR1_VOL:
284 case RT5645_SPK_FUNC_LIM:
285 case RT5645_ADJ_HPF_CTRL:
286 case RT5645_DAC1_DIG_VOL:
287 case RT5645_DAC2_DIG_VOL:
288 case RT5645_DAC_CTRL:
289 case RT5645_STO1_ADC_DIG_VOL:
290 case RT5645_MONO_ADC_DIG_VOL:
291 case RT5645_ADC_BST_VOL1:
292 case RT5645_ADC_BST_VOL2:
293 case RT5645_STO1_ADC_MIXER:
294 case RT5645_MONO_ADC_MIXER:
295 case RT5645_AD_DA_MIXER:
296 case RT5645_STO_DAC_MIXER:
297 case RT5645_MONO_DAC_MIXER:
298 case RT5645_DIG_MIXER:
Bard Liao5c4ca992015-01-21 20:50:15 +0800299 case RT5650_A_DAC_SOUR:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800300 case RT5645_DIG_INF1_DATA:
301 case RT5645_PDM_OUT_CTRL:
302 case RT5645_REC_L1_MIXER:
303 case RT5645_REC_L2_MIXER:
304 case RT5645_REC_R1_MIXER:
305 case RT5645_REC_R2_MIXER:
306 case RT5645_HPMIXL_CTRL:
307 case RT5645_HPOMIXL_CTRL:
308 case RT5645_HPMIXR_CTRL:
309 case RT5645_HPOMIXR_CTRL:
310 case RT5645_HPO_MIXER:
311 case RT5645_SPK_L_MIXER:
312 case RT5645_SPK_R_MIXER:
313 case RT5645_SPO_MIXER:
314 case RT5645_SPO_CLSD_RATIO:
315 case RT5645_OUT_L1_MIXER:
316 case RT5645_OUT_R1_MIXER:
317 case RT5645_OUT_L_GAIN1:
318 case RT5645_OUT_L_GAIN2:
319 case RT5645_OUT_R_GAIN1:
320 case RT5645_OUT_R_GAIN2:
321 case RT5645_LOUT_MIXER:
322 case RT5645_HAPTIC_CTRL1:
323 case RT5645_HAPTIC_CTRL2:
324 case RT5645_HAPTIC_CTRL3:
325 case RT5645_HAPTIC_CTRL4:
326 case RT5645_HAPTIC_CTRL5:
327 case RT5645_HAPTIC_CTRL6:
328 case RT5645_HAPTIC_CTRL7:
329 case RT5645_HAPTIC_CTRL8:
330 case RT5645_HAPTIC_CTRL9:
331 case RT5645_HAPTIC_CTRL10:
332 case RT5645_PWR_DIG1:
333 case RT5645_PWR_DIG2:
334 case RT5645_PWR_ANLG1:
335 case RT5645_PWR_ANLG2:
336 case RT5645_PWR_MIXER:
337 case RT5645_PWR_VOL:
338 case RT5645_PRIV_INDEX:
339 case RT5645_PRIV_DATA:
340 case RT5645_I2S1_SDP:
341 case RT5645_I2S2_SDP:
342 case RT5645_ADDA_CLK1:
343 case RT5645_ADDA_CLK2:
344 case RT5645_DMIC_CTRL1:
345 case RT5645_DMIC_CTRL2:
346 case RT5645_TDM_CTRL_1:
347 case RT5645_TDM_CTRL_2:
Fang, Yang Adf078d22014-10-28 18:36:36 -0300348 case RT5645_TDM_CTRL_3:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800349 case RT5645_GLB_CLK:
350 case RT5645_PLL_CTRL1:
351 case RT5645_PLL_CTRL2:
352 case RT5645_ASRC_1:
353 case RT5645_ASRC_2:
354 case RT5645_ASRC_3:
355 case RT5645_ASRC_4:
356 case RT5645_DEPOP_M1:
357 case RT5645_DEPOP_M2:
358 case RT5645_DEPOP_M3:
359 case RT5645_MICBIAS:
360 case RT5645_A_JD_CTRL1:
361 case RT5645_VAD_CTRL4:
362 case RT5645_CLSD_OUT_CTRL:
363 case RT5645_ADC_EQ_CTRL1:
364 case RT5645_ADC_EQ_CTRL2:
365 case RT5645_EQ_CTRL1:
366 case RT5645_EQ_CTRL2:
367 case RT5645_ALC_CTRL_1:
368 case RT5645_ALC_CTRL_2:
369 case RT5645_ALC_CTRL_3:
370 case RT5645_ALC_CTRL_4:
371 case RT5645_ALC_CTRL_5:
372 case RT5645_JD_CTRL:
373 case RT5645_IRQ_CTRL1:
374 case RT5645_IRQ_CTRL2:
375 case RT5645_IRQ_CTRL3:
376 case RT5645_INT_IRQ_ST:
377 case RT5645_GPIO_CTRL1:
378 case RT5645_GPIO_CTRL2:
379 case RT5645_GPIO_CTRL3:
380 case RT5645_BASS_BACK:
381 case RT5645_MP3_PLUS1:
382 case RT5645_MP3_PLUS2:
383 case RT5645_ADJ_HPF1:
384 case RT5645_ADJ_HPF2:
385 case RT5645_HP_CALIB_AMP_DET:
386 case RT5645_SV_ZCD1:
387 case RT5645_SV_ZCD2:
388 case RT5645_IL_CMD:
389 case RT5645_IL_CMD2:
390 case RT5645_IL_CMD3:
Bard Liao5c4ca992015-01-21 20:50:15 +0800391 case RT5650_4BTN_IL_CMD1:
392 case RT5650_4BTN_IL_CMD2:
Oder Chiou1319b2f2014-04-28 19:59:10 +0800393 case RT5645_DRC1_HL_CTRL1:
394 case RT5645_DRC2_HL_CTRL1:
395 case RT5645_ADC_MONO_HP_CTRL1:
396 case RT5645_ADC_MONO_HP_CTRL2:
397 case RT5645_DRC2_CTRL1:
398 case RT5645_DRC2_CTRL2:
399 case RT5645_DRC2_CTRL3:
400 case RT5645_DRC2_CTRL4:
401 case RT5645_DRC2_CTRL5:
402 case RT5645_JD_CTRL3:
403 case RT5645_JD_CTRL4:
404 case RT5645_GEN_CTRL1:
405 case RT5645_GEN_CTRL2:
406 case RT5645_GEN_CTRL3:
407 case RT5645_VENDOR_ID:
408 case RT5645_VENDOR_ID1:
409 case RT5645_VENDOR_ID2:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800410 return true;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800411 default:
Oder Chiou71bfa9b2014-05-08 15:42:37 +0800412 return false;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800413 }
414}
415
416static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
417static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
418static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
419static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
420static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
421
422/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
423static unsigned int bst_tlv[] = {
424 TLV_DB_RANGE_HEAD(7),
425 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
426 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
427 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
428 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
429 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
430 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
431 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0),
432};
433
434static const char * const rt5645_tdm_data_swap_select[] = {
435 "L/R", "R/L", "L/L", "R/R"
436};
437
438static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
439 RT5645_TDM_CTRL_1, 6, rt5645_tdm_data_swap_select);
440
441static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
442 RT5645_TDM_CTRL_1, 4, rt5645_tdm_data_swap_select);
443
444static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
445 RT5645_TDM_CTRL_1, 2, rt5645_tdm_data_swap_select);
446
447static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot6_7_enum,
448 RT5645_TDM_CTRL_1, 0, rt5645_tdm_data_swap_select);
449
450static const char * const rt5645_tdm_adc_data_select[] = {
451 "1/2/R", "2/1/R", "R/1/2", "R/2/1"
452};
453
454static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_sel_enum,
455 RT5645_TDM_CTRL_1, 8,
456 rt5645_tdm_adc_data_select);
457
458static const struct snd_kcontrol_new rt5645_snd_controls[] = {
459 /* Speaker Output Volume */
460 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
461 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
462 SOC_DOUBLE_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
463 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
464
465 /* Headphone Output Volume */
466 SOC_DOUBLE("HP Channel Switch", RT5645_HP_VOL,
467 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
468 SOC_DOUBLE_TLV("HP Playback Volume", RT5645_HP_VOL,
469 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
470
471 /* OUTPUT Control */
472 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
473 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
474 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
475 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
476 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
477 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
478
479 /* DAC Digital Volume */
480 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
481 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
482 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
483 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
484 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
485 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 175, 0, dac_vol_tlv),
486
487 /* IN1/IN2 Control */
488 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
489 RT5645_BST_SFT1, 8, 0, bst_tlv),
490 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
491 RT5645_BST_SFT2, 8, 0, bst_tlv),
492
493 /* INL/INR Volume Control */
494 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
495 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
496
497 /* ADC Digital Volume Control */
498 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
499 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
500 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
501 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
502 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
503 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
504 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
505 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 127, 0, adc_vol_tlv),
506
507 /* ADC Boost Volume Control */
508 SOC_DOUBLE_TLV("STO1 ADC Boost Gain", RT5645_ADC_BST_VOL1,
509 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
510 adc_bst_tlv),
511 SOC_DOUBLE_TLV("STO2 ADC Boost Gain", RT5645_ADC_BST_VOL1,
512 RT5645_STO2_ADC_L_BST_SFT, RT5645_STO2_ADC_R_BST_SFT, 3, 0,
513 adc_bst_tlv),
514
515 /* I2S2 function select */
516 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
517 1, 1),
518
519 /* TDM */
520 SOC_ENUM("TDM Adc Slot0 1 Data", rt5645_tdm_adc_slot0_1_enum),
521 SOC_ENUM("TDM Adc Slot2 3 Data", rt5645_tdm_adc_slot2_3_enum),
522 SOC_ENUM("TDM Adc Slot4 5 Data", rt5645_tdm_adc_slot4_5_enum),
523 SOC_ENUM("TDM Adc Slot6 7 Data", rt5645_tdm_adc_slot6_7_enum),
524 SOC_ENUM("TDM IF1 ADC DATA Sel", rt5645_tdm_adc_sel_enum),
525 SOC_SINGLE("TDM IF1_DAC1_L Sel", RT5645_TDM_CTRL_3, 12, 7, 0),
526 SOC_SINGLE("TDM IF1_DAC1_R Sel", RT5645_TDM_CTRL_3, 8, 7, 0),
527 SOC_SINGLE("TDM IF1_DAC2_L Sel", RT5645_TDM_CTRL_3, 4, 7, 0),
528 SOC_SINGLE("TDM IF1_DAC2_R Sel", RT5645_TDM_CTRL_3, 0, 7, 0),
529};
530
531/**
532 * set_dmic_clk - Set parameter of dmic.
533 *
534 * @w: DAPM widget.
535 * @kcontrol: The kcontrol of this widget.
536 * @event: Event id.
537 *
Oder Chiou1319b2f2014-04-28 19:59:10 +0800538 */
539static int set_dmic_clk(struct snd_soc_dapm_widget *w,
540 struct snd_kcontrol *kcontrol, int event)
541{
542 struct snd_soc_codec *codec = w->codec;
543 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou49ef7922014-05-20 15:01:53 +0800544 int idx = -EINVAL;
Oder Chiou1319b2f2014-04-28 19:59:10 +0800545
Oder Chiou49ef7922014-05-20 15:01:53 +0800546 idx = rl6231_calc_dmic_clk(rt5645->sysclk);
Oder Chiou1319b2f2014-04-28 19:59:10 +0800547
548 if (idx < 0)
549 dev_err(codec->dev, "Failed to set DMIC clock\n");
550 else
551 snd_soc_update_bits(codec, RT5645_DMIC_CTRL1,
552 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
553 return idx;
554}
555
556static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
557 struct snd_soc_dapm_widget *sink)
558{
559 unsigned int val;
560
561 val = snd_soc_read(source->codec, RT5645_GLB_CLK);
562 val &= RT5645_SCLK_SRC_MASK;
563 if (val == RT5645_SCLK_SRC_PLL1)
564 return 1;
565 else
566 return 0;
567}
568
Bard Liao9e268352014-10-31 15:37:55 +0800569static int is_using_asrc(struct snd_soc_dapm_widget *source,
570 struct snd_soc_dapm_widget *sink)
571{
572 unsigned int reg, shift, val;
573
574 switch (source->shift) {
575 case 0:
576 reg = RT5645_ASRC_3;
577 shift = 0;
578 break;
579 case 1:
580 reg = RT5645_ASRC_3;
581 shift = 4;
582 break;
583 case 3:
584 reg = RT5645_ASRC_2;
585 shift = 0;
586 break;
587 case 8:
588 reg = RT5645_ASRC_2;
589 shift = 4;
590 break;
591 case 9:
592 reg = RT5645_ASRC_2;
593 shift = 8;
594 break;
595 case 10:
596 reg = RT5645_ASRC_2;
597 shift = 12;
598 break;
599 default:
600 return 0;
601 }
602
603 val = (snd_soc_read(source->codec, reg) >> shift) & 0xf;
604 switch (val) {
605 case 1:
606 case 2:
607 case 3:
608 case 4:
609 return 1;
610 default:
611 return 0;
612 }
613
614}
615
Oder Chiou1319b2f2014-04-28 19:59:10 +0800616/* Digital Mixer */
617static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
618 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
619 RT5645_M_ADC_L1_SFT, 1, 1),
620 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
621 RT5645_M_ADC_L2_SFT, 1, 1),
622};
623
624static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
625 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
626 RT5645_M_ADC_R1_SFT, 1, 1),
627 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
628 RT5645_M_ADC_R2_SFT, 1, 1),
629};
630
631static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
632 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
633 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
634 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
635 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
636};
637
638static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
639 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
640 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
641 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
642 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
643};
644
645static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
646 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
647 RT5645_M_ADCMIX_L_SFT, 1, 1),
648 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
649 RT5645_M_DAC1_L_SFT, 1, 1),
650};
651
652static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
653 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
654 RT5645_M_ADCMIX_R_SFT, 1, 1),
655 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_AD_DA_MIXER,
656 RT5645_M_DAC1_R_SFT, 1, 1),
657};
658
659static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
660 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
661 RT5645_M_DAC_L1_SFT, 1, 1),
662 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
663 RT5645_M_DAC_L2_SFT, 1, 1),
664 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
665 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
666};
667
668static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
669 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
670 RT5645_M_DAC_R1_SFT, 1, 1),
671 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
672 RT5645_M_DAC_R2_SFT, 1, 1),
673 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
674 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
675};
676
677static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
678 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
679 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
680 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
681 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
682 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
683 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
684};
685
686static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
687 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
688 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
689 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
690 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
691 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
692 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
693};
694
695static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
696 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
697 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
698 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
699 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
700 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
701 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
702};
703
704static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
705 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
706 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
707 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
708 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
709 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
710 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
711};
712
713/* Analog Input Mixer */
714static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
715 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
716 RT5645_M_HP_L_RM_L_SFT, 1, 1),
717 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
718 RT5645_M_IN_L_RM_L_SFT, 1, 1),
719 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
720 RT5645_M_BST2_RM_L_SFT, 1, 1),
721 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
722 RT5645_M_BST1_RM_L_SFT, 1, 1),
723 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
724 RT5645_M_OM_L_RM_L_SFT, 1, 1),
725};
726
727static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
728 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
729 RT5645_M_HP_R_RM_R_SFT, 1, 1),
730 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
731 RT5645_M_IN_R_RM_R_SFT, 1, 1),
732 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
733 RT5645_M_BST2_RM_R_SFT, 1, 1),
734 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
735 RT5645_M_BST1_RM_R_SFT, 1, 1),
736 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
737 RT5645_M_OM_R_RM_R_SFT, 1, 1),
738};
739
740static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
741 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
742 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
743 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
744 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
745 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
746 RT5645_M_IN_L_SM_L_SFT, 1, 1),
747 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
748 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
749};
750
751static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
752 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
753 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
754 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
755 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
756 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
757 RT5645_M_IN_R_SM_R_SFT, 1, 1),
758 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
759 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
760};
761
762static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
763 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
764 RT5645_M_BST1_OM_L_SFT, 1, 1),
765 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
766 RT5645_M_IN_L_OM_L_SFT, 1, 1),
767 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
768 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
769 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
770 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
771};
772
773static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
774 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
775 RT5645_M_BST2_OM_R_SFT, 1, 1),
776 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
777 RT5645_M_IN_R_OM_R_SFT, 1, 1),
778 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
779 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
780 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
781 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
782};
783
784static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
785 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
786 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
787 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
788 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
789 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
790 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
791 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
792 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
793};
794
795static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
796 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
797 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
798 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
799 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
800};
801
802static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
803 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
804 RT5645_M_DAC1_HM_SFT, 1, 1),
805 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
806 RT5645_M_HPVOL_HM_SFT, 1, 1),
807};
808
809static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
810 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
811 RT5645_M_DAC1_HV_SFT, 1, 1),
812 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
813 RT5645_M_DAC2_HV_SFT, 1, 1),
814 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
815 RT5645_M_IN_HV_SFT, 1, 1),
816 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
817 RT5645_M_BST1_HV_SFT, 1, 1),
818};
819
820static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
821 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
822 RT5645_M_DAC1_HV_SFT, 1, 1),
823 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
824 RT5645_M_DAC2_HV_SFT, 1, 1),
825 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
826 RT5645_M_IN_HV_SFT, 1, 1),
827 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
828 RT5645_M_BST2_HV_SFT, 1, 1),
829};
830
831static const struct snd_kcontrol_new rt5645_lout_mix[] = {
832 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
833 RT5645_M_DAC_L1_LM_SFT, 1, 1),
834 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
835 RT5645_M_DAC_R1_LM_SFT, 1, 1),
836 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
837 RT5645_M_OV_L_LM_SFT, 1, 1),
838 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
839 RT5645_M_OV_R_LM_SFT, 1, 1),
840};
841
842/*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
843static const char * const rt5645_dac1_src[] = {
844 "IF1 DAC", "IF2 DAC", "IF3 DAC"
845};
846
847static SOC_ENUM_SINGLE_DECL(
848 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
849 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
850
851static const struct snd_kcontrol_new rt5645_dac1l_mux =
852 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
853
854static SOC_ENUM_SINGLE_DECL(
855 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
856 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
857
858static const struct snd_kcontrol_new rt5645_dac1r_mux =
859 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
860
861/*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
862static const char * const rt5645_dac12_src[] = {
863 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
864};
865
866static SOC_ENUM_SINGLE_DECL(
867 rt5645_dac2l_enum, RT5645_DAC_CTRL,
868 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
869
870static const struct snd_kcontrol_new rt5645_dac_l2_mux =
871 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
872
873static const char * const rt5645_dacr2_src[] = {
874 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
875};
876
877static SOC_ENUM_SINGLE_DECL(
878 rt5645_dac2r_enum, RT5645_DAC_CTRL,
879 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
880
881static const struct snd_kcontrol_new rt5645_dac_r2_mux =
882 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
883
884
885/* INL/R source */
886static const char * const rt5645_inl_src[] = {
887 "IN2P", "MonoP"
888};
889
890static SOC_ENUM_SINGLE_DECL(
891 rt5645_inl_enum, RT5645_INL1_INR1_VOL,
892 RT5645_INL_SEL_SFT, rt5645_inl_src);
893
894static const struct snd_kcontrol_new rt5645_inl_mux =
895 SOC_DAPM_ENUM("INL source", rt5645_inl_enum);
896
897static const char * const rt5645_inr_src[] = {
898 "IN2N", "MonoN"
899};
900
901static SOC_ENUM_SINGLE_DECL(
902 rt5645_inr_enum, RT5645_INL1_INR1_VOL,
903 RT5645_INR_SEL_SFT, rt5645_inr_src);
904
905static const struct snd_kcontrol_new rt5645_inr_mux =
906 SOC_DAPM_ENUM("INR source", rt5645_inr_enum);
907
908/* Stereo1 ADC source */
909/* MX-27 [12] */
910static const char * const rt5645_stereo_adc1_src[] = {
911 "DAC MIX", "ADC"
912};
913
914static SOC_ENUM_SINGLE_DECL(
915 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
916 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
917
918static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
919 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
920
921/* MX-27 [11] */
922static const char * const rt5645_stereo_adc2_src[] = {
923 "DAC MIX", "DMIC"
924};
925
926static SOC_ENUM_SINGLE_DECL(
927 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
928 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
929
930static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
931 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
932
933/* MX-27 [8] */
934static const char * const rt5645_stereo_dmic_src[] = {
935 "DMIC1", "DMIC2"
936};
937
938static SOC_ENUM_SINGLE_DECL(
939 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
940 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
941
942static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
943 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
944
945/* Mono ADC source */
946/* MX-28 [12] */
947static const char * const rt5645_mono_adc_l1_src[] = {
948 "Mono DAC MIXL", "ADC"
949};
950
951static SOC_ENUM_SINGLE_DECL(
952 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
953 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
954
955static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
956 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
957/* MX-28 [11] */
958static const char * const rt5645_mono_adc_l2_src[] = {
959 "Mono DAC MIXL", "DMIC"
960};
961
962static SOC_ENUM_SINGLE_DECL(
963 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
964 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
965
966static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
967 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
968
969/* MX-28 [8] */
970static const char * const rt5645_mono_dmic_src[] = {
971 "DMIC1", "DMIC2"
972};
973
974static SOC_ENUM_SINGLE_DECL(
975 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
976 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
977
978static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
979 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
980/* MX-28 [1:0] */
981static SOC_ENUM_SINGLE_DECL(
982 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
983 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
984
985static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
986 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
987/* MX-28 [4] */
988static const char * const rt5645_mono_adc_r1_src[] = {
989 "Mono DAC MIXR", "ADC"
990};
991
992static SOC_ENUM_SINGLE_DECL(
993 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
994 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
995
996static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
997 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
998/* MX-28 [3] */
999static const char * const rt5645_mono_adc_r2_src[] = {
1000 "Mono DAC MIXR", "DMIC"
1001};
1002
1003static SOC_ENUM_SINGLE_DECL(
1004 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1005 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1006
1007static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1008 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1009
1010/* MX-77 [9:8] */
1011static const char * const rt5645_if1_adc_in_src[] = {
1012 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1013};
1014
1015static SOC_ENUM_SINGLE_DECL(
1016 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1017 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1018
1019static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1020 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1021
Bard Liao5c4ca992015-01-21 20:50:15 +08001022/* MX-2d [3] [2] */
1023static const char * const rt5650_a_dac1_src[] = {
1024 "DAC1", "Stereo DAC Mixer"
1025};
1026
1027static SOC_ENUM_SINGLE_DECL(
1028 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1029 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1030
1031static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1032 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1033
1034static SOC_ENUM_SINGLE_DECL(
1035 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1036 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1037
1038static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1039 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1040
1041/* MX-2d [1] [0] */
1042static const char * const rt5650_a_dac2_src[] = {
1043 "Stereo DAC Mixer", "Mono DAC Mixer"
1044};
1045
1046static SOC_ENUM_SINGLE_DECL(
1047 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1048 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1049
1050static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1051 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1052
1053static SOC_ENUM_SINGLE_DECL(
1054 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1055 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1056
1057static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1058 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1059
Oder Chiou1319b2f2014-04-28 19:59:10 +08001060/* MX-2F [13:12] */
1061static const char * const rt5645_if2_adc_in_src[] = {
1062 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1063};
1064
1065static SOC_ENUM_SINGLE_DECL(
1066 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1067 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1068
1069static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1070 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1071
1072/* MX-2F [1:0] */
1073static const char * const rt5645_if3_adc_in_src[] = {
1074 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1075};
1076
1077static SOC_ENUM_SINGLE_DECL(
1078 rt5645_if3_adc_in_enum, RT5645_DIG_INF1_DATA,
1079 RT5645_IF3_ADC_IN_SFT, rt5645_if3_adc_in_src);
1080
1081static const struct snd_kcontrol_new rt5645_if3_adc_in_mux =
1082 SOC_DAPM_ENUM("IF3 ADC IN source", rt5645_if3_adc_in_enum);
1083
1084/* MX-31 [15] [13] [11] [9] */
1085static const char * const rt5645_pdm_src[] = {
1086 "Mono DAC", "Stereo DAC"
1087};
1088
1089static SOC_ENUM_SINGLE_DECL(
1090 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1091 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1092
1093static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1094 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1095
1096static SOC_ENUM_SINGLE_DECL(
1097 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1098 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1099
1100static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1101 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1102
1103/* MX-9D [9:8] */
1104static const char * const rt5645_vad_adc_src[] = {
1105 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1106};
1107
1108static SOC_ENUM_SINGLE_DECL(
1109 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1110 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1111
1112static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1113 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1114
1115static const struct snd_kcontrol_new spk_l_vol_control =
1116 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1117 RT5645_L_MUTE_SFT, 1, 1);
1118
1119static const struct snd_kcontrol_new spk_r_vol_control =
1120 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1121 RT5645_R_MUTE_SFT, 1, 1);
1122
1123static const struct snd_kcontrol_new hp_l_vol_control =
1124 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1125 RT5645_L_MUTE_SFT, 1, 1);
1126
1127static const struct snd_kcontrol_new hp_r_vol_control =
1128 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1129 RT5645_R_MUTE_SFT, 1, 1);
1130
1131static const struct snd_kcontrol_new pdm1_l_vol_control =
1132 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1133 RT5645_M_PDM1_L, 1, 1);
1134
1135static const struct snd_kcontrol_new pdm1_r_vol_control =
1136 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1137 RT5645_M_PDM1_R, 1, 1);
1138
1139static void hp_amp_power(struct snd_soc_codec *codec, int on)
1140{
1141 static int hp_amp_power_count;
1142 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1143
1144 if (on) {
1145 if (hp_amp_power_count <= 0) {
1146 /* depop parameters */
1147 snd_soc_update_bits(codec, RT5645_DEPOP_M2,
1148 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1149 snd_soc_write(codec, RT5645_DEPOP_M1, 0x000d);
1150 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1151 RT5645_HP_DCC_INT1, 0x9f01);
1152 mdelay(150);
1153 /* headphone amp power on */
1154 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1155 RT5645_PWR_FV1 | RT5645_PWR_FV2 , 0);
1156 snd_soc_update_bits(codec, RT5645_PWR_VOL,
1157 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1158 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1159 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1160 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1161 RT5645_PWR_HA,
1162 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1163 RT5645_PWR_HA);
1164 mdelay(5);
1165 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1166 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1167 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1168
1169 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1170 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1171 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1172 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1173 0x14, 0x1aaa);
1174 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1175 0x24, 0x0430);
1176 }
1177 hp_amp_power_count++;
1178 } else {
1179 hp_amp_power_count--;
1180 if (hp_amp_power_count <= 0) {
1181 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1182 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1183 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1184 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1185 /* headphone amp power down */
1186 snd_soc_write(codec, RT5645_DEPOP_M1, 0x0000);
1187 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1188 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1189 RT5645_PWR_HA, 0);
1190 }
1191 }
1192}
1193
1194static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1195 struct snd_kcontrol *kcontrol, int event)
1196{
1197 struct snd_soc_codec *codec = w->codec;
1198 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1199
1200 switch (event) {
1201 case SND_SOC_DAPM_POST_PMU:
1202 hp_amp_power(codec, 1);
1203 /* headphone unmute sequence */
Bard Liao5c4ca992015-01-21 20:50:15 +08001204 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1205 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1206 } else {
1207 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1208 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1209 RT5645_CP_FQ3_MASK,
1210 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1211 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1212 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1213 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001214 regmap_write(rt5645->regmap,
1215 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1216 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1217 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1218 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1219 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1220 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1221 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1222 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1223 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1224 msleep(40);
1225 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1226 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1227 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1228 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1229 break;
1230
1231 case SND_SOC_DAPM_PRE_PMD:
1232 /* headphone mute sequence */
Bard Liao5c4ca992015-01-21 20:50:15 +08001233 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1234 snd_soc_write(codec, RT5645_DEPOP_M3, 0x0737);
1235 } else {
1236 snd_soc_update_bits(codec, RT5645_DEPOP_M3,
1237 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1238 RT5645_CP_FQ3_MASK,
1239 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1240 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1241 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1242 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08001243 regmap_write(rt5645->regmap,
1244 RT5645_PR_BASE + RT5645_MAMP_INT_REG2, 0xfc00);
1245 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1246 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1247 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1248 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1249 snd_soc_update_bits(codec, RT5645_DEPOP_M1,
1250 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1251 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1252 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1253 msleep(30);
1254 hp_amp_power(codec, 0);
1255 break;
1256
1257 default:
1258 return 0;
1259 }
1260
1261 return 0;
1262}
1263
1264static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1265 struct snd_kcontrol *kcontrol, int event)
1266{
1267 struct snd_soc_codec *codec = w->codec;
Oder Chiou1319b2f2014-04-28 19:59:10 +08001268
1269 switch (event) {
1270 case SND_SOC_DAPM_POST_PMU:
1271 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1272 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1273 RT5645_PWR_CLS_D_L,
1274 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1275 RT5645_PWR_CLS_D_L);
1276 break;
1277
1278 case SND_SOC_DAPM_PRE_PMD:
1279 snd_soc_update_bits(codec, RT5645_PWR_DIG1,
1280 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1281 RT5645_PWR_CLS_D_L, 0);
1282 break;
1283
1284 default:
1285 return 0;
1286 }
1287
1288 return 0;
1289}
1290
1291static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1292 struct snd_kcontrol *kcontrol, int event)
1293{
1294 struct snd_soc_codec *codec = w->codec;
1295
1296 switch (event) {
1297 case SND_SOC_DAPM_POST_PMU:
1298 hp_amp_power(codec, 1);
1299 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1300 RT5645_PWR_LM, RT5645_PWR_LM);
1301 snd_soc_update_bits(codec, RT5645_LOUT1,
1302 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1303 break;
1304
1305 case SND_SOC_DAPM_PRE_PMD:
1306 snd_soc_update_bits(codec, RT5645_LOUT1,
1307 RT5645_L_MUTE | RT5645_R_MUTE,
1308 RT5645_L_MUTE | RT5645_R_MUTE);
1309 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
1310 RT5645_PWR_LM, 0);
1311 hp_amp_power(codec, 0);
1312 break;
1313
1314 default:
1315 return 0;
1316 }
1317
1318 return 0;
1319}
1320
1321static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1322 struct snd_kcontrol *kcontrol, int event)
1323{
1324 struct snd_soc_codec *codec = w->codec;
1325
1326 switch (event) {
1327 case SND_SOC_DAPM_POST_PMU:
1328 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1329 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1330 break;
1331
1332 case SND_SOC_DAPM_PRE_PMD:
1333 snd_soc_update_bits(codec, RT5645_PWR_ANLG2,
1334 RT5645_PWR_BST2_P, 0);
1335 break;
1336
1337 default:
1338 return 0;
1339 }
1340
1341 return 0;
1342}
1343
1344static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1345 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1346 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1347 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1348 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1349
1350 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1351 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1352 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1353 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1354
Bard Liao9e268352014-10-31 15:37:55 +08001355 /* ASRC */
1356 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1357 11, 0, NULL, 0),
1358 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1359 12, 0, NULL, 0),
1360 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1361 10, 0, NULL, 0),
1362 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1363 9, 0, NULL, 0),
1364 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1365 8, 0, NULL, 0),
1366 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1367 7, 0, NULL, 0),
1368 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1369 5, 0, NULL, 0),
1370 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1371 4, 0, NULL, 0),
1372 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1373 3, 0, NULL, 0),
1374 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1375 1, 0, NULL, 0),
1376 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1377 0, 0, NULL, 0),
1378
Oder Chiou1319b2f2014-04-28 19:59:10 +08001379 /* Input Side */
1380 /* micbias */
1381 SND_SOC_DAPM_MICBIAS("micbias1", RT5645_PWR_ANLG2,
1382 RT5645_PWR_MB1_BIT, 0),
1383 SND_SOC_DAPM_MICBIAS("micbias2", RT5645_PWR_ANLG2,
1384 RT5645_PWR_MB2_BIT, 0),
1385 /* Input Lines */
1386 SND_SOC_DAPM_INPUT("DMIC L1"),
1387 SND_SOC_DAPM_INPUT("DMIC R1"),
1388 SND_SOC_DAPM_INPUT("DMIC L2"),
1389 SND_SOC_DAPM_INPUT("DMIC R2"),
1390
1391 SND_SOC_DAPM_INPUT("IN1P"),
1392 SND_SOC_DAPM_INPUT("IN1N"),
1393 SND_SOC_DAPM_INPUT("IN2P"),
1394 SND_SOC_DAPM_INPUT("IN2N"),
1395
1396 SND_SOC_DAPM_INPUT("Haptic Generator"),
1397
1398 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1399 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1400 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
1401 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
1402 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
1403 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
1404 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
1405 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
1406 /* Boost */
1407 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
1408 RT5645_PWR_BST1_BIT, 0, NULL, 0),
1409 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
1410 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
1411 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1412 /* Input Volume */
1413 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
1414 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
1415 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
1416 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
1417 /* REC Mixer */
1418 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
1419 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
1420 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
1421 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
1422 /* ADCs */
1423 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
1424 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
1425
1426 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
1427 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
1428 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
1429 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
1430
1431 /* ADC Mux */
1432 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
1433 &rt5645_sto1_dmic_mux),
1434 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1435 &rt5645_sto_adc2_mux),
1436 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1437 &rt5645_sto_adc2_mux),
1438 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1439 &rt5645_sto_adc1_mux),
1440 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1441 &rt5645_sto_adc1_mux),
1442 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
1443 &rt5645_mono_dmic_l_mux),
1444 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
1445 &rt5645_mono_dmic_r_mux),
1446 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
1447 &rt5645_mono_adc_l2_mux),
1448 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
1449 &rt5645_mono_adc_l1_mux),
1450 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
1451 &rt5645_mono_adc_r1_mux),
1452 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1453 &rt5645_mono_adc_r2_mux),
1454 /* ADC Mixer */
1455
1456 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
1457 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
1458 SND_SOC_DAPM_SUPPLY_S("adc stereo2 filter", 1, RT5645_PWR_DIG2,
1459 RT5645_PWR_ADC_S2F_BIT, 0, NULL, 0),
1460 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
1461 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
1462 NULL, 0),
1463 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
1464 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
1465 NULL, 0),
1466 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
1467 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
1468 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
1469 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
1470 NULL, 0),
1471 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
1472 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
1473 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
1474 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
1475 NULL, 0),
1476
1477 /* ADC PGA */
1478 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
1479 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
1480 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
1481 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1482 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1483 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1484 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1485 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1486 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
1487 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
1488
1489 /* IF1 2 Mux */
1490 SND_SOC_DAPM_MUX("IF1 ADC Mux", SND_SOC_NOPM,
1491 0, 0, &rt5645_if1_adc_in_mux),
1492 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
1493 0, 0, &rt5645_if2_adc_in_mux),
1494
1495 /* Digital Interface */
1496 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
1497 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
1498 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
1499 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
1500 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1501 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1502 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
1503 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
1504 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1505 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1506 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1507 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
1508 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
1509 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
1510 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
1511 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
1512 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
1513
1514 /* Digital Interface Select */
1515 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
1516 0, 0, &rt5645_vad_adc_mux),
1517
1518 /* Audio Interface */
1519 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1520 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
1521 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1522 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1523
1524 /* Output Side */
1525 /* DAC mixer before sound effect */
1526 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
1527 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
1528 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
1529 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
1530
1531 /* DAC2 channel Mux */
1532 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
1533 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1534 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
1535 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
1536 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1537 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
1538
1539 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
1540 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
1541
1542 /* DAC Mixer */
1543 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
1544 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
1545 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
1546 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
1547 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
1548 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
1549 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
1550 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
1551 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
1552 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
1553 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
1554 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
1555 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
1556 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
1557 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
1558 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
1559 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
1560 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
1561
1562 /* DACs */
1563 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
1564 0),
1565 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
1566 0),
1567 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
1568 0),
1569 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
1570 0),
1571 /* OUT Mixer */
1572 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
1573 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
1574 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
1575 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
1576 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
1577 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
1578 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
1579 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
1580 /* Ouput Volume */
1581 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
1582 &spk_l_vol_control),
1583 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
1584 &spk_r_vol_control),
1585 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
1586 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
1587 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
1588 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
1589 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
1590 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
1591 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
1592 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
1593 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
1594 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
1595 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
1596 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
1597 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
1598
1599 /* HPO/LOUT/Mono Mixer */
1600 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
1601 ARRAY_SIZE(rt5645_spo_l_mix)),
1602 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
1603 ARRAY_SIZE(rt5645_spo_r_mix)),
1604 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
1605 ARRAY_SIZE(rt5645_hpo_mix)),
1606 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
1607 ARRAY_SIZE(rt5645_lout_mix)),
1608
1609 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
1610 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1611 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
1612 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1613 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
1614 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1615
1616 /* PDM */
1617 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
1618 0, NULL, 0),
1619 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
1620 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
1621
1622 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
1623 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
1624
1625 /* Output Lines */
1626 SND_SOC_DAPM_OUTPUT("HPOL"),
1627 SND_SOC_DAPM_OUTPUT("HPOR"),
1628 SND_SOC_DAPM_OUTPUT("LOUTL"),
1629 SND_SOC_DAPM_OUTPUT("LOUTR"),
1630 SND_SOC_DAPM_OUTPUT("PDM1L"),
1631 SND_SOC_DAPM_OUTPUT("PDM1R"),
1632 SND_SOC_DAPM_OUTPUT("SPOL"),
1633 SND_SOC_DAPM_OUTPUT("SPOR"),
1634};
1635
Bard Liao5c4ca992015-01-21 20:50:15 +08001636static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
1637 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
1638 0, 0, &rt5650_a_dac1_l_mux),
1639 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
1640 0, 0, &rt5650_a_dac1_r_mux),
1641 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
1642 0, 0, &rt5650_a_dac2_l_mux),
1643 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
1644 0, 0, &rt5650_a_dac2_r_mux),
1645};
1646
Oder Chiou1319b2f2014-04-28 19:59:10 +08001647static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
Bard Liao9e268352014-10-31 15:37:55 +08001648 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
1649 { "adc stereo2 filter", NULL, "ADC STO2 ASRC", is_using_asrc },
1650 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
1651 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
1652 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
1653 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
1654 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
1655
1656 { "I2S1", NULL, "I2S1 ASRC" },
1657 { "I2S2", NULL, "I2S2 ASRC" },
1658
Oder Chiou1319b2f2014-04-28 19:59:10 +08001659 { "IN1P", NULL, "LDO2" },
1660 { "IN2P", NULL, "LDO2" },
1661
1662 { "DMIC1", NULL, "DMIC L1" },
1663 { "DMIC1", NULL, "DMIC R1" },
1664 { "DMIC2", NULL, "DMIC L2" },
1665 { "DMIC2", NULL, "DMIC R2" },
1666
1667 { "BST1", NULL, "IN1P" },
1668 { "BST1", NULL, "IN1N" },
1669 { "BST1", NULL, "JD Power" },
1670 { "BST1", NULL, "Mic Det Power" },
1671 { "BST2", NULL, "IN2P" },
1672 { "BST2", NULL, "IN2N" },
1673
1674 { "INL VOL", NULL, "IN2P" },
1675 { "INR VOL", NULL, "IN2N" },
1676
1677 { "RECMIXL", "HPOL Switch", "HPOL" },
1678 { "RECMIXL", "INL Switch", "INL VOL" },
1679 { "RECMIXL", "BST2 Switch", "BST2" },
1680 { "RECMIXL", "BST1 Switch", "BST1" },
1681 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
1682
1683 { "RECMIXR", "HPOR Switch", "HPOR" },
1684 { "RECMIXR", "INR Switch", "INR VOL" },
1685 { "RECMIXR", "BST2 Switch", "BST2" },
1686 { "RECMIXR", "BST1 Switch", "BST1" },
1687 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
1688
1689 { "ADC L", NULL, "RECMIXL" },
1690 { "ADC L", NULL, "ADC L power" },
1691 { "ADC R", NULL, "RECMIXR" },
1692 { "ADC R", NULL, "ADC R power" },
1693
1694 {"DMIC L1", NULL, "DMIC CLK"},
1695 {"DMIC L1", NULL, "DMIC1 Power"},
1696 {"DMIC R1", NULL, "DMIC CLK"},
1697 {"DMIC R1", NULL, "DMIC1 Power"},
1698 {"DMIC L2", NULL, "DMIC CLK"},
1699 {"DMIC L2", NULL, "DMIC2 Power"},
1700 {"DMIC R2", NULL, "DMIC CLK"},
1701 {"DMIC R2", NULL, "DMIC2 Power"},
1702
1703 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
1704 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
Bard Liao9e268352014-10-31 15:37:55 +08001705 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001706
1707 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
1708 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
Bard Liao9e268352014-10-31 15:37:55 +08001709 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001710
1711 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
1712 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
Bard Liao9e268352014-10-31 15:37:55 +08001713 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001714
1715 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1716 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
1717 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
1718 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
1719
1720 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
1721 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
1722 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
1723 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
1724
1725 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
1726 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1727 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
1728 { "Mono ADC L1 Mux", "ADC", "ADC L" },
1729
1730 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1731 { "Mono ADC R1 Mux", "ADC", "ADC R" },
1732 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
1733 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
1734
1735 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
1736 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
1737 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
1738 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
1739
1740 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
1741 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
1742 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1743
1744 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
1745 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
1746 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
1747
1748 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
1749 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
1750 { "Mono ADC MIXL", NULL, "adc mono left filter" },
1751 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
1752
1753 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
1754 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
1755 { "Mono ADC MIXR", NULL, "adc mono right filter" },
1756 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
1757
1758 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
1759 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
1760 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
1761
1762 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
1763 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
1764 { "IF_ADC2", NULL, "Mono ADC MIXL" },
1765 { "IF_ADC2", NULL, "Mono ADC MIXR" },
1766 { "VAD_ADC", NULL, "VAD ADC Mux" },
1767
1768 { "IF1 ADC Mux", "IF_ADC1", "IF_ADC1" },
1769 { "IF1 ADC Mux", "IF_ADC2", "IF_ADC2" },
1770 { "IF1 ADC Mux", "VAD_ADC", "VAD_ADC" },
1771
1772 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
1773 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
1774 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
1775
1776 { "IF1 ADC", NULL, "I2S1" },
1777 { "IF1 ADC", NULL, "IF1 ADC Mux" },
1778 { "IF2 ADC", NULL, "I2S2" },
1779 { "IF2 ADC", NULL, "IF2 ADC Mux" },
1780
1781 { "AIF1TX", NULL, "IF1 ADC" },
1782 { "AIF1TX", NULL, "IF2 ADC" },
1783 { "AIF2TX", NULL, "IF2 ADC" },
1784
1785 { "IF1 DAC1", NULL, "AIF1RX" },
1786 { "IF1 DAC2", NULL, "AIF1RX" },
1787 { "IF2 DAC", NULL, "AIF2RX" },
1788
1789 { "IF1 DAC1", NULL, "I2S1" },
1790 { "IF1 DAC2", NULL, "I2S1" },
1791 { "IF2 DAC", NULL, "I2S2" },
1792
1793 { "IF1 DAC2 L", NULL, "IF1 DAC2" },
1794 { "IF1 DAC2 R", NULL, "IF1 DAC2" },
1795 { "IF1 DAC1 L", NULL, "IF1 DAC1" },
1796 { "IF1 DAC1 R", NULL, "IF1 DAC1" },
1797 { "IF2 DAC L", NULL, "IF2 DAC" },
1798 { "IF2 DAC R", NULL, "IF2 DAC" },
1799
1800 { "DAC1 L Mux", "IF1 DAC", "IF1 DAC1 L" },
1801 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
1802
1803 { "DAC1 R Mux", "IF1 DAC", "IF1 DAC1 R" },
1804 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
1805
1806 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
1807 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
1808 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
1809 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
1810 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
1811 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
1812
1813 { "DAC L2 Mux", "IF1 DAC", "IF1 DAC2 L" },
1814 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
1815 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
1816 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
1817 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
1818 { "DAC L2 Volume", NULL, "dac mono left filter" },
1819
1820 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
1821 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
1822 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
1823 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
1824 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
1825 { "DAC R2 Volume", NULL, "dac mono right filter" },
1826
1827 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1828 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
1829 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1830 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
1831 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1832 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
1833 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1834 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
1835
1836 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
1837 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1838 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1839 { "Mono DAC MIXL", NULL, "dac mono left filter" },
1840 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
1841 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1842 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1843 { "Mono DAC MIXR", NULL, "dac mono right filter" },
1844
1845 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
1846 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
1847 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
1848 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
1849 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
1850 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
1851
Oder Chiou1319b2f2014-04-28 19:59:10 +08001852 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001853 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001854 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
Oder Chiou1319b2f2014-04-28 19:59:10 +08001855 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
1856
1857 { "SPK MIXL", "BST1 Switch", "BST1" },
1858 { "SPK MIXL", "INL Switch", "INL VOL" },
1859 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
1860 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
1861 { "SPK MIXR", "BST2 Switch", "BST2" },
1862 { "SPK MIXR", "INR Switch", "INR VOL" },
1863 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
1864 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
1865
1866 { "OUT MIXL", "BST1 Switch", "BST1" },
1867 { "OUT MIXL", "INL Switch", "INL VOL" },
1868 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
1869 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
1870
1871 { "OUT MIXR", "BST2 Switch", "BST2" },
1872 { "OUT MIXR", "INR Switch", "INR VOL" },
1873 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
1874 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
1875
1876 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
1877 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
1878 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
1879 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
1880 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
1881 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
1882 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
1883 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
1884 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
1885 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
1886
1887 { "DAC 2", NULL, "DAC L2" },
1888 { "DAC 2", NULL, "DAC R2" },
1889 { "DAC 1", NULL, "DAC L1" },
1890 { "DAC 1", NULL, "DAC R1" },
1891 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
1892 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
1893 { "HPOVOL", NULL, "HPOVOL L" },
1894 { "HPOVOL", NULL, "HPOVOL R" },
1895 { "HPO MIX", "DAC1 Switch", "DAC 1" },
1896 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
1897
1898 { "SPKVOL L", "Switch", "SPK MIXL" },
1899 { "SPKVOL R", "Switch", "SPK MIXR" },
1900
1901 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
1902 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
1903 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
1904 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
1905 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
1906 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
1907
1908 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
1909 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
1910 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
1911 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
1912
1913 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
1914 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
1915 { "PDM1 L Mux", NULL, "PDM1 Power" },
1916 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
1917 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
1918 { "PDM1 R Mux", NULL, "PDM1 Power" },
1919
1920 { "HP amp", NULL, "HPO MIX" },
1921 { "HP amp", NULL, "JD Power" },
1922 { "HP amp", NULL, "Mic Det Power" },
1923 { "HP amp", NULL, "LDO2" },
1924 { "HPOL", NULL, "HP amp" },
1925 { "HPOR", NULL, "HP amp" },
1926
1927 { "LOUT amp", NULL, "LOUT MIX" },
1928 { "LOUTL", NULL, "LOUT amp" },
1929 { "LOUTR", NULL, "LOUT amp" },
1930
1931 { "PDM1 L", "Switch", "PDM1 L Mux" },
1932 { "PDM1 R", "Switch", "PDM1 R Mux" },
1933
1934 { "PDM1L", NULL, "PDM1 L" },
1935 { "PDM1R", NULL, "PDM1 R" },
1936
1937 { "SPK amp", NULL, "SPOL MIX" },
1938 { "SPK amp", NULL, "SPOR MIX" },
1939 { "SPOL", NULL, "SPK amp" },
1940 { "SPOR", NULL, "SPK amp" },
1941};
1942
Bard Liao5c4ca992015-01-21 20:50:15 +08001943static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
1944 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
1945 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
1946 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
1947 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
1948
1949 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
1950 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
1951 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
1952 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
1953
1954 { "DAC L1", NULL, "A DAC1 L Mux" },
1955 { "DAC R1", NULL, "A DAC1 R Mux" },
1956 { "DAC L2", NULL, "A DAC2 L Mux" },
1957 { "DAC R2", NULL, "A DAC2 R Mux" },
1958};
1959
1960static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
1961 { "DAC L1", NULL, "Stereo DAC MIXL" },
1962 { "DAC R1", NULL, "Stereo DAC MIXR" },
1963 { "DAC L2", NULL, "Mono DAC MIXL" },
1964 { "DAC R2", NULL, "Mono DAC MIXR" },
1965};
1966
Oder Chiou1319b2f2014-04-28 19:59:10 +08001967static int rt5645_hw_params(struct snd_pcm_substream *substream,
1968 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1969{
1970 struct snd_soc_codec *codec = dai->codec;
1971 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
1972 unsigned int val_len = 0, val_clk, mask_clk;
1973 int pre_div, bclk_ms, frame_size;
1974
1975 rt5645->lrck[dai->id] = params_rate(params);
Oder Chioud92950e2014-05-20 15:01:55 +08001976 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
Oder Chiou1319b2f2014-04-28 19:59:10 +08001977 if (pre_div < 0) {
1978 dev_err(codec->dev, "Unsupported clock setting\n");
1979 return -EINVAL;
1980 }
1981 frame_size = snd_soc_params_to_frame_size(params);
1982 if (frame_size < 0) {
1983 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
1984 return -EINVAL;
1985 }
1986 bclk_ms = frame_size > 32;
1987 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
1988
1989 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
1990 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
1991 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1992 bclk_ms, pre_div, dai->id);
1993
1994 switch (params_width(params)) {
1995 case 16:
1996 break;
1997 case 20:
1998 val_len |= RT5645_I2S_DL_20;
1999 break;
2000 case 24:
2001 val_len |= RT5645_I2S_DL_24;
2002 break;
2003 case 8:
2004 val_len |= RT5645_I2S_DL_8;
2005 break;
2006 default:
2007 return -EINVAL;
2008 }
2009
2010 switch (dai->id) {
2011 case RT5645_AIF1:
2012 mask_clk = RT5645_I2S_BCLK_MS1_MASK | RT5645_I2S_PD1_MASK;
2013 val_clk = bclk_ms << RT5645_I2S_BCLK_MS1_SFT |
2014 pre_div << RT5645_I2S_PD1_SFT;
2015 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2016 RT5645_I2S_DL_MASK, val_len);
2017 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2018 break;
2019 case RT5645_AIF2:
2020 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2021 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2022 pre_div << RT5645_I2S_PD2_SFT;
2023 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
2024 RT5645_I2S_DL_MASK, val_len);
2025 snd_soc_update_bits(codec, RT5645_ADDA_CLK1, mask_clk, val_clk);
2026 break;
2027 default:
2028 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2029 return -EINVAL;
2030 }
2031
2032 return 0;
2033}
2034
2035static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2036{
2037 struct snd_soc_codec *codec = dai->codec;
2038 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2039 unsigned int reg_val = 0;
2040
2041 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2042 case SND_SOC_DAIFMT_CBM_CFM:
2043 rt5645->master[dai->id] = 1;
2044 break;
2045 case SND_SOC_DAIFMT_CBS_CFS:
2046 reg_val |= RT5645_I2S_MS_S;
2047 rt5645->master[dai->id] = 0;
2048 break;
2049 default:
2050 return -EINVAL;
2051 }
2052
2053 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2054 case SND_SOC_DAIFMT_NB_NF:
2055 break;
2056 case SND_SOC_DAIFMT_IB_NF:
2057 reg_val |= RT5645_I2S_BP_INV;
2058 break;
2059 default:
2060 return -EINVAL;
2061 }
2062
2063 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2064 case SND_SOC_DAIFMT_I2S:
2065 break;
2066 case SND_SOC_DAIFMT_LEFT_J:
2067 reg_val |= RT5645_I2S_DF_LEFT;
2068 break;
2069 case SND_SOC_DAIFMT_DSP_A:
2070 reg_val |= RT5645_I2S_DF_PCM_A;
2071 break;
2072 case SND_SOC_DAIFMT_DSP_B:
2073 reg_val |= RT5645_I2S_DF_PCM_B;
2074 break;
2075 default:
2076 return -EINVAL;
2077 }
2078 switch (dai->id) {
2079 case RT5645_AIF1:
2080 snd_soc_update_bits(codec, RT5645_I2S1_SDP,
2081 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2082 RT5645_I2S_DF_MASK, reg_val);
2083 break;
Axel Lin8c325702014-05-17 19:17:32 +08002084 case RT5645_AIF2:
2085 snd_soc_update_bits(codec, RT5645_I2S2_SDP,
Oder Chiou1319b2f2014-04-28 19:59:10 +08002086 RT5645_I2S_MS_MASK | RT5645_I2S_BP_MASK |
2087 RT5645_I2S_DF_MASK, reg_val);
2088 break;
2089 default:
2090 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2091 return -EINVAL;
2092 }
2093 return 0;
2094}
2095
2096static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2097 int clk_id, unsigned int freq, int dir)
2098{
2099 struct snd_soc_codec *codec = dai->codec;
2100 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2101 unsigned int reg_val = 0;
2102
2103 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2104 return 0;
2105
2106 switch (clk_id) {
2107 case RT5645_SCLK_S_MCLK:
2108 reg_val |= RT5645_SCLK_SRC_MCLK;
2109 break;
2110 case RT5645_SCLK_S_PLL1:
2111 reg_val |= RT5645_SCLK_SRC_PLL1;
2112 break;
2113 case RT5645_SCLK_S_RCCLK:
2114 reg_val |= RT5645_SCLK_SRC_RCCLK;
2115 break;
2116 default:
2117 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
2118 return -EINVAL;
2119 }
2120 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2121 RT5645_SCLK_SRC_MASK, reg_val);
2122 rt5645->sysclk = freq;
2123 rt5645->sysclk_src = clk_id;
2124
2125 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2126
2127 return 0;
2128}
2129
Oder Chiou1319b2f2014-04-28 19:59:10 +08002130static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2131 unsigned int freq_in, unsigned int freq_out)
2132{
2133 struct snd_soc_codec *codec = dai->codec;
2134 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
Oder Chiou71c7a2d2014-05-20 15:01:54 +08002135 struct rl6231_pll_code pll_code;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002136 int ret;
2137
2138 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2139 freq_out == rt5645->pll_out)
2140 return 0;
2141
2142 if (!freq_in || !freq_out) {
2143 dev_dbg(codec->dev, "PLL disabled\n");
2144
2145 rt5645->pll_in = 0;
2146 rt5645->pll_out = 0;
2147 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2148 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2149 return 0;
2150 }
2151
2152 switch (source) {
2153 case RT5645_PLL1_S_MCLK:
2154 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2155 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2156 break;
2157 case RT5645_PLL1_S_BCLK1:
2158 case RT5645_PLL1_S_BCLK2:
2159 switch (dai->id) {
2160 case RT5645_AIF1:
2161 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2162 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2163 break;
2164 case RT5645_AIF2:
2165 snd_soc_update_bits(codec, RT5645_GLB_CLK,
2166 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2167 break;
2168 default:
2169 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
2170 return -EINVAL;
2171 }
2172 break;
2173 default:
2174 dev_err(codec->dev, "Unknown PLL source %d\n", source);
2175 return -EINVAL;
2176 }
2177
Oder Chiou71c7a2d2014-05-20 15:01:54 +08002178 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002179 if (ret < 0) {
2180 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
2181 return ret;
2182 }
2183
2184 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
2185 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2186 pll_code.n_code, pll_code.k_code);
2187
2188 snd_soc_write(codec, RT5645_PLL_CTRL1,
2189 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2190 snd_soc_write(codec, RT5645_PLL_CTRL2,
2191 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2192 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2193
2194 rt5645->pll_in = freq_in;
2195 rt5645->pll_out = freq_out;
2196 rt5645->pll_src = source;
2197
2198 return 0;
2199}
2200
2201static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2202 unsigned int rx_mask, int slots, int slot_width)
2203{
2204 struct snd_soc_codec *codec = dai->codec;
2205 unsigned int val = 0;
2206
Bard Liao850577d2014-11-13 09:55:22 +08002207 if (rx_mask || tx_mask) {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002208 val |= (1 << 14);
Bard Liao850577d2014-11-13 09:55:22 +08002209 snd_soc_update_bits(codec, RT5645_BASS_BACK,
2210 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
2211 }
Oder Chiou1319b2f2014-04-28 19:59:10 +08002212
2213 switch (slots) {
2214 case 4:
2215 val |= (1 << 12);
2216 break;
2217 case 6:
2218 val |= (2 << 12);
2219 break;
2220 case 8:
2221 val |= (3 << 12);
2222 break;
2223 case 2:
2224 default:
2225 break;
2226 }
2227
2228 switch (slot_width) {
2229 case 20:
2230 val |= (1 << 10);
2231 break;
2232 case 24:
2233 val |= (2 << 10);
2234 break;
2235 case 32:
2236 val |= (3 << 10);
2237 break;
2238 case 16:
2239 default:
2240 break;
2241 }
2242
2243 snd_soc_update_bits(codec, RT5645_TDM_CTRL_1, 0x7c00, val);
2244
2245 return 0;
2246}
2247
2248static int rt5645_set_bias_level(struct snd_soc_codec *codec,
2249 enum snd_soc_bias_level level)
2250{
2251 switch (level) {
Bard Liao0b2e4952014-11-04 13:15:10 +08002252 case SND_SOC_BIAS_PREPARE:
2253 if (SND_SOC_BIAS_STANDBY == codec->dapm.bias_level) {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002254 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2255 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2256 RT5645_PWR_BG | RT5645_PWR_VREF2,
2257 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2258 RT5645_PWR_BG | RT5645_PWR_VREF2);
2259 mdelay(10);
2260 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2261 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2262 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2263 snd_soc_update_bits(codec, RT5645_GEN_CTRL1,
2264 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
2265 }
2266 break;
2267
Bard Liao0b2e4952014-11-04 13:15:10 +08002268 case SND_SOC_BIAS_STANDBY:
2269 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2270 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2271 RT5645_PWR_BG | RT5645_PWR_VREF2,
2272 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2273 RT5645_PWR_BG | RT5645_PWR_VREF2);
2274 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2275 RT5645_PWR_FV1 | RT5645_PWR_FV2,
2276 RT5645_PWR_FV1 | RT5645_PWR_FV2);
2277 break;
2278
Oder Chiou1319b2f2014-04-28 19:59:10 +08002279 case SND_SOC_BIAS_OFF:
2280 snd_soc_write(codec, RT5645_DEPOP_M2, 0x1100);
2281 snd_soc_write(codec, RT5645_GEN_CTRL1, 0x0128);
Bard Liao0b2e4952014-11-04 13:15:10 +08002282 snd_soc_update_bits(codec, RT5645_PWR_ANLG1,
2283 RT5645_PWR_VREF1 | RT5645_PWR_MB |
2284 RT5645_PWR_BG | RT5645_PWR_VREF2 |
2285 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002286 break;
2287
2288 default:
2289 break;
2290 }
2291 codec->dapm.bias_level = level;
2292
2293 return 0;
2294}
2295
Bard Liao471f2082014-11-14 14:25:37 +08002296static int rt5645_jack_detect(struct snd_soc_codec *codec)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002297{
2298 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2299 int gpio_state, jack_type = 0;
2300 unsigned int val;
2301
Bard Liao75945892014-12-09 10:14:45 +08002302 if (!gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2303 dev_err(codec->dev, "invalid gpio\n");
2304 return -EINVAL;
2305 }
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002306 gpio_state = gpio_get_value(rt5645->pdata.hp_det_gpio);
2307
2308 dev_dbg(codec->dev, "gpio = %d(%d)\n", rt5645->pdata.hp_det_gpio,
2309 gpio_state);
2310
2311 if ((rt5645->pdata.gpio_hp_det_active_high && gpio_state) ||
2312 (!rt5645->pdata.gpio_hp_det_active_high && !gpio_state)) {
2313 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias1");
2314 snd_soc_dapm_force_enable_pin(&codec->dapm, "micbias2");
2315 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2316 snd_soc_dapm_force_enable_pin(&codec->dapm, "Mic Det Power");
2317 snd_soc_dapm_sync(&codec->dapm);
2318
2319 snd_soc_write(codec, RT5645_IN1_CTRL1, 0x0006);
2320 snd_soc_write(codec, RT5645_JD_CTRL3, 0x00b0);
2321
2322 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2323 RT5645_CBJ_MN_JD, 0);
2324 snd_soc_update_bits(codec, RT5645_IN1_CTRL2,
2325 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
2326
2327 msleep(400);
2328 val = snd_soc_read(codec, RT5645_IN1_CTRL3) & 0x7;
2329 dev_dbg(codec->dev, "val = %d\n", val);
2330
2331 if (val == 1 || val == 2)
2332 jack_type = SND_JACK_HEADSET;
2333 else
2334 jack_type = SND_JACK_HEADPHONE;
2335
2336 snd_soc_dapm_disable_pin(&codec->dapm, "micbias1");
2337 snd_soc_dapm_disable_pin(&codec->dapm, "micbias2");
Bard Liao2d4e2d02014-11-18 16:50:18 +08002338 if (rt5645->pdata.jd_mode == 0)
2339 snd_soc_dapm_disable_pin(&codec->dapm, "LDO2");
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002340 snd_soc_dapm_disable_pin(&codec->dapm, "Mic Det Power");
2341 snd_soc_dapm_sync(&codec->dapm);
2342 }
2343
Bard Liao471f2082014-11-14 14:25:37 +08002344 snd_soc_jack_report(rt5645->hp_jack, jack_type, SND_JACK_HEADPHONE);
2345 snd_soc_jack_report(rt5645->mic_jack, jack_type, SND_JACK_MICROPHONE);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002346 return 0;
2347}
2348
2349int rt5645_set_jack_detect(struct snd_soc_codec *codec,
Bard Liao471f2082014-11-14 14:25:37 +08002350 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack)
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002351{
2352 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2353
Bard Liao471f2082014-11-14 14:25:37 +08002354 rt5645->hp_jack = hp_jack;
2355 rt5645->mic_jack = mic_jack;
2356 rt5645_jack_detect(codec);
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002357
2358 return 0;
2359}
2360EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
2361
Oder Chioucd6e82b2014-10-07 10:25:37 +08002362static void rt5645_jack_detect_work(struct work_struct *work)
2363{
2364 struct rt5645_priv *rt5645 =
2365 container_of(work, struct rt5645_priv, jack_detect_work.work);
2366
Bard Liao471f2082014-11-14 14:25:37 +08002367 rt5645_jack_detect(rt5645->codec);
Oder Chioucd6e82b2014-10-07 10:25:37 +08002368}
2369
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002370static irqreturn_t rt5645_irq(int irq, void *data)
2371{
2372 struct rt5645_priv *rt5645 = data;
2373
Oder Chioucd6e82b2014-10-07 10:25:37 +08002374 queue_delayed_work(system_power_efficient_wq,
2375 &rt5645->jack_detect_work, msecs_to_jiffies(250));
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002376
2377 return IRQ_HANDLED;
2378}
2379
Oder Chiou1319b2f2014-04-28 19:59:10 +08002380static int rt5645_probe(struct snd_soc_codec *codec)
2381{
2382 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2383
2384 rt5645->codec = codec;
2385
Bard Liao5c4ca992015-01-21 20:50:15 +08002386 switch (rt5645->codec_type) {
2387 case CODEC_TYPE_RT5645:
2388 snd_soc_dapm_add_routes(&codec->dapm,
2389 rt5645_specific_dapm_routes,
2390 ARRAY_SIZE(rt5645_specific_dapm_routes));
2391 break;
2392 case CODEC_TYPE_RT5650:
2393 snd_soc_dapm_new_controls(&codec->dapm,
2394 rt5650_specific_dapm_widgets,
2395 ARRAY_SIZE(rt5650_specific_dapm_widgets));
2396 snd_soc_dapm_add_routes(&codec->dapm,
2397 rt5650_specific_dapm_routes,
2398 ARRAY_SIZE(rt5650_specific_dapm_routes));
2399 break;
2400 }
2401
Oder Chiou1319b2f2014-04-28 19:59:10 +08002402 rt5645_set_bias_level(codec, SND_SOC_BIAS_OFF);
2403
2404 snd_soc_update_bits(codec, RT5645_CHARGE_PUMP, 0x0300, 0x0200);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002405
Bard Liaobb656ad2014-11-05 15:02:08 +08002406 /* for JD function */
2407 if (rt5645->pdata.en_jd_func) {
2408 snd_soc_dapm_force_enable_pin(&codec->dapm, "JD Power");
2409 snd_soc_dapm_force_enable_pin(&codec->dapm, "LDO2");
2410 snd_soc_dapm_sync(&codec->dapm);
2411 }
2412
Oder Chiou1319b2f2014-04-28 19:59:10 +08002413 return 0;
2414}
2415
2416static int rt5645_remove(struct snd_soc_codec *codec)
2417{
2418 rt5645_reset(codec);
2419 return 0;
2420}
2421
2422#ifdef CONFIG_PM
2423static int rt5645_suspend(struct snd_soc_codec *codec)
2424{
2425 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2426
2427 regcache_cache_only(rt5645->regmap, true);
2428 regcache_mark_dirty(rt5645->regmap);
2429
2430 return 0;
2431}
2432
2433static int rt5645_resume(struct snd_soc_codec *codec)
2434{
2435 struct rt5645_priv *rt5645 = snd_soc_codec_get_drvdata(codec);
2436
2437 regcache_cache_only(rt5645->regmap, false);
Oder Chiou0f776ef2014-05-08 14:47:37 +08002438 regcache_sync(rt5645->regmap);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002439
2440 return 0;
2441}
2442#else
2443#define rt5645_suspend NULL
2444#define rt5645_resume NULL
2445#endif
2446
2447#define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
2448#define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
2449 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
2450
Oder Chiou9e22f782014-05-08 14:47:35 +08002451static struct snd_soc_dai_ops rt5645_aif_dai_ops = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002452 .hw_params = rt5645_hw_params,
2453 .set_fmt = rt5645_set_dai_fmt,
2454 .set_sysclk = rt5645_set_dai_sysclk,
2455 .set_tdm_slot = rt5645_set_tdm_slot,
2456 .set_pll = rt5645_set_dai_pll,
2457};
2458
Oder Chiou9e22f782014-05-08 14:47:35 +08002459static struct snd_soc_dai_driver rt5645_dai[] = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002460 {
2461 .name = "rt5645-aif1",
2462 .id = RT5645_AIF1,
2463 .playback = {
2464 .stream_name = "AIF1 Playback",
2465 .channels_min = 1,
2466 .channels_max = 2,
2467 .rates = RT5645_STEREO_RATES,
2468 .formats = RT5645_FORMATS,
2469 },
2470 .capture = {
2471 .stream_name = "AIF1 Capture",
2472 .channels_min = 1,
2473 .channels_max = 2,
2474 .rates = RT5645_STEREO_RATES,
2475 .formats = RT5645_FORMATS,
2476 },
2477 .ops = &rt5645_aif_dai_ops,
2478 },
2479 {
2480 .name = "rt5645-aif2",
2481 .id = RT5645_AIF2,
2482 .playback = {
2483 .stream_name = "AIF2 Playback",
2484 .channels_min = 1,
2485 .channels_max = 2,
2486 .rates = RT5645_STEREO_RATES,
2487 .formats = RT5645_FORMATS,
2488 },
2489 .capture = {
2490 .stream_name = "AIF2 Capture",
2491 .channels_min = 1,
2492 .channels_max = 2,
2493 .rates = RT5645_STEREO_RATES,
2494 .formats = RT5645_FORMATS,
2495 },
2496 .ops = &rt5645_aif_dai_ops,
2497 },
2498};
2499
2500static struct snd_soc_codec_driver soc_codec_dev_rt5645 = {
2501 .probe = rt5645_probe,
2502 .remove = rt5645_remove,
2503 .suspend = rt5645_suspend,
2504 .resume = rt5645_resume,
2505 .set_bias_level = rt5645_set_bias_level,
2506 .idle_bias_off = true,
2507 .controls = rt5645_snd_controls,
2508 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
2509 .dapm_widgets = rt5645_dapm_widgets,
2510 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
2511 .dapm_routes = rt5645_dapm_routes,
2512 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
2513};
2514
2515static const struct regmap_config rt5645_regmap = {
2516 .reg_bits = 8,
2517 .val_bits = 16,
2518
2519 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
2520 RT5645_PR_SPACING),
2521 .volatile_reg = rt5645_volatile_register,
2522 .readable_reg = rt5645_readable_register,
2523
2524 .cache_type = REGCACHE_RBTREE,
2525 .reg_defaults = rt5645_reg,
2526 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
2527 .ranges = rt5645_ranges,
2528 .num_ranges = ARRAY_SIZE(rt5645_ranges),
2529};
2530
2531static const struct i2c_device_id rt5645_i2c_id[] = {
2532 { "rt5645", 0 },
Bard Liao5c4ca992015-01-21 20:50:15 +08002533 { "rt5650", 0 },
Oder Chiou1319b2f2014-04-28 19:59:10 +08002534 { }
2535};
2536MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
2537
2538static int rt5645_i2c_probe(struct i2c_client *i2c,
2539 const struct i2c_device_id *id)
2540{
2541 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
2542 struct rt5645_priv *rt5645;
2543 int ret;
2544 unsigned int val;
2545
2546 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
2547 GFP_KERNEL);
2548 if (rt5645 == NULL)
2549 return -ENOMEM;
2550
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002551 rt5645->i2c = i2c;
Oder Chiou1319b2f2014-04-28 19:59:10 +08002552 i2c_set_clientdata(i2c, rt5645);
2553
2554 if (pdata)
2555 rt5645->pdata = *pdata;
2556
2557 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
2558 if (IS_ERR(rt5645->regmap)) {
2559 ret = PTR_ERR(rt5645->regmap);
2560 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2561 ret);
2562 return ret;
2563 }
2564
2565 regmap_read(rt5645->regmap, RT5645_VENDOR_ID2, &val);
Bard Liao5c4ca992015-01-21 20:50:15 +08002566
2567 switch (val) {
2568 case RT5645_DEVICE_ID:
2569 rt5645->codec_type = CODEC_TYPE_RT5645;
2570 break;
2571 case RT5650_DEVICE_ID:
2572 rt5645->codec_type = CODEC_TYPE_RT5650;
2573 break;
2574 default:
Oder Chiou1319b2f2014-04-28 19:59:10 +08002575 dev_err(&i2c->dev,
Bard Liao5c4ca992015-01-21 20:50:15 +08002576 "Device with ID register %x is not rt5645 or rt5650\n",
2577 val);
Oder Chiou1319b2f2014-04-28 19:59:10 +08002578 return -ENODEV;
2579 }
2580
2581 regmap_write(rt5645->regmap, RT5645_RESET, 0);
2582
2583 ret = regmap_register_patch(rt5645->regmap, init_list,
2584 ARRAY_SIZE(init_list));
2585 if (ret != 0)
2586 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
2587
Bard Liao5c4ca992015-01-21 20:50:15 +08002588 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
2589 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
2590 ARRAY_SIZE(rt5650_init_list));
2591 if (ret != 0)
2592 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
2593 ret);
2594 }
2595
Oder Chiou1319b2f2014-04-28 19:59:10 +08002596 if (rt5645->pdata.in2_diff)
2597 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
2598 RT5645_IN_DF2, RT5645_IN_DF2);
2599
2600 if (rt5645->pdata.dmic_en) {
2601 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2602 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
2603
2604 switch (rt5645->pdata.dmic1_data_pin) {
2605 case RT5645_DMIC_DATA_IN2N:
2606 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2607 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
2608 break;
2609
2610 case RT5645_DMIC_DATA_GPIO5:
2611 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2612 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
2613 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2614 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
2615 break;
2616
2617 case RT5645_DMIC_DATA_GPIO11:
2618 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2619 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
2620 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2621 RT5645_GP11_PIN_MASK,
2622 RT5645_GP11_PIN_DMIC1_SDA);
2623 break;
2624
2625 default:
2626 break;
2627 }
2628
2629 switch (rt5645->pdata.dmic2_data_pin) {
2630 case RT5645_DMIC_DATA_IN2P:
2631 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2632 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
2633 break;
2634
2635 case RT5645_DMIC_DATA_GPIO6:
2636 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2637 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
2638 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2639 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
2640 break;
2641
2642 case RT5645_DMIC_DATA_GPIO10:
2643 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2644 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
2645 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2646 RT5645_GP10_PIN_MASK,
2647 RT5645_GP10_PIN_DMIC2_SDA);
2648 break;
2649
2650 case RT5645_DMIC_DATA_GPIO12:
2651 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
2652 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
2653 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2654 RT5645_GP12_PIN_MASK,
2655 RT5645_GP12_PIN_DMIC2_SDA);
2656 break;
2657
2658 default:
2659 break;
2660 }
2661
2662 }
2663
Bard Liaobb656ad2014-11-05 15:02:08 +08002664 if (rt5645->pdata.en_jd_func) {
2665 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2666 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU,
2667 RT5645_IRQ_CLK_GATE_CTRL | RT5645_MICINDET_MANU);
2668 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
2669 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
2670 regmap_update_bits(rt5645->regmap, RT5645_JD_CTRL3,
2671 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL,
2672 RT5645_JD_CBJ_EN | RT5645_JD_CBJ_POL);
2673 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2674 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
2675 }
2676
Bard Liao2d4e2d02014-11-18 16:50:18 +08002677 if (rt5645->pdata.jd_mode) {
2678 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
2679 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
2680 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
2681 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
2682 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
2683 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
2684 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
2685 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
2686 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
2687 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
2688 switch (rt5645->pdata.jd_mode) {
2689 case 1:
2690 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2691 RT5645_JD1_MODE_MASK,
2692 RT5645_JD1_MODE_0);
2693 break;
2694 case 2:
2695 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2696 RT5645_JD1_MODE_MASK,
2697 RT5645_JD1_MODE_1);
2698 break;
2699 case 3:
2700 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
2701 RT5645_JD1_MODE_MASK,
2702 RT5645_JD1_MODE_2);
2703 break;
2704 default:
2705 break;
2706 }
2707 }
2708
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002709 if (rt5645->i2c->irq) {
2710 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
2711 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2712 | IRQF_ONESHOT, "rt5645", rt5645);
2713 if (ret)
2714 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
2715 }
2716
2717 if (gpio_is_valid(rt5645->pdata.hp_det_gpio)) {
2718 ret = gpio_request(rt5645->pdata.hp_det_gpio, "rt5645");
2719 if (ret)
2720 dev_err(&i2c->dev, "Fail gpio_request hp_det_gpio\n");
2721
2722 ret = gpio_direction_input(rt5645->pdata.hp_det_gpio);
2723 if (ret)
2724 dev_err(&i2c->dev, "Fail gpio_direction hp_det_gpio\n");
2725 }
2726
Oder Chioucd6e82b2014-10-07 10:25:37 +08002727 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
2728
Axel Lindd56eba2014-06-10 11:36:41 +08002729 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5645,
2730 rt5645_dai, ARRAY_SIZE(rt5645_dai));
Oder Chiou1319b2f2014-04-28 19:59:10 +08002731}
2732
2733static int rt5645_i2c_remove(struct i2c_client *i2c)
2734{
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002735 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
2736
2737 if (i2c->irq)
2738 free_irq(i2c->irq, rt5645);
2739
Oder Chioucd6e82b2014-10-07 10:25:37 +08002740 cancel_delayed_work_sync(&rt5645->jack_detect_work);
2741
Oder Chiouf3fa1bb2014-09-19 19:15:45 +08002742 if (gpio_is_valid(rt5645->pdata.hp_det_gpio))
2743 gpio_free(rt5645->pdata.hp_det_gpio);
2744
Oder Chiou1319b2f2014-04-28 19:59:10 +08002745 snd_soc_unregister_codec(&i2c->dev);
2746
2747 return 0;
2748}
2749
Oder Chiou9e22f782014-05-08 14:47:35 +08002750static struct i2c_driver rt5645_i2c_driver = {
Oder Chiou1319b2f2014-04-28 19:59:10 +08002751 .driver = {
2752 .name = "rt5645",
2753 .owner = THIS_MODULE,
2754 },
2755 .probe = rt5645_i2c_probe,
2756 .remove = rt5645_i2c_remove,
2757 .id_table = rt5645_i2c_id,
2758};
2759module_i2c_driver(rt5645_i2c_driver);
2760
2761MODULE_DESCRIPTION("ASoC RT5645 driver");
2762MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
2763MODULE_LICENSE("GPL v2");