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Nicolas Ferredc78baa2009-07-03 19:24:33 +02001/*
2 * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems)
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 *
Nicolas Ferre9102d872012-06-12 10:44:55 +020012 * This supports the Atmel AHB DMA Controller found in several Atmel SoCs.
13 * The only Atmel DMA Controller that is not covered by this driver is the one
14 * found on AT91SAM9263.
Nicolas Ferredc78baa2009-07-03 19:24:33 +020015 */
16
Ludovic Desroches62971b22013-06-13 10:39:39 +020017#include <dt-bindings/dma/at91.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020018#include <linux/clk.h>
19#include <linux/dmaengine.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/interrupt.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090025#include <linux/slab.h>
Nicolas Ferrec5115952011-10-17 14:56:41 +020026#include <linux/of.h>
27#include <linux/of_device.h>
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +000028#include <linux/of_dma.h>
Nicolas Ferredc78baa2009-07-03 19:24:33 +020029
30#include "at_hdmac_regs.h"
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000031#include "dmaengine.h"
Nicolas Ferredc78baa2009-07-03 19:24:33 +020032
33/*
34 * Glossary
35 * --------
36 *
37 * at_hdmac : Name of the ATmel AHB DMA Controller
38 * at_dma_ / atdma : ATmel DMA controller entity related
39 * atc_ / atchan : ATmel DMA Channel entity related
40 */
41
42#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
Nicolas Ferreae14d4b2011-04-30 16:57:49 +020043#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
44 |ATC_DIF(AT_DMA_MEM_IF))
Nicolas Ferredc78baa2009-07-03 19:24:33 +020045
46/*
47 * Initial number of descriptors to allocate for each channel. This could
48 * be increased during dma usage.
49 */
50static unsigned int init_nr_desc_per_channel = 64;
51module_param(init_nr_desc_per_channel, uint, 0644);
52MODULE_PARM_DESC(init_nr_desc_per_channel,
53 "initial descriptors per channel (default: 64)");
54
55
56/* prototypes */
57static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx);
Elen Songd48de6f2013-05-10 11:01:46 +080058static void atc_issue_pending(struct dma_chan *chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +020059
60
61/*----------------------------------------------------------------------*/
62
63static struct at_desc *atc_first_active(struct at_dma_chan *atchan)
64{
65 return list_first_entry(&atchan->active_list,
66 struct at_desc, desc_node);
67}
68
69static struct at_desc *atc_first_queued(struct at_dma_chan *atchan)
70{
71 return list_first_entry(&atchan->queue,
72 struct at_desc, desc_node);
73}
74
75/**
Uwe Kleine-König421f91d2010-06-11 12:17:00 +020076 * atc_alloc_descriptor - allocate and return an initialized descriptor
Nicolas Ferredc78baa2009-07-03 19:24:33 +020077 * @chan: the channel to allocate descriptors for
78 * @gfp_flags: GFP allocation flags
79 *
80 * Note: The ack-bit is positioned in the descriptor flag at creation time
81 * to make initial allocation more convenient. This bit will be cleared
82 * and control will be given to client at usage time (during
83 * preparation functions).
84 */
85static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan,
86 gfp_t gfp_flags)
87{
88 struct at_desc *desc = NULL;
89 struct at_dma *atdma = to_at_dma(chan->device);
90 dma_addr_t phys;
91
92 desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys);
93 if (desc) {
94 memset(desc, 0, sizeof(struct at_desc));
Dan Williams285a3c72009-09-08 17:53:03 -070095 INIT_LIST_HEAD(&desc->tx_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +020096 dma_async_tx_descriptor_init(&desc->txd, chan);
97 /* txd.flags will be overwritten in prep functions */
98 desc->txd.flags = DMA_CTRL_ACK;
99 desc->txd.tx_submit = atc_tx_submit;
100 desc->txd.phys = phys;
101 }
102
103 return desc;
104}
105
106/**
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200107 * atc_desc_get - get an unused descriptor from free_list
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200108 * @atchan: channel we want a new descriptor for
109 */
110static struct at_desc *atc_desc_get(struct at_dma_chan *atchan)
111{
112 struct at_desc *desc, *_desc;
113 struct at_desc *ret = NULL;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000114 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200115 unsigned int i = 0;
116 LIST_HEAD(tmp_list);
117
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000118 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200119 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
120 i++;
121 if (async_tx_test_ack(&desc->txd)) {
122 list_del(&desc->desc_node);
123 ret = desc;
124 break;
125 }
126 dev_dbg(chan2dev(&atchan->chan_common),
127 "desc %p not ACKed\n", desc);
128 }
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000129 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200130 dev_vdbg(chan2dev(&atchan->chan_common),
131 "scanned %u descriptors on freelist\n", i);
132
133 /* no more descriptor available in initial pool: create one more */
134 if (!ret) {
135 ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC);
136 if (ret) {
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000137 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200138 atchan->descs_allocated++;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000139 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200140 } else {
141 dev_err(chan2dev(&atchan->chan_common),
142 "not enough descriptors available\n");
143 }
144 }
145
146 return ret;
147}
148
149/**
150 * atc_desc_put - move a descriptor, including any children, to the free list
151 * @atchan: channel we work on
152 * @desc: descriptor, at the head of a chain, to move to free list
153 */
154static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc)
155{
156 if (desc) {
157 struct at_desc *child;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000158 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200159
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000160 spin_lock_irqsave(&atchan->lock, flags);
Dan Williams285a3c72009-09-08 17:53:03 -0700161 list_for_each_entry(child, &desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200162 dev_vdbg(chan2dev(&atchan->chan_common),
163 "moving child desc %p to freelist\n",
164 child);
Dan Williams285a3c72009-09-08 17:53:03 -0700165 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200166 dev_vdbg(chan2dev(&atchan->chan_common),
167 "moving desc %p to freelist\n", desc);
168 list_add(&desc->desc_node, &atchan->free_list);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000169 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200170 }
171}
172
173/**
Masanari Iidad73111c2012-08-04 23:37:53 +0900174 * atc_desc_chain - build chain adding a descriptor
175 * @first: address of first descriptor of the chain
176 * @prev: address of previous descriptor of the chain
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200177 * @desc: descriptor to queue
178 *
179 * Called from prep_* functions
180 */
181static void atc_desc_chain(struct at_desc **first, struct at_desc **prev,
182 struct at_desc *desc)
183{
184 if (!(*first)) {
185 *first = desc;
186 } else {
187 /* inform the HW lli about chaining */
188 (*prev)->lli.dscr = desc->txd.phys;
189 /* insert the link descriptor to the LD ring */
190 list_add_tail(&desc->desc_node,
191 &(*first)->tx_list);
192 }
193 *prev = desc;
194}
195
196/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200197 * atc_dostart - starts the DMA engine for real
198 * @atchan: the channel we want to start
199 * @first: first descriptor in the list we want to begin with
200 *
201 * Called with atchan->lock held and bh disabled
202 */
203static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first)
204{
205 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
206
207 /* ASSERT: channel is idle */
208 if (atc_chan_is_enabled(atchan)) {
209 dev_err(chan2dev(&atchan->chan_common),
210 "BUG: Attempted to start non-idle channel\n");
211 dev_err(chan2dev(&atchan->chan_common),
212 " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n",
213 channel_readl(atchan, SADDR),
214 channel_readl(atchan, DADDR),
215 channel_readl(atchan, CTRLA),
216 channel_readl(atchan, CTRLB),
217 channel_readl(atchan, DSCR));
218
219 /* The tasklet will hopefully advance the queue... */
220 return;
221 }
222
223 vdbg_dump_regs(atchan);
224
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200225 channel_writel(atchan, SADDR, 0);
226 channel_writel(atchan, DADDR, 0);
227 channel_writel(atchan, CTRLA, 0);
228 channel_writel(atchan, CTRLB, 0);
229 channel_writel(atchan, DSCR, first->txd.phys);
230 dma_writel(atdma, CHER, atchan->mask);
231
232 vdbg_dump_regs(atchan);
233}
234
Elen Songd48de6f2013-05-10 11:01:46 +0800235/*
236 * atc_get_current_descriptors -
237 * locate the descriptor which equal to physical address in DSCR
238 * @atchan: the channel we want to start
239 * @dscr_addr: physical descriptor address in DSCR
240 */
241static struct at_desc *atc_get_current_descriptors(struct at_dma_chan *atchan,
242 u32 dscr_addr)
243{
244 struct at_desc *desc, *_desc, *child, *desc_cur = NULL;
245
246 list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) {
247 if (desc->lli.dscr == dscr_addr) {
248 desc_cur = desc;
249 break;
250 }
251
252 list_for_each_entry(child, &desc->tx_list, desc_node) {
253 if (child->lli.dscr == dscr_addr) {
254 desc_cur = child;
255 break;
256 }
257 }
258 }
259
260 return desc_cur;
261}
262
263/*
264 * atc_get_bytes_left -
265 * Get the number of bytes residue in dma buffer,
266 * @chan: the channel we want to start
267 */
268static int atc_get_bytes_left(struct dma_chan *chan)
269{
270 struct at_dma_chan *atchan = to_at_dma_chan(chan);
271 struct at_dma *atdma = to_at_dma(chan->device);
272 int chan_id = atchan->chan_common.chan_id;
273 struct at_desc *desc_first = atc_first_active(atchan);
274 struct at_desc *desc_cur;
275 int ret = 0, count = 0;
276
277 /*
278 * Initialize necessary values in the first time.
279 * remain_desc record remain desc length.
280 */
281 if (atchan->remain_desc == 0)
282 /* First descriptor embedds the transaction length */
283 atchan->remain_desc = desc_first->len;
284
285 /*
286 * This happens when current descriptor transfer complete.
287 * The residual buffer size should reduce current descriptor length.
288 */
289 if (unlikely(test_bit(ATC_IS_BTC, &atchan->status))) {
290 clear_bit(ATC_IS_BTC, &atchan->status);
291 desc_cur = atc_get_current_descriptors(atchan,
292 channel_readl(atchan, DSCR));
293 if (!desc_cur) {
294 ret = -EINVAL;
295 goto out;
296 }
297 atchan->remain_desc -= (desc_cur->lli.ctrla & ATC_BTSIZE_MAX)
298 << (desc_first->tx_width);
299 if (atchan->remain_desc < 0) {
300 ret = -EINVAL;
301 goto out;
Nicolas Ferrec3dbc602013-06-07 17:26:14 +0200302 } else {
Elen Songd48de6f2013-05-10 11:01:46 +0800303 ret = atchan->remain_desc;
Nicolas Ferrec3dbc602013-06-07 17:26:14 +0200304 }
Elen Songd48de6f2013-05-10 11:01:46 +0800305 } else {
306 /*
307 * Get residual bytes when current
308 * descriptor transfer in progress.
309 */
310 count = (channel_readl(atchan, CTRLA) & ATC_BTSIZE_MAX)
311 << (desc_first->tx_width);
312 ret = atchan->remain_desc - count;
313 }
314 /*
315 * Check fifo empty.
316 */
317 if (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id)))
318 atc_issue_pending(chan);
319
320out:
321 return ret;
322}
323
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200324/**
325 * atc_chain_complete - finish work for one transaction chain
326 * @atchan: channel we work on
327 * @desc: descriptor at the head of the chain we want do complete
328 *
329 * Called with atchan->lock held and bh disabled */
330static void
331atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc)
332{
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200333 struct dma_async_tx_descriptor *txd = &desc->txd;
334
335 dev_vdbg(chan2dev(&atchan->chan_common),
336 "descriptor %u complete\n", txd->cookie);
337
Vinod Kould4116052012-05-11 11:48:21 +0530338 /* mark the descriptor as complete for non cyclic cases only */
339 if (!atc_chan_is_cyclic(atchan))
340 dma_cookie_complete(txd);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200341
342 /* move children to free_list */
Dan Williams285a3c72009-09-08 17:53:03 -0700343 list_splice_init(&desc->tx_list, &atchan->free_list);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200344 /* move myself to free_list */
345 list_move(&desc->desc_node, &atchan->free_list);
346
Dan Williamsd38a8c62013-10-18 19:35:23 +0200347 dma_descriptor_unmap(txd);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200348 /* for cyclic transfers,
349 * no need to replay callback function while stopping */
Nicolas Ferre3c477482011-07-25 21:09:23 +0000350 if (!atc_chan_is_cyclic(atchan)) {
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200351 dma_async_tx_callback callback = txd->callback;
352 void *param = txd->callback_param;
353
354 /*
355 * The API requires that no submissions are done from a
356 * callback, so we don't need to drop the lock here
357 */
358 if (callback)
359 callback(param);
360 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200361
362 dma_run_dependencies(txd);
363}
364
365/**
366 * atc_complete_all - finish work for all transactions
367 * @atchan: channel to complete transactions for
368 *
369 * Eventually submit queued descriptors if any
370 *
371 * Assume channel is idle while calling this function
372 * Called with atchan->lock held and bh disabled
373 */
374static void atc_complete_all(struct at_dma_chan *atchan)
375{
376 struct at_desc *desc, *_desc;
377 LIST_HEAD(list);
378
379 dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n");
380
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200381 /*
382 * Submit queued descriptors ASAP, i.e. before we go through
383 * the completed ones.
384 */
385 if (!list_empty(&atchan->queue))
386 atc_dostart(atchan, atc_first_queued(atchan));
387 /* empty active_list now it is completed */
388 list_splice_init(&atchan->active_list, &list);
389 /* empty queue list by moving descriptors (if any) to active_list */
390 list_splice_init(&atchan->queue, &atchan->active_list);
391
392 list_for_each_entry_safe(desc, _desc, &list, desc_node)
393 atc_chain_complete(atchan, desc);
394}
395
396/**
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200397 * atc_advance_work - at the end of a transaction, move forward
398 * @atchan: channel where the transaction ended
399 *
400 * Called with atchan->lock held and bh disabled
401 */
402static void atc_advance_work(struct at_dma_chan *atchan)
403{
404 dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n");
405
Ludovic Desrochesd202f052013-04-18 09:52:59 +0200406 if (atc_chan_is_enabled(atchan))
407 return;
408
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200409 if (list_empty(&atchan->active_list) ||
410 list_is_singular(&atchan->active_list)) {
411 atc_complete_all(atchan);
412 } else {
413 atc_chain_complete(atchan, atc_first_active(atchan));
414 /* advance work */
415 atc_dostart(atchan, atc_first_active(atchan));
416 }
417}
418
419
420/**
421 * atc_handle_error - handle errors reported by DMA controller
422 * @atchan: channel where error occurs
423 *
424 * Called with atchan->lock held and bh disabled
425 */
426static void atc_handle_error(struct at_dma_chan *atchan)
427{
428 struct at_desc *bad_desc;
429 struct at_desc *child;
430
431 /*
432 * The descriptor currently at the head of the active list is
433 * broked. Since we don't have any way to report errors, we'll
434 * just have to scream loudly and try to carry on.
435 */
436 bad_desc = atc_first_active(atchan);
437 list_del_init(&bad_desc->desc_node);
438
439 /* As we are stopped, take advantage to push queued descriptors
440 * in active_list */
441 list_splice_init(&atchan->queue, atchan->active_list.prev);
442
443 /* Try to restart the controller */
444 if (!list_empty(&atchan->active_list))
445 atc_dostart(atchan, atc_first_active(atchan));
446
447 /*
448 * KERN_CRITICAL may seem harsh, but since this only happens
449 * when someone submits a bad physical address in a
450 * descriptor, we should consider ourselves lucky that the
451 * controller flagged an error instead of scribbling over
452 * random memory locations.
453 */
454 dev_crit(chan2dev(&atchan->chan_common),
455 "Bad descriptor submitted for DMA!\n");
456 dev_crit(chan2dev(&atchan->chan_common),
457 " cookie: %d\n", bad_desc->txd.cookie);
458 atc_dump_lli(atchan, &bad_desc->lli);
Dan Williams285a3c72009-09-08 17:53:03 -0700459 list_for_each_entry(child, &bad_desc->tx_list, desc_node)
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200460 atc_dump_lli(atchan, &child->lli);
461
462 /* Pretend the descriptor completed successfully */
463 atc_chain_complete(atchan, bad_desc);
464}
465
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200466/**
467 * atc_handle_cyclic - at the end of a period, run callback function
468 * @atchan: channel used for cyclic operations
469 *
470 * Called with atchan->lock held and bh disabled
471 */
472static void atc_handle_cyclic(struct at_dma_chan *atchan)
473{
474 struct at_desc *first = atc_first_active(atchan);
475 struct dma_async_tx_descriptor *txd = &first->txd;
476 dma_async_tx_callback callback = txd->callback;
477 void *param = txd->callback_param;
478
479 dev_vdbg(chan2dev(&atchan->chan_common),
480 "new cyclic period llp 0x%08x\n",
481 channel_readl(atchan, DSCR));
482
483 if (callback)
484 callback(param);
485}
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200486
487/*-- IRQ & Tasklet ---------------------------------------------------*/
488
489static void atc_tasklet(unsigned long data)
490{
491 struct at_dma_chan *atchan = (struct at_dma_chan *)data;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000492 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200493
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000494 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200495 if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status))
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200496 atc_handle_error(atchan);
Nicolas Ferre3c477482011-07-25 21:09:23 +0000497 else if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200498 atc_handle_cyclic(atchan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200499 else
500 atc_advance_work(atchan);
501
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000502 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200503}
504
505static irqreturn_t at_dma_interrupt(int irq, void *dev_id)
506{
507 struct at_dma *atdma = (struct at_dma *)dev_id;
508 struct at_dma_chan *atchan;
509 int i;
510 u32 status, pending, imr;
511 int ret = IRQ_NONE;
512
513 do {
514 imr = dma_readl(atdma, EBCIMR);
515 status = dma_readl(atdma, EBCISR);
516 pending = status & imr;
517
518 if (!pending)
519 break;
520
521 dev_vdbg(atdma->dma_common.dev,
522 "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n",
523 status, imr, pending);
524
525 for (i = 0; i < atdma->dma_common.chancnt; i++) {
526 atchan = &atdma->chan[i];
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200527 if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200528 if (pending & AT_DMA_ERR(i)) {
529 /* Disable channel on AHB error */
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +0200530 dma_writel(atdma, CHDR,
531 AT_DMA_RES(i) | atchan->mask);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200532 /* Give information to tasklet */
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200533 set_bit(ATC_IS_ERROR, &atchan->status);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200534 }
Elen Songd48de6f2013-05-10 11:01:46 +0800535 if (pending & AT_DMA_BTC(i))
536 set_bit(ATC_IS_BTC, &atchan->status);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200537 tasklet_schedule(&atchan->tasklet);
538 ret = IRQ_HANDLED;
539 }
540 }
541
542 } while (pending);
543
544 return ret;
545}
546
547
548/*-- DMA Engine API --------------------------------------------------*/
549
550/**
551 * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine
552 * @desc: descriptor at the head of the transaction chain
553 *
554 * Queue chain if DMA engine is working already
555 *
556 * Cookie increment and adding to active_list or queue must be atomic
557 */
558static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx)
559{
560 struct at_desc *desc = txd_to_at_desc(tx);
561 struct at_dma_chan *atchan = to_at_dma_chan(tx->chan);
562 dma_cookie_t cookie;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000563 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200564
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000565 spin_lock_irqsave(&atchan->lock, flags);
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000566 cookie = dma_cookie_assign(tx);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200567
568 if (list_empty(&atchan->active_list)) {
569 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
570 desc->txd.cookie);
571 atc_dostart(atchan, desc);
572 list_add_tail(&desc->desc_node, &atchan->active_list);
573 } else {
574 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
575 desc->txd.cookie);
576 list_add_tail(&desc->desc_node, &atchan->queue);
577 }
578
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000579 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200580
581 return cookie;
582}
583
584/**
585 * atc_prep_dma_memcpy - prepare a memcpy operation
586 * @chan: the channel to prepare operation on
587 * @dest: operation virtual destination address
588 * @src: operation virtual source address
589 * @len: operation length
590 * @flags: tx descriptor status flags
591 */
592static struct dma_async_tx_descriptor *
593atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
594 size_t len, unsigned long flags)
595{
596 struct at_dma_chan *atchan = to_at_dma_chan(chan);
597 struct at_desc *desc = NULL;
598 struct at_desc *first = NULL;
599 struct at_desc *prev = NULL;
600 size_t xfer_count;
601 size_t offset;
602 unsigned int src_width;
603 unsigned int dst_width;
604 u32 ctrla;
605 u32 ctrlb;
606
607 dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n",
608 dest, src, len, flags);
609
610 if (unlikely(!len)) {
611 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
612 return NULL;
613 }
614
Nicolas Ferre9b3aa582011-04-30 16:57:45 +0200615 ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200616 | ATC_SRC_ADDR_MODE_INCR
617 | ATC_DST_ADDR_MODE_INCR
618 | ATC_FC_MEM2MEM;
619
620 /*
621 * We can be a lot more clever here, but this should take care
622 * of the most common optimization.
623 */
624 if (!((src | dest | len) & 3)) {
Nicolas Ferreb409ebf2012-05-10 12:17:40 +0200625 ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200626 src_width = dst_width = 2;
627 } else if (!((src | dest | len) & 1)) {
Nicolas Ferreb409ebf2012-05-10 12:17:40 +0200628 ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200629 src_width = dst_width = 1;
630 } else {
Nicolas Ferreb409ebf2012-05-10 12:17:40 +0200631 ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200632 src_width = dst_width = 0;
633 }
634
635 for (offset = 0; offset < len; offset += xfer_count << src_width) {
636 xfer_count = min_t(size_t, (len - offset) >> src_width,
637 ATC_BTSIZE_MAX);
638
639 desc = atc_desc_get(atchan);
640 if (!desc)
641 goto err_desc_get;
642
643 desc->lli.saddr = src + offset;
644 desc->lli.daddr = dest + offset;
645 desc->lli.ctrla = ctrla | xfer_count;
646 desc->lli.ctrlb = ctrlb;
647
648 desc->txd.cookie = 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200649
Nicolas Ferree257e152011-05-06 19:56:53 +0200650 atc_desc_chain(&first, &prev, desc);
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200651 }
652
653 /* First descriptor of the chain embedds additional information */
654 first->txd.cookie = -EBUSY;
655 first->len = len;
Elen Songd088c332013-05-10 11:00:50 +0800656 first->tx_width = src_width;
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200657
658 /* set end-of-link to the last link descriptor of list*/
659 set_desc_eol(desc);
660
Nicolas Ferre568f7f02011-01-12 15:39:09 +0100661 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferredc78baa2009-07-03 19:24:33 +0200662
663 return &first->txd;
664
665err_desc_get:
666 atc_desc_put(atchan, first);
667 return NULL;
668}
669
Nicolas Ferre808347f2009-07-22 20:04:45 +0200670
671/**
672 * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
673 * @chan: DMA channel
674 * @sgl: scatterlist to transfer to/from
675 * @sg_len: number of entries in @scatterlist
676 * @direction: DMA direction
677 * @flags: tx descriptor status flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500678 * @context: transaction context (ignored)
Nicolas Ferre808347f2009-07-22 20:04:45 +0200679 */
680static struct dma_async_tx_descriptor *
681atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530682 unsigned int sg_len, enum dma_transfer_direction direction,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500683 unsigned long flags, void *context)
Nicolas Ferre808347f2009-07-22 20:04:45 +0200684{
685 struct at_dma_chan *atchan = to_at_dma_chan(chan);
686 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100687 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200688 struct at_desc *first = NULL;
689 struct at_desc *prev = NULL;
690 u32 ctrla;
691 u32 ctrlb;
692 dma_addr_t reg;
693 unsigned int reg_width;
694 unsigned int mem_width;
695 unsigned int i;
696 struct scatterlist *sg;
697 size_t total_len = 0;
698
Nicolas Ferrecc52a102011-04-30 16:57:47 +0200699 dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n",
700 sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530701 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Nicolas Ferre808347f2009-07-22 20:04:45 +0200702 flags);
703
704 if (unlikely(!atslave || !sg_len)) {
Nicolas Ferrec618a9b2012-09-11 17:21:44 +0200705 dev_dbg(chan2dev(chan), "prep_slave_sg: sg length is zero!\n");
Nicolas Ferre808347f2009-07-22 20:04:45 +0200706 return NULL;
707 }
708
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +0200709 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
710 | ATC_DCSIZE(sconfig->dst_maxburst);
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200711 ctrlb = ATC_IEN;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200712
713 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +0530714 case DMA_MEM_TO_DEV:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100715 reg_width = convert_buswidth(sconfig->dst_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200716 ctrla |= ATC_DST_WIDTH(reg_width);
717 ctrlb |= ATC_DST_ADDR_MODE_FIXED
718 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200719 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000720 | ATC_SIF(atchan->mem_if) | ATC_DIF(atchan->per_if);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100721 reg = sconfig->dst_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200722 for_each_sg(sgl, sg, sg_len, i) {
723 struct at_desc *desc;
724 u32 len;
725 u32 mem;
726
727 desc = atc_desc_get(atchan);
728 if (!desc)
729 goto err_desc_get;
730
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +0100731 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200732 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +0200733 if (unlikely(!len)) {
734 dev_dbg(chan2dev(chan),
735 "prep_slave_sg: sg(%d) data length is zero\n", i);
736 goto err;
737 }
Nicolas Ferre808347f2009-07-22 20:04:45 +0200738 mem_width = 2;
739 if (unlikely(mem & 3 || len & 3))
740 mem_width = 0;
741
742 desc->lli.saddr = mem;
743 desc->lli.daddr = reg;
744 desc->lli.ctrla = ctrla
745 | ATC_SRC_WIDTH(mem_width)
746 | len >> mem_width;
747 desc->lli.ctrlb = ctrlb;
748
Nicolas Ferree257e152011-05-06 19:56:53 +0200749 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200750 total_len += len;
751 }
752 break;
Vinod Kouldb8196d2011-10-13 22:34:23 +0530753 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100754 reg_width = convert_buswidth(sconfig->src_addr_width);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200755 ctrla |= ATC_SRC_WIDTH(reg_width);
756 ctrlb |= ATC_DST_ADDR_MODE_INCR
757 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200758 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000759 | ATC_SIF(atchan->per_if) | ATC_DIF(atchan->mem_if);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200760
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100761 reg = sconfig->src_addr;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200762 for_each_sg(sgl, sg, sg_len, i) {
763 struct at_desc *desc;
764 u32 len;
765 u32 mem;
766
767 desc = atc_desc_get(atchan);
768 if (!desc)
769 goto err_desc_get;
770
Nicolas Ferre0f70e8c2010-12-15 18:50:16 +0100771 mem = sg_dma_address(sg);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200772 len = sg_dma_len(sg);
Nicolas Ferrec4567972012-09-11 17:21:45 +0200773 if (unlikely(!len)) {
774 dev_dbg(chan2dev(chan),
775 "prep_slave_sg: sg(%d) data length is zero\n", i);
776 goto err;
777 }
Nicolas Ferre808347f2009-07-22 20:04:45 +0200778 mem_width = 2;
779 if (unlikely(mem & 3 || len & 3))
780 mem_width = 0;
781
782 desc->lli.saddr = reg;
783 desc->lli.daddr = mem;
784 desc->lli.ctrla = ctrla
785 | ATC_DST_WIDTH(mem_width)
Nicolas Ferre59a609d2010-12-13 13:48:41 +0100786 | len >> reg_width;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200787 desc->lli.ctrlb = ctrlb;
788
Nicolas Ferree257e152011-05-06 19:56:53 +0200789 atc_desc_chain(&first, &prev, desc);
Nicolas Ferre808347f2009-07-22 20:04:45 +0200790 total_len += len;
791 }
792 break;
793 default:
794 return NULL;
795 }
796
797 /* set end-of-link to the last link descriptor of list*/
798 set_desc_eol(prev);
799
800 /* First descriptor of the chain embedds additional information */
801 first->txd.cookie = -EBUSY;
802 first->len = total_len;
Elen Songd088c332013-05-10 11:00:50 +0800803 first->tx_width = reg_width;
Nicolas Ferre808347f2009-07-22 20:04:45 +0200804
Nicolas Ferre568f7f02011-01-12 15:39:09 +0100805 /* first link descriptor of list is responsible of flags */
806 first->txd.flags = flags; /* client is in control of this ack */
Nicolas Ferre808347f2009-07-22 20:04:45 +0200807
808 return &first->txd;
809
810err_desc_get:
811 dev_err(chan2dev(chan), "not enough descriptors available\n");
Nicolas Ferrec4567972012-09-11 17:21:45 +0200812err:
Nicolas Ferre808347f2009-07-22 20:04:45 +0200813 atc_desc_put(atchan, first);
814 return NULL;
815}
816
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200817/**
818 * atc_dma_cyclic_check_values
819 * Check for too big/unaligned periods and unaligned DMA buffer
820 */
821static int
822atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr,
Andy Shevchenko0e7264c2013-01-10 10:52:57 +0200823 size_t period_len)
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200824{
825 if (period_len > (ATC_BTSIZE_MAX << reg_width))
826 goto err_out;
827 if (unlikely(period_len & ((1 << reg_width) - 1)))
828 goto err_out;
829 if (unlikely(buf_addr & ((1 << reg_width) - 1)))
830 goto err_out;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200831
832 return 0;
833
834err_out:
835 return -EINVAL;
836}
837
838/**
Masanari Iidad73111c2012-08-04 23:37:53 +0900839 * atc_dma_cyclic_fill_desc - Fill one period descriptor
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200840 */
841static int
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100842atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc,
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200843 unsigned int period_index, dma_addr_t buf_addr,
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100844 unsigned int reg_width, size_t period_len,
845 enum dma_transfer_direction direction)
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200846{
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100847 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100848 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
849 u32 ctrla;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200850
851 /* prepare common CRTLA value */
Nicolas Ferre1dd1ea82012-05-10 12:17:41 +0200852 ctrla = ATC_SCSIZE(sconfig->src_maxburst)
853 | ATC_DCSIZE(sconfig->dst_maxburst)
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200854 | ATC_DST_WIDTH(reg_width)
855 | ATC_SRC_WIDTH(reg_width)
856 | period_len >> reg_width;
857
858 switch (direction) {
Vinod Kouldb8196d2011-10-13 22:34:23 +0530859 case DMA_MEM_TO_DEV:
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200860 desc->lli.saddr = buf_addr + (period_len * period_index);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100861 desc->lli.daddr = sconfig->dst_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200862 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200863 desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200864 | ATC_SRC_ADDR_MODE_INCR
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200865 | ATC_FC_MEM2PER
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000866 | ATC_SIF(atchan->mem_if)
867 | ATC_DIF(atchan->per_if);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200868 break;
869
Vinod Kouldb8196d2011-10-13 22:34:23 +0530870 case DMA_DEV_TO_MEM:
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100871 desc->lli.saddr = sconfig->src_addr;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200872 desc->lli.daddr = buf_addr + (period_len * period_index);
873 desc->lli.ctrla = ctrla;
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200874 desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200875 | ATC_SRC_ADDR_MODE_FIXED
Nicolas Ferreae14d4b2011-04-30 16:57:49 +0200876 | ATC_FC_PER2MEM
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +0000877 | ATC_SIF(atchan->per_if)
878 | ATC_DIF(atchan->mem_if);
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200879 break;
880
881 default:
882 return -EINVAL;
883 }
884
885 return 0;
886}
887
888/**
889 * atc_prep_dma_cyclic - prepare the cyclic DMA transfer
890 * @chan: the DMA channel to prepare
891 * @buf_addr: physical DMA address where the buffer starts
892 * @buf_len: total number of bytes for the entire buffer
893 * @period_len: number of bytes for each period
894 * @direction: transfer direction, to or from device
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300895 * @flags: tx descriptor status flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500896 * @context: transfer context (ignored)
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200897 */
898static struct dma_async_tx_descriptor *
899atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500900 size_t period_len, enum dma_transfer_direction direction,
Peter Ujfalusiec8b5e42012-09-14 15:05:47 +0300901 unsigned long flags, void *context)
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200902{
903 struct at_dma_chan *atchan = to_at_dma_chan(chan);
904 struct at_dma_slave *atslave = chan->private;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100905 struct dma_slave_config *sconfig = &atchan->dma_sconfig;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200906 struct at_desc *first = NULL;
907 struct at_desc *prev = NULL;
908 unsigned long was_cyclic;
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100909 unsigned int reg_width;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200910 unsigned int periods = buf_len / period_len;
911 unsigned int i;
912
913 dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n",
Vinod Kouldb8196d2011-10-13 22:34:23 +0530914 direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE",
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200915 buf_addr,
916 periods, buf_len, period_len);
917
918 if (unlikely(!atslave || !buf_len || !period_len)) {
919 dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n");
920 return NULL;
921 }
922
923 was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status);
924 if (was_cyclic) {
925 dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n");
926 return NULL;
927 }
928
Andy Shevchenko0e7264c2013-01-10 10:52:57 +0200929 if (unlikely(!is_slave_direction(direction)))
930 goto err_out;
931
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100932 if (sconfig->direction == DMA_MEM_TO_DEV)
933 reg_width = convert_buswidth(sconfig->dst_addr_width);
934 else
935 reg_width = convert_buswidth(sconfig->src_addr_width);
936
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200937 /* Check for too big/unaligned periods and unaligned DMA buffer */
Andy Shevchenko0e7264c2013-01-10 10:52:57 +0200938 if (atc_dma_cyclic_check_values(reg_width, buf_addr, period_len))
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200939 goto err_out;
940
941 /* build cyclic linked list */
942 for (i = 0; i < periods; i++) {
943 struct at_desc *desc;
944
945 desc = atc_desc_get(atchan);
946 if (!desc)
947 goto err_desc_get;
948
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100949 if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr,
950 reg_width, period_len, direction))
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200951 goto err_desc_get;
952
953 atc_desc_chain(&first, &prev, desc);
954 }
955
956 /* lets make a cyclic list */
957 prev->lli.dscr = first->txd.phys;
958
959 /* First descriptor of the chain embedds additional information */
960 first->txd.cookie = -EBUSY;
961 first->len = buf_len;
Elen Songd088c332013-05-10 11:00:50 +0800962 first->tx_width = reg_width;
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200963
964 return &first->txd;
965
966err_desc_get:
967 dev_err(chan2dev(chan), "not enough descriptors available\n");
968 atc_desc_put(atchan, first);
969err_out:
970 clear_bit(ATC_IS_CYCLIC, &atchan->status);
971 return NULL;
972}
973
Nicolas Ferrebeeaa102012-03-14 12:41:43 +0100974static int set_runtime_config(struct dma_chan *chan,
975 struct dma_slave_config *sconfig)
976{
977 struct at_dma_chan *atchan = to_at_dma_chan(chan);
978
979 /* Check if it is chan is configured for slave transfers */
980 if (!chan->private)
981 return -EINVAL;
982
983 memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig));
984
985 convert_burst(&atchan->dma_sconfig.src_maxburst);
986 convert_burst(&atchan->dma_sconfig.dst_maxburst);
987
988 return 0;
989}
990
Nicolas Ferre53830cc2011-04-30 16:57:46 +0200991
Linus Walleij05827632010-05-17 16:30:42 -0700992static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
993 unsigned long arg)
Nicolas Ferre808347f2009-07-22 20:04:45 +0200994{
995 struct at_dma_chan *atchan = to_at_dma_chan(chan);
996 struct at_dma *atdma = to_at_dma(chan->device);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +0200997 int chan_id = atchan->chan_common.chan_id;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +0000998 unsigned long flags;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +0200999
Nicolas Ferre808347f2009-07-22 20:04:45 +02001000 LIST_HEAD(list);
1001
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001002 dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd);
1003
1004 if (cmd == DMA_PAUSE) {
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001005 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001006
1007 dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id));
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001008 set_bit(ATC_IS_PAUSED, &atchan->status);
1009
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001010 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001011 } else if (cmd == DMA_RESUME) {
Nicolas Ferre3c477482011-07-25 21:09:23 +00001012 if (!atc_chan_is_paused(atchan))
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001013 return 0;
1014
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001015 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001016
1017 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id));
1018 clear_bit(ATC_IS_PAUSED, &atchan->status);
1019
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001020 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001021 } else if (cmd == DMA_TERMINATE_ALL) {
1022 struct at_desc *desc, *_desc;
1023 /*
1024 * This is only called when something went wrong elsewhere, so
1025 * we don't really care about the data. Just disable the
1026 * channel. We still have to poll the channel enable bit due
1027 * to AHB/HSB limitations.
1028 */
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001029 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001030
1031 /* disabling channel: must also remove suspend state */
1032 dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask);
1033
1034 /* confirm that this channel is disabled */
1035 while (dma_readl(atdma, CHSR) & atchan->mask)
1036 cpu_relax();
1037
1038 /* active_list entries will end up before queued entries */
1039 list_splice_init(&atchan->queue, &list);
1040 list_splice_init(&atchan->active_list, &list);
1041
1042 /* Flush all pending and queued descriptors */
1043 list_for_each_entry_safe(desc, _desc, &list, desc_node)
1044 atc_chain_complete(atchan, desc);
1045
1046 clear_bit(ATC_IS_PAUSED, &atchan->status);
1047 /* if channel dedicated to cyclic operations, free it */
1048 clear_bit(ATC_IS_CYCLIC, &atchan->status);
1049
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001050 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferrebeeaa102012-03-14 12:41:43 +01001051 } else if (cmd == DMA_SLAVE_CONFIG) {
1052 return set_runtime_config(chan, (struct dma_slave_config *)arg);
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001053 } else {
Linus Walleijc3635c72010-03-26 16:44:01 -07001054 return -ENXIO;
Nicolas Ferre23b5e3a2011-05-06 19:56:52 +02001055 }
Yong Wangb0ebeb92010-08-05 10:40:08 +08001056
Linus Walleijc3635c72010-03-26 16:44:01 -07001057 return 0;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001058}
1059
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001060/**
Linus Walleij07934482010-03-26 16:50:49 -07001061 * atc_tx_status - poll for transaction completion
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001062 * @chan: DMA channel
1063 * @cookie: transaction identifier to check status of
Linus Walleij07934482010-03-26 16:50:49 -07001064 * @txstate: if not %NULL updated with transaction state
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001065 *
Linus Walleij07934482010-03-26 16:50:49 -07001066 * If @txstate is passed in, upon return it reflect the driver
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001067 * internal state and can be used with dma_async_is_complete() to check
1068 * the status of multiple cookies without re-checking hardware state.
1069 */
1070static enum dma_status
Linus Walleij07934482010-03-26 16:50:49 -07001071atc_tx_status(struct dma_chan *chan,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001072 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -07001073 struct dma_tx_state *txstate)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001074{
1075 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001076 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001077 enum dma_status ret;
Elen Songd48de6f2013-05-10 11:01:46 +08001078 int bytes = 0;
1079
1080 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul6d203d12013-10-16 13:34:35 +05301081 if (ret == DMA_COMPLETE)
Elen Songd48de6f2013-05-10 11:01:46 +08001082 return ret;
1083 /*
1084 * There's no point calculating the residue if there's
1085 * no txstate to store the value.
1086 */
1087 if (!txstate)
1088 return DMA_ERROR;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001089
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001090 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001091
Elen Songd48de6f2013-05-10 11:01:46 +08001092 /* Get number of bytes left in the active transactions */
1093 bytes = atc_get_bytes_left(chan);
Russell King - ARM Linux96a2af42012-03-06 22:35:27 +00001094
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001095 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001096
Elen Songd48de6f2013-05-10 11:01:46 +08001097 if (unlikely(bytes < 0)) {
1098 dev_vdbg(chan2dev(chan), "get residual bytes error\n");
1099 return DMA_ERROR;
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001100 } else {
Elen Songd48de6f2013-05-10 11:01:46 +08001101 dma_set_residue(txstate, bytes);
Nicolas Ferrec3dbc602013-06-07 17:26:14 +02001102 }
Nicolas Ferre543aabc2011-05-06 19:56:51 +02001103
Elen Songd48de6f2013-05-10 11:01:46 +08001104 dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d residue = %d\n",
1105 ret, cookie, bytes);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001106
1107 return ret;
1108}
1109
1110/**
1111 * atc_issue_pending - try to finish work
1112 * @chan: target DMA channel
1113 */
1114static void atc_issue_pending(struct dma_chan *chan)
1115{
1116 struct at_dma_chan *atchan = to_at_dma_chan(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001117 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001118
1119 dev_vdbg(chan2dev(chan), "issue_pending\n");
1120
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001121 /* Not needed for cyclic transfers */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001122 if (atc_chan_is_cyclic(atchan))
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001123 return;
1124
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001125 spin_lock_irqsave(&atchan->lock, flags);
Ludovic Desrochesd202f052013-04-18 09:52:59 +02001126 atc_advance_work(atchan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001127 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001128}
1129
1130/**
1131 * atc_alloc_chan_resources - allocate resources for DMA channel
1132 * @chan: allocate descriptor resources for this channel
1133 * @client: current client requesting the channel be ready for requests
1134 *
1135 * return - the number of allocated descriptors
1136 */
1137static int atc_alloc_chan_resources(struct dma_chan *chan)
1138{
1139 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1140 struct at_dma *atdma = to_at_dma(chan->device);
1141 struct at_desc *desc;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001142 struct at_dma_slave *atslave;
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001143 unsigned long flags;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001144 int i;
Nicolas Ferre808347f2009-07-22 20:04:45 +02001145 u32 cfg;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001146 LIST_HEAD(tmp_list);
1147
1148 dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
1149
1150 /* ASSERT: channel is idle */
1151 if (atc_chan_is_enabled(atchan)) {
1152 dev_dbg(chan2dev(chan), "DMA channel not idle ?\n");
1153 return -EIO;
1154 }
1155
Nicolas Ferre808347f2009-07-22 20:04:45 +02001156 cfg = ATC_DEFAULT_CFG;
1157
1158 atslave = chan->private;
1159 if (atslave) {
1160 /*
1161 * We need controller-specific data to set up slave
1162 * transfers.
1163 */
1164 BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev);
1165
Nicolas Ferreea7e7902013-05-10 15:19:13 +02001166 /* if cfg configuration specified take it instead of default */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001167 if (atslave->cfg)
1168 cfg = atslave->cfg;
1169 }
1170
1171 /* have we already been set up?
1172 * reconfigure channel but no need to reallocate descriptors */
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001173 if (!list_empty(&atchan->free_list))
1174 return atchan->descs_allocated;
1175
1176 /* Allocate initial pool of descriptors */
1177 for (i = 0; i < init_nr_desc_per_channel; i++) {
1178 desc = atc_alloc_descriptor(chan, GFP_KERNEL);
1179 if (!desc) {
1180 dev_err(atdma->dma_common.dev,
1181 "Only %d initial descriptors\n", i);
1182 break;
1183 }
1184 list_add_tail(&desc->desc_node, &tmp_list);
1185 }
1186
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001187 spin_lock_irqsave(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001188 atchan->descs_allocated = i;
Elen Songd48de6f2013-05-10 11:01:46 +08001189 atchan->remain_desc = 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001190 list_splice(&tmp_list, &atchan->free_list);
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001191 dma_cookie_init(chan);
Nicolas Ferred8cb04b2011-07-27 12:21:28 +00001192 spin_unlock_irqrestore(&atchan->lock, flags);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001193
1194 /* channel parameters */
Nicolas Ferre808347f2009-07-22 20:04:45 +02001195 channel_writel(atchan, CFG, cfg);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001196
1197 dev_dbg(chan2dev(chan),
1198 "alloc_chan_resources: allocated %d descriptors\n",
1199 atchan->descs_allocated);
1200
1201 return atchan->descs_allocated;
1202}
1203
1204/**
1205 * atc_free_chan_resources - free all channel resources
1206 * @chan: DMA channel
1207 */
1208static void atc_free_chan_resources(struct dma_chan *chan)
1209{
1210 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1211 struct at_dma *atdma = to_at_dma(chan->device);
1212 struct at_desc *desc, *_desc;
1213 LIST_HEAD(list);
1214
1215 dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n",
1216 atchan->descs_allocated);
1217
1218 /* ASSERT: channel is idle */
1219 BUG_ON(!list_empty(&atchan->active_list));
1220 BUG_ON(!list_empty(&atchan->queue));
1221 BUG_ON(atc_chan_is_enabled(atchan));
1222
1223 list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) {
1224 dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
1225 list_del(&desc->desc_node);
1226 /* free link descriptor */
1227 dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys);
1228 }
1229 list_splice_init(&atchan->free_list, &list);
1230 atchan->descs_allocated = 0;
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001231 atchan->status = 0;
Elen Songd48de6f2013-05-10 11:01:46 +08001232 atchan->remain_desc = 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001233
1234 dev_vdbg(chan2dev(chan), "free_chan_resources: done\n");
1235}
1236
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001237#ifdef CONFIG_OF
1238static bool at_dma_filter(struct dma_chan *chan, void *slave)
1239{
1240 struct at_dma_slave *atslave = slave;
1241
1242 if (atslave->dma_dev == chan->device->dev) {
1243 chan->private = atslave;
1244 return true;
1245 } else {
1246 return false;
1247 }
1248}
1249
1250static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1251 struct of_dma *of_dma)
1252{
1253 struct dma_chan *chan;
1254 struct at_dma_chan *atchan;
1255 struct at_dma_slave *atslave;
1256 dma_cap_mask_t mask;
1257 unsigned int per_id;
1258 struct platform_device *dmac_pdev;
1259
1260 if (dma_spec->args_count != 2)
1261 return NULL;
1262
1263 dmac_pdev = of_find_device_by_node(dma_spec->np);
1264
1265 dma_cap_zero(mask);
1266 dma_cap_set(DMA_SLAVE, mask);
1267
1268 atslave = devm_kzalloc(&dmac_pdev->dev, sizeof(*atslave), GFP_KERNEL);
1269 if (!atslave)
1270 return NULL;
Ludovic Desroches62971b22013-06-13 10:39:39 +02001271
1272 atslave->cfg = ATC_DST_H2SEL_HW | ATC_SRC_H2SEL_HW;
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001273 /*
1274 * We can fill both SRC_PER and DST_PER, one of these fields will be
1275 * ignored depending on DMA transfer direction.
1276 */
Ludovic Desroches62971b22013-06-13 10:39:39 +02001277 per_id = dma_spec->args[1] & AT91_DMA_CFG_PER_ID_MASK;
1278 atslave->cfg |= ATC_DST_PER_MSB(per_id) | ATC_DST_PER(per_id)
Nicolas Ferre6c227702013-05-10 15:19:15 +02001279 | ATC_SRC_PER_MSB(per_id) | ATC_SRC_PER(per_id);
Ludovic Desroches62971b22013-06-13 10:39:39 +02001280 /*
1281 * We have to translate the value we get from the device tree since
1282 * the half FIFO configuration value had to be 0 to keep backward
1283 * compatibility.
1284 */
1285 switch (dma_spec->args[1] & AT91_DMA_CFG_FIFOCFG_MASK) {
1286 case AT91_DMA_CFG_FIFOCFG_ALAP:
1287 atslave->cfg |= ATC_FIFOCFG_LARGESTBURST;
1288 break;
1289 case AT91_DMA_CFG_FIFOCFG_ASAP:
1290 atslave->cfg |= ATC_FIFOCFG_ENOUGHSPACE;
1291 break;
1292 case AT91_DMA_CFG_FIFOCFG_HALF:
1293 default:
1294 atslave->cfg |= ATC_FIFOCFG_HALFFIFO;
1295 }
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001296 atslave->dma_dev = &dmac_pdev->dev;
1297
1298 chan = dma_request_channel(mask, at_dma_filter, atslave);
1299 if (!chan)
1300 return NULL;
1301
1302 atchan = to_at_dma_chan(chan);
1303 atchan->per_if = dma_spec->args[0] & 0xff;
1304 atchan->mem_if = (dma_spec->args[0] >> 16) & 0xff;
1305
1306 return chan;
1307}
1308#else
1309static struct dma_chan *at_dma_xlate(struct of_phandle_args *dma_spec,
1310 struct of_dma *of_dma)
1311{
1312 return NULL;
1313}
1314#endif
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001315
1316/*-- Module Management -----------------------------------------------*/
1317
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001318/* cap_mask is a multi-u32 bitfield, fill it with proper C code. */
1319static struct at_dma_platform_data at91sam9rl_config = {
1320 .nr_channels = 2,
1321};
1322static struct at_dma_platform_data at91sam9g45_config = {
1323 .nr_channels = 8,
1324};
1325
Nicolas Ferrec5115952011-10-17 14:56:41 +02001326#if defined(CONFIG_OF)
1327static const struct of_device_id atmel_dma_dt_ids[] = {
1328 {
1329 .compatible = "atmel,at91sam9rl-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001330 .data = &at91sam9rl_config,
Nicolas Ferrec5115952011-10-17 14:56:41 +02001331 }, {
1332 .compatible = "atmel,at91sam9g45-dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001333 .data = &at91sam9g45_config,
Nicolas Ferredcc81732011-11-22 11:55:53 +01001334 }, {
1335 /* sentinel */
1336 }
Nicolas Ferrec5115952011-10-17 14:56:41 +02001337};
1338
1339MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids);
1340#endif
1341
Nicolas Ferre0ab88a02011-11-22 11:55:52 +01001342static const struct platform_device_id atdma_devtypes[] = {
Nicolas Ferre67348452011-10-17 14:56:40 +02001343 {
1344 .name = "at91sam9rl_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001345 .driver_data = (unsigned long) &at91sam9rl_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001346 }, {
1347 .name = "at91sam9g45_dma",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001348 .driver_data = (unsigned long) &at91sam9g45_config,
Nicolas Ferre67348452011-10-17 14:56:40 +02001349 }, {
1350 /* sentinel */
1351 }
1352};
1353
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001354static inline const struct at_dma_platform_data * __init at_dma_get_driver_data(
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001355 struct platform_device *pdev)
Nicolas Ferrec5115952011-10-17 14:56:41 +02001356{
1357 if (pdev->dev.of_node) {
1358 const struct of_device_id *match;
1359 match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node);
1360 if (match == NULL)
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001361 return NULL;
1362 return match->data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001363 }
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001364 return (struct at_dma_platform_data *)
1365 platform_get_device_id(pdev)->driver_data;
Nicolas Ferrec5115952011-10-17 14:56:41 +02001366}
1367
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001368/**
1369 * at_dma_off - disable DMA controller
1370 * @atdma: the Atmel HDAMC device
1371 */
1372static void at_dma_off(struct at_dma *atdma)
1373{
1374 dma_writel(atdma, EN, 0);
1375
1376 /* disable all interrupts */
1377 dma_writel(atdma, EBCIDR, -1L);
1378
1379 /* confirm that all channels are disabled */
1380 while (dma_readl(atdma, CHSR) & atdma->all_chan_mask)
1381 cpu_relax();
1382}
1383
1384static int __init at_dma_probe(struct platform_device *pdev)
1385{
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001386 struct resource *io;
1387 struct at_dma *atdma;
1388 size_t size;
1389 int irq;
1390 int err;
1391 int i;
Uwe Kleine-König7fd63cc2012-07-13 14:32:10 +02001392 const struct at_dma_platform_data *plat_dat;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001393
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001394 /* setup platform data for each SoC */
1395 dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask);
1396 dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask);
1397 dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask);
Nicolas Ferre67348452011-10-17 14:56:40 +02001398
1399 /* get DMA parameters from controller type */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001400 plat_dat = at_dma_get_driver_data(pdev);
1401 if (!plat_dat)
1402 return -ENODEV;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001403
1404 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1405 if (!io)
1406 return -EINVAL;
1407
1408 irq = platform_get_irq(pdev, 0);
1409 if (irq < 0)
1410 return irq;
1411
1412 size = sizeof(struct at_dma);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001413 size += plat_dat->nr_channels * sizeof(struct at_dma_chan);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001414 atdma = kzalloc(size, GFP_KERNEL);
1415 if (!atdma)
1416 return -ENOMEM;
1417
Nicolas Ferre67348452011-10-17 14:56:40 +02001418 /* discover transaction capabilities */
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001419 atdma->dma_common.cap_mask = plat_dat->cap_mask;
1420 atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001421
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07001422 size = resource_size(io);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001423 if (!request_mem_region(io->start, size, pdev->dev.driver->name)) {
1424 err = -EBUSY;
1425 goto err_kfree;
1426 }
1427
1428 atdma->regs = ioremap(io->start, size);
1429 if (!atdma->regs) {
1430 err = -ENOMEM;
1431 goto err_release_r;
1432 }
1433
1434 atdma->clk = clk_get(&pdev->dev, "dma_clk");
1435 if (IS_ERR(atdma->clk)) {
1436 err = PTR_ERR(atdma->clk);
1437 goto err_clk;
1438 }
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001439 err = clk_prepare_enable(atdma->clk);
1440 if (err)
1441 goto err_clk_prepare;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001442
1443 /* force dma off, just in case */
1444 at_dma_off(atdma);
1445
1446 err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma);
1447 if (err)
1448 goto err_irq;
1449
1450 platform_set_drvdata(pdev, atdma);
1451
1452 /* create a pool of consistent memory blocks for hardware descriptors */
1453 atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool",
1454 &pdev->dev, sizeof(struct at_desc),
1455 4 /* word alignment */, 0);
1456 if (!atdma->dma_desc_pool) {
1457 dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
1458 err = -ENOMEM;
1459 goto err_pool_create;
1460 }
1461
1462 /* clear any pending interrupt */
1463 while (dma_readl(atdma, EBCISR))
1464 cpu_relax();
1465
1466 /* initialize channels related values */
1467 INIT_LIST_HEAD(&atdma->dma_common.channels);
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001468 for (i = 0; i < plat_dat->nr_channels; i++) {
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001469 struct at_dma_chan *atchan = &atdma->chan[i];
1470
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001471 atchan->mem_if = AT_DMA_MEM_IF;
1472 atchan->per_if = AT_DMA_PER_IF;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001473 atchan->chan_common.device = &atdma->dma_common;
Russell King - ARM Linuxd3ee98cdc2012-03-06 22:35:47 +00001474 dma_cookie_init(&atchan->chan_common);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001475 list_add_tail(&atchan->chan_common.device_node,
1476 &atdma->dma_common.channels);
1477
1478 atchan->ch_regs = atdma->regs + ch_regs(i);
1479 spin_lock_init(&atchan->lock);
1480 atchan->mask = 1 << i;
1481
1482 INIT_LIST_HEAD(&atchan->active_list);
1483 INIT_LIST_HEAD(&atchan->queue);
1484 INIT_LIST_HEAD(&atchan->free_list);
1485
1486 tasklet_init(&atchan->tasklet, atc_tasklet,
1487 (unsigned long)atchan);
Nikolaus Vossbda3a472012-01-17 10:28:33 +01001488 atc_enable_chan_irq(atdma, i);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001489 }
1490
1491 /* set base routines */
1492 atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources;
1493 atdma->dma_common.device_free_chan_resources = atc_free_chan_resources;
Linus Walleij07934482010-03-26 16:50:49 -07001494 atdma->dma_common.device_tx_status = atc_tx_status;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001495 atdma->dma_common.device_issue_pending = atc_issue_pending;
1496 atdma->dma_common.dev = &pdev->dev;
1497
1498 /* set prep routines based on capability */
1499 if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask))
1500 atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy;
1501
Nicolas Ferred7db8082011-08-05 11:43:44 +00001502 if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) {
Nicolas Ferre808347f2009-07-22 20:04:45 +02001503 atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg;
Nicolas Ferred7db8082011-08-05 11:43:44 +00001504 /* controller can do slave DMA: can trigger cyclic transfers */
1505 dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask);
Nicolas Ferre53830cc2011-04-30 16:57:46 +02001506 atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic;
Linus Walleijc3635c72010-03-26 16:44:01 -07001507 atdma->dma_common.device_control = atc_control;
Nicolas Ferred7db8082011-08-05 11:43:44 +00001508 }
Nicolas Ferre808347f2009-07-22 20:04:45 +02001509
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001510 dma_writel(atdma, EN, AT_DMA_ENABLE);
1511
1512 dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n",
1513 dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "",
1514 dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "",
Nicolas Ferre02f88be2011-11-22 11:55:54 +01001515 plat_dat->nr_channels);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001516
1517 dma_async_device_register(&atdma->dma_common);
1518
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001519 /*
1520 * Do not return an error if the dmac node is not present in order to
1521 * not break the existing way of requesting channel with
1522 * dma_request_channel().
1523 */
1524 if (pdev->dev.of_node) {
1525 err = of_dma_controller_register(pdev->dev.of_node,
1526 at_dma_xlate, atdma);
1527 if (err) {
1528 dev_err(&pdev->dev, "could not register of_dma_controller\n");
1529 goto err_of_dma_controller_register;
1530 }
1531 }
1532
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001533 return 0;
1534
Ludovic Desrochesbbe89c82013-04-19 09:11:18 +00001535err_of_dma_controller_register:
1536 dma_async_device_unregister(&atdma->dma_common);
1537 dma_pool_destroy(atdma->dma_desc_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001538err_pool_create:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001539 free_irq(platform_get_irq(pdev, 0), atdma);
1540err_irq:
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001541 clk_disable_unprepare(atdma->clk);
1542err_clk_prepare:
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001543 clk_put(atdma->clk);
1544err_clk:
1545 iounmap(atdma->regs);
1546 atdma->regs = NULL;
1547err_release_r:
1548 release_mem_region(io->start, size);
1549err_kfree:
1550 kfree(atdma);
1551 return err;
1552}
1553
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001554static int at_dma_remove(struct platform_device *pdev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001555{
1556 struct at_dma *atdma = platform_get_drvdata(pdev);
1557 struct dma_chan *chan, *_chan;
1558 struct resource *io;
1559
1560 at_dma_off(atdma);
1561 dma_async_device_unregister(&atdma->dma_common);
1562
1563 dma_pool_destroy(atdma->dma_desc_pool);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001564 free_irq(platform_get_irq(pdev, 0), atdma);
1565
1566 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1567 device_node) {
1568 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1569
1570 /* Disable interrupts */
Nikolaus Vossbda3a472012-01-17 10:28:33 +01001571 atc_disable_chan_irq(atdma, chan->chan_id);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001572
1573 tasklet_kill(&atchan->tasklet);
1574 list_del(&chan->device_node);
1575 }
1576
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001577 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001578 clk_put(atdma->clk);
1579
1580 iounmap(atdma->regs);
1581 atdma->regs = NULL;
1582
1583 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
H Hartley Sweeten114df7d2011-06-01 15:16:09 -07001584 release_mem_region(io->start, resource_size(io));
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001585
1586 kfree(atdma);
1587
1588 return 0;
1589}
1590
1591static void at_dma_shutdown(struct platform_device *pdev)
1592{
1593 struct at_dma *atdma = platform_get_drvdata(pdev);
1594
1595 at_dma_off(platform_get_drvdata(pdev));
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001596 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001597}
1598
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001599static int at_dma_prepare(struct device *dev)
1600{
1601 struct platform_device *pdev = to_platform_device(dev);
1602 struct at_dma *atdma = platform_get_drvdata(pdev);
1603 struct dma_chan *chan, *_chan;
1604
1605 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1606 device_node) {
1607 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1608 /* wait for transaction completion (except in cyclic case) */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001609 if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001610 return -EAGAIN;
1611 }
1612 return 0;
1613}
1614
1615static void atc_suspend_cyclic(struct at_dma_chan *atchan)
1616{
1617 struct dma_chan *chan = &atchan->chan_common;
1618
1619 /* Channel should be paused by user
1620 * do it anyway even if it is not done already */
Nicolas Ferre3c477482011-07-25 21:09:23 +00001621 if (!atc_chan_is_paused(atchan)) {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001622 dev_warn(chan2dev(chan),
1623 "cyclic channel not paused, should be done by channel user\n");
1624 atc_control(chan, DMA_PAUSE, 0);
1625 }
1626
1627 /* now preserve additional data for cyclic operations */
1628 /* next descriptor address in the cyclic list */
1629 atchan->save_dscr = channel_readl(atchan, DSCR);
1630
1631 vdbg_dump_regs(atchan);
1632}
1633
Dan Williams33f82d12009-09-10 00:06:44 +02001634static int at_dma_suspend_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001635{
Dan Williams33f82d12009-09-10 00:06:44 +02001636 struct platform_device *pdev = to_platform_device(dev);
1637 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001638 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001639
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001640 /* preserve data */
1641 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1642 device_node) {
1643 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1644
Nicolas Ferre3c477482011-07-25 21:09:23 +00001645 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001646 atc_suspend_cyclic(atchan);
1647 atchan->save_cfg = channel_readl(atchan, CFG);
1648 }
1649 atdma->save_imr = dma_readl(atdma, EBCIMR);
1650
1651 /* disable DMA controller */
1652 at_dma_off(atdma);
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001653 clk_disable_unprepare(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001654 return 0;
1655}
1656
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001657static void atc_resume_cyclic(struct at_dma_chan *atchan)
1658{
1659 struct at_dma *atdma = to_at_dma(atchan->chan_common.device);
1660
1661 /* restore channel status for cyclic descriptors list:
1662 * next descriptor in the cyclic list at the time of suspend */
1663 channel_writel(atchan, SADDR, 0);
1664 channel_writel(atchan, DADDR, 0);
1665 channel_writel(atchan, CTRLA, 0);
1666 channel_writel(atchan, CTRLB, 0);
1667 channel_writel(atchan, DSCR, atchan->save_dscr);
1668 dma_writel(atdma, CHER, atchan->mask);
1669
1670 /* channel pause status should be removed by channel user
1671 * We cannot take the initiative to do it here */
1672
1673 vdbg_dump_regs(atchan);
1674}
1675
Dan Williams33f82d12009-09-10 00:06:44 +02001676static int at_dma_resume_noirq(struct device *dev)
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001677{
Dan Williams33f82d12009-09-10 00:06:44 +02001678 struct platform_device *pdev = to_platform_device(dev);
1679 struct at_dma *atdma = platform_get_drvdata(pdev);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001680 struct dma_chan *chan, *_chan;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001681
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001682 /* bring back DMA controller */
Boris BREZILLONf784d9c2013-06-19 13:14:54 +02001683 clk_prepare_enable(atdma->clk);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001684 dma_writel(atdma, EN, AT_DMA_ENABLE);
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001685
1686 /* clear any pending interrupt */
1687 while (dma_readl(atdma, EBCISR))
1688 cpu_relax();
1689
1690 /* restore saved data */
1691 dma_writel(atdma, EBCIER, atdma->save_imr);
1692 list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels,
1693 device_node) {
1694 struct at_dma_chan *atchan = to_at_dma_chan(chan);
1695
1696 channel_writel(atchan, CFG, atchan->save_cfg);
Nicolas Ferre3c477482011-07-25 21:09:23 +00001697 if (atc_chan_is_cyclic(atchan))
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001698 atc_resume_cyclic(atchan);
1699 }
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001700 return 0;
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001701}
1702
Alexey Dobriyan47145212009-12-14 18:00:08 -08001703static const struct dev_pm_ops at_dma_dev_pm_ops = {
Nicolas Ferrec0ba5942011-07-27 12:21:29 +00001704 .prepare = at_dma_prepare,
Dan Williams33f82d12009-09-10 00:06:44 +02001705 .suspend_noirq = at_dma_suspend_noirq,
1706 .resume_noirq = at_dma_resume_noirq,
1707};
1708
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001709static struct platform_driver at_dma_driver = {
Maxin B. John1d1bbd32013-02-20 02:07:04 +02001710 .remove = at_dma_remove,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001711 .shutdown = at_dma_shutdown,
Nicolas Ferre67348452011-10-17 14:56:40 +02001712 .id_table = atdma_devtypes,
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001713 .driver = {
1714 .name = "at_hdmac",
Dan Williams33f82d12009-09-10 00:06:44 +02001715 .pm = &at_dma_dev_pm_ops,
Nicolas Ferrec5115952011-10-17 14:56:41 +02001716 .of_match_table = of_match_ptr(atmel_dma_dt_ids),
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001717 },
1718};
1719
1720static int __init at_dma_init(void)
1721{
1722 return platform_driver_probe(&at_dma_driver, at_dma_probe);
1723}
Eric Xu93d0bec2011-01-12 15:39:08 +01001724subsys_initcall(at_dma_init);
Nicolas Ferredc78baa2009-07-03 19:24:33 +02001725
1726static void __exit at_dma_exit(void)
1727{
1728 platform_driver_unregister(&at_dma_driver);
1729}
1730module_exit(at_dma_exit);
1731
1732MODULE_DESCRIPTION("Atmel AHB DMA Controller driver");
1733MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>");
1734MODULE_LICENSE("GPL");
1735MODULE_ALIAS("platform:at_hdmac");