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Andy Shevchenko4b45efe2015-07-27 18:04:03 +03001/*
2 * Intel LPSS PCI support.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 *
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/ioport.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pci.h>
18#include <linux/pm.h>
19#include <linux/pm_runtime.h>
Mika Westerberg028af592015-11-30 17:11:42 +020020#include <linux/property.h>
Andy Shevchenko4b45efe2015-07-27 18:04:03 +030021
22#include "intel-lpss.h"
23
24static int intel_lpss_pci_probe(struct pci_dev *pdev,
25 const struct pci_device_id *id)
26{
27 struct intel_lpss_platform_info *info;
28 int ret;
29
30 ret = pcim_enable_device(pdev);
31 if (ret)
32 return ret;
33
34 info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
35 GFP_KERNEL);
36 if (!info)
37 return -ENOMEM;
38
39 info->mem = &pdev->resource[0];
40 info->irq = pdev->irq;
41
Kai-Heng Feng8573fcd2019-07-05 12:55:03 +080042 pdev->d3cold_delay = 0;
43
Andy Shevchenko4b45efe2015-07-27 18:04:03 +030044 /* Probably it is enough to set this for iDMA capable devices only */
45 pci_set_master(pdev);
46
47 ret = intel_lpss_probe(&pdev->dev, info);
48 if (ret)
49 return ret;
50
51 pm_runtime_put(&pdev->dev);
52 pm_runtime_allow(&pdev->dev);
53
54 return 0;
55}
56
57static void intel_lpss_pci_remove(struct pci_dev *pdev)
58{
59 pm_runtime_forbid(&pdev->dev);
60 pm_runtime_get_sync(&pdev->dev);
61
62 intel_lpss_remove(&pdev->dev);
63}
64
65static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
66
67static const struct intel_lpss_platform_info spt_info = {
68 .clk_rate = 120000000,
69};
70
Mika Westerberg028af592015-11-30 17:11:42 +020071static struct property_entry spt_i2c_properties[] = {
72 PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 230),
73 { },
74};
75
Mika Westerberg028af592015-11-30 17:11:42 +020076static const struct intel_lpss_platform_info spt_i2c_info = {
77 .clk_rate = 120000000,
Heikki Krogerusf4d05262016-03-29 14:52:23 +030078 .properties = spt_i2c_properties,
Mika Westerberg028af592015-11-30 17:11:42 +020079};
80
Andy Shevchenkoec14c532015-11-30 17:11:43 +020081static struct property_entry uart_properties[] = {
82 PROPERTY_ENTRY_U32("reg-io-width", 4),
83 PROPERTY_ENTRY_U32("reg-shift", 2),
84 PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
85 { },
86};
87
Andy Shevchenko4b45efe2015-07-27 18:04:03 +030088static const struct intel_lpss_platform_info spt_uart_info = {
89 .clk_rate = 120000000,
90 .clk_con_id = "baudclk",
Heikki Krogerusf4d05262016-03-29 14:52:23 +030091 .properties = uart_properties,
Andy Shevchenko4b45efe2015-07-27 18:04:03 +030092};
93
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +030094static const struct intel_lpss_platform_info bxt_info = {
95 .clk_rate = 100000000,
96};
97
98static const struct intel_lpss_platform_info bxt_uart_info = {
99 .clk_rate = 100000000,
100 .clk_con_id = "baudclk",
Heikki Krogerusf4d05262016-03-29 14:52:23 +0300101 .properties = uart_properties,
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300102};
103
Mika Westerberg0343b2f2016-01-26 14:17:49 +0200104static struct property_entry bxt_i2c_properties[] = {
105 PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 42),
106 PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
107 PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
108 { },
109};
110
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300111static const struct intel_lpss_platform_info bxt_i2c_info = {
112 .clk_rate = 133000000,
Heikki Krogerusf4d05262016-03-29 14:52:23 +0300113 .properties = bxt_i2c_properties,
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300114};
115
Jarkko Nikulac50cdd62016-09-12 14:41:33 +0300116static struct property_entry apl_i2c_properties[] = {
117 PROPERTY_ENTRY_U32("i2c-sda-hold-time-ns", 207),
118 PROPERTY_ENTRY_U32("i2c-sda-falling-time-ns", 171),
119 PROPERTY_ENTRY_U32("i2c-scl-falling-time-ns", 208),
120 { },
121};
122
123static const struct intel_lpss_platform_info apl_i2c_info = {
124 .clk_rate = 133000000,
125 .properties = apl_i2c_properties,
126};
127
Andy Shevchenko4b45efe2015-07-27 18:04:03 +0300128static const struct pci_device_id intel_lpss_pci_ids[] = {
Huiquan Zhong023269c2016-01-15 00:12:31 +0800129 /* BXT A-Step */
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300130 { PCI_VDEVICE(INTEL, 0x0aac), (kernel_ulong_t)&bxt_i2c_info },
131 { PCI_VDEVICE(INTEL, 0x0aae), (kernel_ulong_t)&bxt_i2c_info },
132 { PCI_VDEVICE(INTEL, 0x0ab0), (kernel_ulong_t)&bxt_i2c_info },
133 { PCI_VDEVICE(INTEL, 0x0ab2), (kernel_ulong_t)&bxt_i2c_info },
134 { PCI_VDEVICE(INTEL, 0x0ab4), (kernel_ulong_t)&bxt_i2c_info },
135 { PCI_VDEVICE(INTEL, 0x0ab6), (kernel_ulong_t)&bxt_i2c_info },
136 { PCI_VDEVICE(INTEL, 0x0ab8), (kernel_ulong_t)&bxt_i2c_info },
137 { PCI_VDEVICE(INTEL, 0x0aba), (kernel_ulong_t)&bxt_i2c_info },
138 { PCI_VDEVICE(INTEL, 0x0abc), (kernel_ulong_t)&bxt_uart_info },
139 { PCI_VDEVICE(INTEL, 0x0abe), (kernel_ulong_t)&bxt_uart_info },
140 { PCI_VDEVICE(INTEL, 0x0ac0), (kernel_ulong_t)&bxt_uart_info },
141 { PCI_VDEVICE(INTEL, 0x0ac2), (kernel_ulong_t)&bxt_info },
142 { PCI_VDEVICE(INTEL, 0x0ac4), (kernel_ulong_t)&bxt_info },
143 { PCI_VDEVICE(INTEL, 0x0ac6), (kernel_ulong_t)&bxt_info },
144 { PCI_VDEVICE(INTEL, 0x0aee), (kernel_ulong_t)&bxt_uart_info },
Huiquan Zhong023269c2016-01-15 00:12:31 +0800145 /* BXT B-Step */
146 { PCI_VDEVICE(INTEL, 0x1aac), (kernel_ulong_t)&bxt_i2c_info },
147 { PCI_VDEVICE(INTEL, 0x1aae), (kernel_ulong_t)&bxt_i2c_info },
148 { PCI_VDEVICE(INTEL, 0x1ab0), (kernel_ulong_t)&bxt_i2c_info },
149 { PCI_VDEVICE(INTEL, 0x1ab2), (kernel_ulong_t)&bxt_i2c_info },
150 { PCI_VDEVICE(INTEL, 0x1ab4), (kernel_ulong_t)&bxt_i2c_info },
151 { PCI_VDEVICE(INTEL, 0x1ab6), (kernel_ulong_t)&bxt_i2c_info },
152 { PCI_VDEVICE(INTEL, 0x1ab8), (kernel_ulong_t)&bxt_i2c_info },
153 { PCI_VDEVICE(INTEL, 0x1aba), (kernel_ulong_t)&bxt_i2c_info },
154 { PCI_VDEVICE(INTEL, 0x1abc), (kernel_ulong_t)&bxt_uart_info },
155 { PCI_VDEVICE(INTEL, 0x1abe), (kernel_ulong_t)&bxt_uart_info },
156 { PCI_VDEVICE(INTEL, 0x1ac0), (kernel_ulong_t)&bxt_uart_info },
157 { PCI_VDEVICE(INTEL, 0x1ac2), (kernel_ulong_t)&bxt_info },
158 { PCI_VDEVICE(INTEL, 0x1ac4), (kernel_ulong_t)&bxt_info },
159 { PCI_VDEVICE(INTEL, 0x1ac6), (kernel_ulong_t)&bxt_info },
160 { PCI_VDEVICE(INTEL, 0x1aee), (kernel_ulong_t)&bxt_uart_info },
161
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300162 /* APL */
Jarkko Nikulac50cdd62016-09-12 14:41:33 +0300163 { PCI_VDEVICE(INTEL, 0x5aac), (kernel_ulong_t)&apl_i2c_info },
164 { PCI_VDEVICE(INTEL, 0x5aae), (kernel_ulong_t)&apl_i2c_info },
165 { PCI_VDEVICE(INTEL, 0x5ab0), (kernel_ulong_t)&apl_i2c_info },
166 { PCI_VDEVICE(INTEL, 0x5ab2), (kernel_ulong_t)&apl_i2c_info },
167 { PCI_VDEVICE(INTEL, 0x5ab4), (kernel_ulong_t)&apl_i2c_info },
168 { PCI_VDEVICE(INTEL, 0x5ab6), (kernel_ulong_t)&apl_i2c_info },
169 { PCI_VDEVICE(INTEL, 0x5ab8), (kernel_ulong_t)&apl_i2c_info },
170 { PCI_VDEVICE(INTEL, 0x5aba), (kernel_ulong_t)&apl_i2c_info },
Andy Shevchenkoff0a04a2015-10-21 12:41:48 +0300171 { PCI_VDEVICE(INTEL, 0x5abc), (kernel_ulong_t)&bxt_uart_info },
172 { PCI_VDEVICE(INTEL, 0x5abe), (kernel_ulong_t)&bxt_uart_info },
173 { PCI_VDEVICE(INTEL, 0x5ac0), (kernel_ulong_t)&bxt_uart_info },
174 { PCI_VDEVICE(INTEL, 0x5ac2), (kernel_ulong_t)&bxt_info },
175 { PCI_VDEVICE(INTEL, 0x5ac4), (kernel_ulong_t)&bxt_info },
176 { PCI_VDEVICE(INTEL, 0x5ac6), (kernel_ulong_t)&bxt_info },
177 { PCI_VDEVICE(INTEL, 0x5aee), (kernel_ulong_t)&bxt_uart_info },
Andy Shevchenko4b45efe2015-07-27 18:04:03 +0300178 /* SPT-LP */
179 { PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
180 { PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
181 { PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
182 { PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
Mika Westerberg028af592015-11-30 17:11:42 +0200183 { PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_i2c_info },
184 { PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_i2c_info },
185 { PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_i2c_info },
186 { PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_i2c_info },
187 { PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_i2c_info },
188 { PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_i2c_info },
Andy Shevchenko4b45efe2015-07-27 18:04:03 +0300189 { PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
190 /* SPT-H */
191 { PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
192 { PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
193 { PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
194 { PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
Mika Westerberg028af592015-11-30 17:11:42 +0200195 { PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_i2c_info },
196 { PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_i2c_info },
Andy Shevchenko4b45efe2015-07-27 18:04:03 +0300197 { PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
Mika Westerberg77fc5ff2016-07-04 18:24:54 +0300198 /* KBL-H */
Jarkko Nikula2c8c3412016-09-29 12:59:39 +0300199 { PCI_VDEVICE(INTEL, 0xa2a7), (kernel_ulong_t)&spt_uart_info },
200 { PCI_VDEVICE(INTEL, 0xa2a8), (kernel_ulong_t)&spt_uart_info },
201 { PCI_VDEVICE(INTEL, 0xa2a9), (kernel_ulong_t)&spt_info },
202 { PCI_VDEVICE(INTEL, 0xa2aa), (kernel_ulong_t)&spt_info },
203 { PCI_VDEVICE(INTEL, 0xa2e0), (kernel_ulong_t)&spt_i2c_info },
204 { PCI_VDEVICE(INTEL, 0xa2e1), (kernel_ulong_t)&spt_i2c_info },
205 { PCI_VDEVICE(INTEL, 0xa2e2), (kernel_ulong_t)&spt_i2c_info },
206 { PCI_VDEVICE(INTEL, 0xa2e3), (kernel_ulong_t)&spt_i2c_info },
207 { PCI_VDEVICE(INTEL, 0xa2e6), (kernel_ulong_t)&spt_uart_info },
Andy Shevchenko4b45efe2015-07-27 18:04:03 +0300208 { }
209};
210MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
211
212static struct pci_driver intel_lpss_pci_driver = {
213 .name = "intel-lpss",
214 .id_table = intel_lpss_pci_ids,
215 .probe = intel_lpss_pci_probe,
216 .remove = intel_lpss_pci_remove,
217 .driver = {
218 .pm = &intel_lpss_pci_pm_ops,
219 },
220};
221
222module_pci_driver(intel_lpss_pci_driver);
223
224MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
225MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
226MODULE_DESCRIPTION("Intel LPSS PCI driver");
227MODULE_LICENSE("GPL v2");