Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.9 / 5c938b911f2fe214ce8e77ff4b7c05bfc12b0034 / . / drivers / phy / phy-qcom-ufs-qmp-14nm.h
blob: 46e652f344011947d0b9005c0ab30dc9b1d366db [file] [log] [blame]
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]1/*
2 * Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 */
14
15#ifndef UFS_QCOM_PHY_QMP_14NM_H_
16#define UFS_QCOM_PHY_QMP_14NM_H_
17
18#include "phy-qcom-ufs-i.h"
19
20/* QCOM UFS PHY control registers */
21#define COM_OFF(x) (0x000 + x)
22#define PHY_OFF(x) (0xC00 + x)
23#define TX_OFF(n, x) (0x400 + (0x400 * n) + x)
24#define RX_OFF(n, x) (0x600 + (0x400 * n) + x)
25
26/* UFS PHY QSERDES COM registers */
27#define QSERDES_COM_BG_TIMER COM_OFF(0x0C)
28#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN COM_OFF(0x34)
29#define QSERDES_COM_SYS_CLK_CTRL COM_OFF(0x3C)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]30#define QSERDES_COM_PLL_IVCO COM_OFF(0x48)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]31#define QSERDES_COM_LOCK_CMP1_MODE0 COM_OFF(0x4C)
32#define QSERDES_COM_LOCK_CMP2_MODE0 COM_OFF(0x50)
33#define QSERDES_COM_LOCK_CMP3_MODE0 COM_OFF(0x54)
34#define QSERDES_COM_LOCK_CMP1_MODE1 COM_OFF(0x58)
35#define QSERDES_COM_LOCK_CMP2_MODE1 COM_OFF(0x5C)
36#define QSERDES_COM_LOCK_CMP3_MODE1 COM_OFF(0x60)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]37#define QSERDES_COM_BG_TRIM COM_OFF(0x70)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]38#define QSERDES_COM_CP_CTRL_MODE0 COM_OFF(0x78)
39#define QSERDES_COM_CP_CTRL_MODE1 COM_OFF(0x7C)
40#define QSERDES_COM_PLL_RCTRL_MODE0 COM_OFF(0x84)
41#define QSERDES_COM_PLL_RCTRL_MODE1 COM_OFF(0x88)
42#define QSERDES_COM_PLL_CCTRL_MODE0 COM_OFF(0x90)
43#define QSERDES_COM_PLL_CCTRL_MODE1 COM_OFF(0x94)
44#define QSERDES_COM_SYSCLK_EN_SEL COM_OFF(0xAC)
45#define QSERDES_COM_RESETSM_CNTRL COM_OFF(0xB4)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]46#define QSERDES_COM_RESCODE_DIV_NUM COM_OFF(0xC4)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]47#define QSERDES_COM_LOCK_CMP_EN COM_OFF(0xC8)
48#define QSERDES_COM_LOCK_CMP_CFG COM_OFF(0xCC)
49#define QSERDES_COM_DEC_START_MODE0 COM_OFF(0xD0)
50#define QSERDES_COM_DEC_START_MODE1 COM_OFF(0xD4)
51#define QSERDES_COM_DIV_FRAC_START1_MODE0 COM_OFF(0xDC)
52#define QSERDES_COM_DIV_FRAC_START2_MODE0 COM_OFF(0xE0)
53#define QSERDES_COM_DIV_FRAC_START3_MODE0 COM_OFF(0xE4)
54#define QSERDES_COM_DIV_FRAC_START1_MODE1 COM_OFF(0xE8)
55#define QSERDES_COM_DIV_FRAC_START2_MODE1 COM_OFF(0xEC)
56#define QSERDES_COM_DIV_FRAC_START3_MODE1 COM_OFF(0xF0)
57#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 COM_OFF(0x108)
58#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 COM_OFF(0x10C)
59#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 COM_OFF(0x110)
60#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 COM_OFF(0x114)
61#define QSERDES_COM_VCO_TUNE_CTRL COM_OFF(0x124)
62#define QSERDES_COM_VCO_TUNE_MAP COM_OFF(0x128)
63#define QSERDES_COM_VCO_TUNE1_MODE0 COM_OFF(0x12C)
64#define QSERDES_COM_VCO_TUNE2_MODE0 COM_OFF(0x130)
65#define QSERDES_COM_VCO_TUNE1_MODE1 COM_OFF(0x134)
66#define QSERDES_COM_VCO_TUNE2_MODE1 COM_OFF(0x138)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]67#define QSERDES_COM_VCO_TUNE_INITVAL1 COM_OFF(0x13C)
68#define QSERDES_COM_VCO_TUNE_INITVAL2 COM_OFF(0x140)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]69#define QSERDES_COM_VCO_TUNE_TIMER1 COM_OFF(0x144)
70#define QSERDES_COM_VCO_TUNE_TIMER2 COM_OFF(0x148)
71#define QSERDES_COM_CLK_SELECT COM_OFF(0x174)
72#define QSERDES_COM_HSCLK_SEL COM_OFF(0x178)
73#define QSERDES_COM_CORECLK_DIV COM_OFF(0x184)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]74#define QSERDES_COM_SW_RESET COM_OFF(0x188)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]75#define QSERDES_COM_CORE_CLK_EN COM_OFF(0x18C)
76#define QSERDES_COM_CMN_CONFIG COM_OFF(0x194)
77#define QSERDES_COM_SVS_MODE_CLK_SEL COM_OFF(0x19C)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]78#define QSERDES_COM_DEBUG_BUS0 COM_OFF(0x1A0)
79#define QSERDES_COM_DEBUG_BUS1 COM_OFF(0x1A4)
80#define QSERDES_COM_DEBUG_BUS2 COM_OFF(0x1A8)
81#define QSERDES_COM_DEBUG_BUS3 COM_OFF(0x1AC)
82#define QSERDES_COM_DEBUG_BUS_SEL COM_OFF(0x1B0)
83#define QSERDES_COM_CMN_MISC2 COM_OFF(0x1B8)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]84#define QSERDES_COM_CORECLK_DIV_MODE1 COM_OFF(0x1BC)
85
86/* UFS PHY registers */
87#define UFS_PHY_PHY_START PHY_OFF(0x00)
88#define UFS_PHY_POWER_DOWN_CONTROL PHY_OFF(0x04)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]89#define UFS_PHY_TX_LARGE_AMP_DRV_LVL PHY_OFF(0x34)
90#define UFS_PHY_TX_SMALL_AMP_DRV_LVL PHY_OFF(0x3C)
91#define UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP PHY_OFF(0xCC)
92#define UFS_PHY_LINECFG_DISABLE PHY_OFF(0x138)
93#define UFS_PHY_RX_SYM_RESYNC_CTRL PHY_OFF(0x13C)
94#define UFS_PHY_RX_SIGDET_CTRL2 PHY_OFF(0x148)
95#define UFS_PHY_RX_PWM_GEAR_BAND PHY_OFF(0x154)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]96#define UFS_PHY_PCS_READY_STATUS PHY_OFF(0x168)
97
98/* UFS PHY TX registers */
99#define QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN TX_OFF(0, 0x68)
100#define QSERDES_TX_LANE_MODE TX_OFF(0, 0x94)
101
102/* UFS PHY RX registers */
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]103#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF RX_OFF(0, 0x30)
104#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER RX_OFF(0, 0x34)
105#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH RX_OFF(0, 0x38)
106#define QSERDES_RX_UCDR_SVS_SO_GAIN RX_OFF(0, 0x3C)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]107#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN RX_OFF(0, 0x40)
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]108#define QSERDES_RX_UCDR_SO_SATURATION_ENABLE RX_OFF(0, 0x48)
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]109#define QSERDES_RX_RX_TERM_BW RX_OFF(0, 0x90)
110#define QSERDES_RX_RX_EQ_GAIN1_LSB RX_OFF(0, 0xC4)
111#define QSERDES_RX_RX_EQ_GAIN1_MSB RX_OFF(0, 0xC8)
112#define QSERDES_RX_RX_EQ_GAIN2_LSB RX_OFF(0, 0xCC)
113#define QSERDES_RX_RX_EQ_GAIN2_MSB RX_OFF(0, 0xD0)
114#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 RX_OFF(0, 0xD8)
115#define QSERDES_RX_SIGDET_CNTRL RX_OFF(0, 0x114)
116#define QSERDES_RX_SIGDET_LVL RX_OFF(0, 0x118)
117#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL RX_OFF(0, 0x11C)
118#define QSERDES_RX_RX_INTERFACE_MODE RX_OFF(0, 0x12C)
119
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]120#define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1)
121
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]122/*
123 * This structure represents the 14nm specific phy.
124 * common_cfg MUST remain the first field in this structure
125 * in case extra fields are added. This way, when calling
126 * get_ufs_qcom_phy() of generic phy, we can extract the
127 * common phy structure (struct ufs_qcom_phy) out of it
128 * regardless of the relevant specific phy.
129 */
130struct ufs_qcom_phy_qmp_14nm {
131 struct ufs_qcom_phy common_cfg;
132};
133
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]134static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_0_0[] = {
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]135 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
136 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]137 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x17),
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]138 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]139 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
140 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
141 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
142 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
143 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
144 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
145 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
146 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x1C),
147 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
148 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
149 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
150 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
151 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
152 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
153 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
154 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
155 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
156 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
157 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
158 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
159 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
160 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
161 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
162 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
163 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x3F),
164 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x01),
165 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
166 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
167 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
168 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
169 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
170 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
171 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
172 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
173 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
174 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
175 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
176 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
177 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
178 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
179 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
180 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
181
182 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
183 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06),
184
185 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
186 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F),
187 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
188 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
189 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
190 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
191 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
192 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
193 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
194 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
195 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
196 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
197 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F),
198 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
199 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x1F),
200 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
201 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
202 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
203 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B),
204 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
205 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12),
206 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06),
207 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
208 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
209
210 /*
211 * UFS_PHY_RX_PWM_GEAR_BAND configuration is changed after the power up
212 * sequence so make sure that this register gets set to power on reset
213 * value. This is required in case power up sequence is initiated after
214 * this register value got changed to value other than power on reset
215 * value.
216 */
217 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x55),
218};
219
220/*
221 * For 2.1.0 revision, SVS mode configuration can be part of PHY power
222 * up sequence itself.
223 */
224static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_1_0[] = {
225 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
226 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
227 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
228 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
229 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]230 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
231 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
232 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x05),
233 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
234 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
235 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
236 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x10),
237 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
238 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
239 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
240 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
241 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
242 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x14),
243 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
244 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
245 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
246 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
247 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
248 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
249 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
250 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
251 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
252 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
253 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
254 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
255 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
256 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
257 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
258 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
259 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
260 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
261 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
262 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
263 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
264 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
265 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
266 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
267 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
268 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
269 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
270 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
271 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
272
273 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]274 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06),
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]275
276 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]277 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F),
278 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
279 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]280 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
281 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
282 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
283 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
284 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]285 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
286 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
287
288 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
289 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F),
290 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15),
291 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
292 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x1F),
293 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
294 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
295 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
296 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B),
297 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
298 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x12),
299 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x06),
300 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
301 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
302};
303
304static struct ufs_qcom_phy_calibration phy_cal_table_rate_A_2_2_0[] = {
305 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_POWER_DOWN_CONTROL, 0x01),
306 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_CONFIG, 0x0e),
307 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
308 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CLK_SELECT, 0x30),
309 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SYS_CLK_CTRL, 0x02),
310 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
311 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TIMER, 0x0a),
312 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_HSCLK_SEL, 0x00),
313 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV, 0x0a),
314 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a),
315 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_EN, 0x01),
316 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
317 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESETSM_CNTRL, 0x20),
318 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CORE_CLK_EN, 0x00),
319 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP_CFG, 0x00),
320 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
321 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
322 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x04),
323 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05),
324 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE0, 0x82),
325 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00),
326 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00),
327 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00),
328 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
329 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
330 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
331 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
332 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
333 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE0, 0x28),
334 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE0, 0x02),
335 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE0, 0xff),
336 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c),
337 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
338 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DEC_START_MODE1, 0x98),
339 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00),
340 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00),
341 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00),
342 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CP_CTRL_MODE1, 0x0b),
343 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_RCTRL_MODE1, 0x16),
344 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_CCTRL_MODE1, 0x28),
345 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80),
346 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00),
347 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6),
348 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE2_MODE1, 0x00),
349 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP1_MODE1, 0x32),
350 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f),
351 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
352
353 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_HIGHZ_TRANSCEIVER_BIAS_DRVR_EN, 0x45),
354 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_TX_LANE_MODE, 0x06),
355
356 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_LVL, 0x24),
357 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_CNTRL, 0x0F),
358 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
359 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E),
360 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B),
361 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_TERM_BW, 0x5B),
362 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF),
363 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F),
364 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF),
365 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F),
366 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D),
367
368 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_PLL_IVCO, 0x0F),
369 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_BG_TRIM, 0x0F),
370 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15),
371 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
372 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_CMN_MISC2, 0x63),
373 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04),
374 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04),
375 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04),
376 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_UCDR_SO_SATURATION_ENABLE, 0x4B),
377 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL1, 0xFF),
378 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00),
379 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6c),
380 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A),
381 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02),
382 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28),
383 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SYM_RESYNC_CTRL, 0x03),
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]384};
385
386static struct ufs_qcom_phy_calibration phy_cal_table_rate_B[] = {
387 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x54),
388};
389
Subhash Jadavanicce6fbc2016-08-11 11:35:26 -0700[diff] [blame]390static struct ufs_qcom_phy_calibration phy_cal_table_rate_B_2_2_0[] = {
391 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_COM_VCO_TUNE_MAP, 0x44),
392};
393
394/*
395 * For 2.0.0 revision, apply this SVS mode configuration after PHY power
396 * up sequence is completed.
397 */
398static struct ufs_qcom_phy_calibration phy_svs_mode_config_2_0_0[] = {
399 UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
400 UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_PWM_GEAR_BAND, 0x15),
401};
402
Yaniv Gardica14ab52015-01-15 16:32:38 +0200[diff] [blame]403#endif