Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * ti_hdmi.h |
| 3 | * |
| 4 | * HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor. |
| 5 | * |
| 6 | * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License version 2 as published by |
| 10 | * the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef _TI_HDMI_H |
| 22 | #define _TI_HDMI_H |
| 23 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 24 | #include <linux/platform_device.h> |
| 25 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 26 | struct hdmi_ip_data; |
| 27 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 28 | enum hdmi_pll_pwr { |
| 29 | HDMI_PLLPWRCMD_ALLOFF = 0, |
| 30 | HDMI_PLLPWRCMD_PLLONLY = 1, |
| 31 | HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2, |
| 32 | HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3 |
| 33 | }; |
| 34 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 35 | enum hdmi_phy_pwr { |
| 36 | HDMI_PHYPWRCMD_OFF = 0, |
| 37 | HDMI_PHYPWRCMD_LDOON = 1, |
| 38 | HDMI_PHYPWRCMD_TXON = 2 |
| 39 | }; |
| 40 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 41 | enum hdmi_core_hdmi_dvi { |
| 42 | HDMI_DVI = 0, |
| 43 | HDMI_HDMI = 1 |
| 44 | }; |
| 45 | |
| 46 | enum hdmi_clk_refsel { |
| 47 | HDMI_REFSEL_PCLK = 0, |
| 48 | HDMI_REFSEL_REF1 = 1, |
| 49 | HDMI_REFSEL_REF2 = 2, |
| 50 | HDMI_REFSEL_SYSCLK = 3 |
| 51 | }; |
| 52 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 53 | enum hdmi_packing_mode { |
| 54 | HDMI_PACK_10b_RGB_YUV444 = 0, |
| 55 | HDMI_PACK_24b_RGB_YUV444_YUV422 = 1, |
| 56 | HDMI_PACK_20b_YUV422 = 2, |
| 57 | HDMI_PACK_ALREADYPACKED = 7 |
| 58 | }; |
| 59 | |
| 60 | enum hdmi_stereo_channels { |
| 61 | HDMI_AUDIO_STEREO_NOCHANNELS = 0, |
| 62 | HDMI_AUDIO_STEREO_ONECHANNEL = 1, |
| 63 | HDMI_AUDIO_STEREO_TWOCHANNELS = 2, |
| 64 | HDMI_AUDIO_STEREO_THREECHANNELS = 3, |
| 65 | HDMI_AUDIO_STEREO_FOURCHANNELS = 4 |
| 66 | }; |
| 67 | |
| 68 | enum hdmi_audio_type { |
| 69 | HDMI_AUDIO_TYPE_LPCM = 0, |
| 70 | HDMI_AUDIO_TYPE_IEC = 1 |
| 71 | }; |
| 72 | |
| 73 | enum hdmi_audio_justify { |
| 74 | HDMI_AUDIO_JUSTIFY_LEFT = 0, |
| 75 | HDMI_AUDIO_JUSTIFY_RIGHT = 1 |
| 76 | }; |
| 77 | |
| 78 | enum hdmi_audio_sample_order { |
| 79 | HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0, |
| 80 | HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1 |
| 81 | }; |
| 82 | |
| 83 | enum hdmi_audio_samples_perword { |
| 84 | HDMI_AUDIO_ONEWORD_ONESAMPLE = 0, |
| 85 | HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1 |
| 86 | }; |
| 87 | |
| 88 | enum hdmi_audio_sample_size { |
| 89 | HDMI_AUDIO_SAMPLE_16BITS = 0, |
| 90 | HDMI_AUDIO_SAMPLE_24BITS = 1 |
| 91 | }; |
| 92 | |
| 93 | enum hdmi_audio_transf_mode { |
| 94 | HDMI_AUDIO_TRANSF_DMA = 0, |
| 95 | HDMI_AUDIO_TRANSF_IRQ = 1 |
| 96 | }; |
| 97 | |
| 98 | enum hdmi_audio_blk_strt_end_sig { |
| 99 | HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0, |
| 100 | HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1 |
| 101 | }; |
| 102 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 103 | struct hdmi_cm { |
| 104 | int code; |
| 105 | int mode; |
| 106 | }; |
| 107 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 108 | struct hdmi_video_format { |
| 109 | enum hdmi_packing_mode packing_mode; |
| 110 | u32 y_res; /* Line per panel */ |
| 111 | u32 x_res; /* pixel per line */ |
| 112 | }; |
| 113 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 114 | struct hdmi_config { |
Archit Taneja | cc937e5 | 2012-06-24 13:08:10 +0530 | [diff] [blame] | 115 | struct omap_video_timings timings; |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 116 | struct hdmi_cm cm; |
| 117 | }; |
| 118 | |
| 119 | /* HDMI PLL structure */ |
| 120 | struct hdmi_pll_info { |
| 121 | u16 regn; |
| 122 | u16 regm; |
| 123 | u32 regmf; |
| 124 | u16 regm2; |
| 125 | u16 regsd; |
| 126 | u16 dcofreq; |
| 127 | enum hdmi_clk_refsel refsel; |
| 128 | }; |
| 129 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 130 | struct hdmi_audio_format { |
| 131 | enum hdmi_stereo_channels stereo_channels; |
| 132 | u8 active_chnnls_msk; |
| 133 | enum hdmi_audio_type type; |
| 134 | enum hdmi_audio_justify justification; |
| 135 | enum hdmi_audio_sample_order sample_order; |
| 136 | enum hdmi_audio_samples_perword samples_per_word; |
| 137 | enum hdmi_audio_sample_size sample_size; |
| 138 | enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end; |
| 139 | }; |
| 140 | |
| 141 | struct hdmi_audio_dma { |
| 142 | u8 transfer_size; |
| 143 | u8 block_size; |
| 144 | enum hdmi_audio_transf_mode mode; |
| 145 | u16 fifo_threshold; |
| 146 | }; |
| 147 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 148 | struct ti_hdmi_ip_ops { |
| 149 | |
| 150 | void (*video_configure)(struct hdmi_ip_data *ip_data); |
| 151 | |
Tomi Valkeinen | 937fce1 | 2011-08-31 11:12:40 +0300 | [diff] [blame] | 152 | int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len); |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 153 | |
Mythri P K | 162874d | 2011-09-22 13:37:45 +0530 | [diff] [blame] | 154 | void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s); |
| 155 | |
Ricardo Neri | 7e151f7 | 2012-03-15 14:08:03 -0600 | [diff] [blame] | 156 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
Axel Castaneda Gonzalez | 3df9fb5 | 2012-05-03 09:00:21 -0500 | [diff] [blame] | 157 | int (*audio_start)(struct hdmi_ip_data *ip_data); |
| 158 | |
| 159 | void (*audio_stop)(struct hdmi_ip_data *ip_data); |
Ricardo Neri | 6ec355d | 2012-03-21 12:38:15 -0600 | [diff] [blame] | 160 | |
| 161 | int (*audio_config)(struct hdmi_ip_data *ip_data, |
| 162 | struct omap_dss_audio *audio); |
Ricardo Neri | d7b6f44 | 2012-11-06 00:19:16 -0600 | [diff] [blame] | 163 | |
| 164 | int (*audio_get_dma_port)(u32 *offset, u32 *size); |
Ricardo Neri | 80a4859 | 2011-11-27 16:09:58 -0600 | [diff] [blame] | 165 | #endif |
| 166 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 167 | }; |
| 168 | |
Mythri P K | da8f14f | 2012-02-08 11:54:19 +0530 | [diff] [blame] | 169 | /* |
| 170 | * Refer to section 8.2 in HDMI 1.3 specification for |
| 171 | * details about infoframe databytes |
| 172 | */ |
| 173 | struct hdmi_core_infoframe_avi { |
| 174 | /* Y0, Y1 rgb,yCbCr */ |
| 175 | u8 db1_format; |
| 176 | /* A0 Active information Present */ |
| 177 | u8 db1_active_info; |
| 178 | /* B0, B1 Bar info data valid */ |
| 179 | u8 db1_bar_info_dv; |
| 180 | /* S0, S1 scan information */ |
| 181 | u8 db1_scan_info; |
| 182 | /* C0, C1 colorimetry */ |
| 183 | u8 db2_colorimetry; |
| 184 | /* M0, M1 Aspect ratio (4:3, 16:9) */ |
| 185 | u8 db2_aspect_ratio; |
| 186 | /* R0...R3 Active format aspect ratio */ |
| 187 | u8 db2_active_fmt_ar; |
| 188 | /* ITC IT content. */ |
| 189 | u8 db3_itc; |
| 190 | /* EC0, EC1, EC2 Extended colorimetry */ |
| 191 | u8 db3_ec; |
| 192 | /* Q1, Q0 Quantization range */ |
| 193 | u8 db3_q_range; |
| 194 | /* SC1, SC0 Non-uniform picture scaling */ |
| 195 | u8 db3_nup_scaling; |
| 196 | /* VIC0..6 Video format identification */ |
| 197 | u8 db4_videocode; |
| 198 | /* PR0..PR3 Pixel repetition factor */ |
| 199 | u8 db5_pixel_repeat; |
| 200 | /* Line number end of top bar */ |
| 201 | u16 db6_7_line_eoftop; |
| 202 | /* Line number start of bottom bar */ |
| 203 | u16 db8_9_line_sofbottom; |
| 204 | /* Pixel number end of left bar */ |
| 205 | u16 db10_11_pixel_eofleft; |
| 206 | /* Pixel number start of right bar */ |
| 207 | u16 db12_13_pixel_sofright; |
| 208 | }; |
| 209 | |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 210 | struct hdmi_wp_data { |
| 211 | void __iomem *base; |
| 212 | }; |
| 213 | |
Archit Taneja | c1577c1 | 2013-10-08 12:55:26 +0530 | [diff] [blame] | 214 | struct hdmi_pll_data { |
| 215 | void __iomem *base; |
| 216 | |
| 217 | struct hdmi_pll_info info; |
| 218 | }; |
| 219 | |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame^] | 220 | struct hdmi_phy_data { |
| 221 | void __iomem *base; |
| 222 | |
| 223 | int irq; |
| 224 | }; |
| 225 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 226 | struct hdmi_ip_data { |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 227 | struct hdmi_wp_data wp; |
Archit Taneja | c1577c1 | 2013-10-08 12:55:26 +0530 | [diff] [blame] | 228 | struct hdmi_pll_data pll; |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame^] | 229 | struct hdmi_phy_data phy; |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 230 | |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 231 | unsigned long core_sys_offset; |
| 232 | unsigned long core_av_offset; |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame^] | 233 | |
Mythri P K | 60634a2 | 2011-09-08 19:06:26 +0530 | [diff] [blame] | 234 | const struct ti_hdmi_ip_ops *ops; |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 235 | struct hdmi_config cfg; |
Mythri P K | da8f14f | 2012-02-08 11:54:19 +0530 | [diff] [blame] | 236 | struct hdmi_core_infoframe_avi avi_cfg; |
Tomi Valkeinen | c49d005 | 2012-01-17 11:09:57 +0200 | [diff] [blame] | 237 | |
| 238 | /* ti_hdmi_4xxx_ip private data. These should be in a separate struct */ |
Jassi Brar | 3a5383a | 2012-06-27 19:34:56 +0530 | [diff] [blame] | 239 | struct mutex lock; |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 240 | }; |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 241 | |
| 242 | /* HDMI wrapper funcs */ |
| 243 | int hdmi_wp_video_start(struct hdmi_wp_data *wp); |
| 244 | void hdmi_wp_video_stop(struct hdmi_wp_data *wp); |
| 245 | void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s); |
| 246 | u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp); |
| 247 | void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus); |
| 248 | void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask); |
| 249 | void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask); |
| 250 | int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val); |
| 251 | int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val); |
| 252 | void hdmi_wp_video_config_format(struct hdmi_wp_data *wp, |
| 253 | struct hdmi_video_format *video_fmt); |
| 254 | void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp, |
| 255 | struct omap_video_timings *timings); |
| 256 | void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp, |
| 257 | struct omap_video_timings *timings); |
| 258 | void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt, |
| 259 | struct omap_video_timings *timings, struct hdmi_config *param); |
| 260 | int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp); |
| 261 | |
Archit Taneja | c1577c1 | 2013-10-08 12:55:26 +0530 | [diff] [blame] | 262 | /* HDMI PLL funcs */ |
| 263 | int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); |
| 264 | void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp); |
| 265 | void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); |
| 266 | void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy); |
| 267 | int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll); |
| 268 | |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame^] | 269 | /* HDMI PHY funcs */ |
| 270 | int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, |
| 271 | struct hdmi_config *cfg); |
| 272 | void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp); |
| 273 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s); |
| 274 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy); |
| 275 | |
Tomi Valkeinen | 937fce1 | 2011-08-31 11:12:40 +0300 | [diff] [blame] | 276 | int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len); |
Mythri P K | 176b578 | 2011-09-08 19:06:25 +0530 | [diff] [blame] | 277 | void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data); |
Mythri P K | 162874d | 2011-09-22 13:37:45 +0530 | [diff] [blame] | 278 | void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s); |
Ricardo Neri | 7e151f7 | 2012-03-15 14:08:03 -0600 | [diff] [blame] | 279 | #if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) |
Ricardo Neri | 3554762 | 2012-03-20 21:02:01 -0600 | [diff] [blame] | 280 | int hdmi_compute_acr(u32 sample_freq, u32 *n, u32 *cts); |
Archit Taneja | f382d9e | 2013-08-06 14:56:55 +0530 | [diff] [blame] | 281 | int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable); |
| 282 | int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable); |
| 283 | void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp, |
| 284 | struct hdmi_audio_format *aud_fmt); |
| 285 | void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp, |
| 286 | struct hdmi_audio_dma *aud_dma); |
Axel Castaneda Gonzalez | 3df9fb5 | 2012-05-03 09:00:21 -0500 | [diff] [blame] | 287 | int ti_hdmi_4xxx_audio_start(struct hdmi_ip_data *ip_data); |
| 288 | void ti_hdmi_4xxx_audio_stop(struct hdmi_ip_data *ip_data); |
Ricardo Neri | 6ec355d | 2012-03-21 12:38:15 -0600 | [diff] [blame] | 289 | int ti_hdmi_4xxx_audio_config(struct hdmi_ip_data *ip_data, |
| 290 | struct omap_dss_audio *audio); |
Ricardo Neri | d7b6f44 | 2012-11-06 00:19:16 -0600 | [diff] [blame] | 291 | int ti_hdmi_4xxx_audio_get_dma_port(u32 *offset, u32 *size); |
Ricardo Neri | 80a4859 | 2011-11-27 16:09:58 -0600 | [diff] [blame] | 292 | #endif |
Mythri P K | 94c5298 | 2011-09-08 19:06:21 +0530 | [diff] [blame] | 293 | #endif |