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Chris Leech0bbd5f42006-05-23 17:35:34 -07001/*
Maciej Sosnowski211a22c2009-02-26 11:05:43 +01002 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
Chris Leech0bbd5f42006-05-23 17:35:34 -07003 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
7 * any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
20 */
21#ifndef IOATDMA_H
22#define IOATDMA_H
23
24#include <linux/dmaengine.h>
Dan Williams584ec222009-07-28 14:32:12 -070025#include "hw.h"
Chris Leech0bbd5f42006-05-23 17:35:34 -070026#include <linux/init.h>
27#include <linux/dmapool.h>
28#include <linux/cache.h>
David S. Miller57c651f2006-05-23 17:39:49 -070029#include <linux/pci_ids.h>
Maciej Sosnowski16a37ac2008-07-22 17:30:57 -070030#include <net/tcp.h>
Chris Leech0bbd5f42006-05-23 17:35:34 -070031
Maciej Sosnowski211a22c2009-02-26 11:05:43 +010032#define IOAT_DMA_VERSION "3.64"
Shannon Nelson5149fd02007-10-18 03:07:13 -070033
Chris Leech0bbd5f42006-05-23 17:35:34 -070034#define IOAT_LOW_COMPLETION_MASK 0xffffffc0
Shannon Nelson7bb67c12007-11-14 16:59:51 -080035#define IOAT_DMA_DCA_ANY_CPU ~0
Maciej Sosnowski09177e82008-07-22 10:07:33 -070036#define IOAT_WATCHDOG_PERIOD (2 * HZ)
Shannon Nelson7bb67c12007-11-14 16:59:51 -080037
Dan Williams1f27adc22009-09-08 17:29:02 -070038#define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, common)
39#define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
Dan Williamsbc3c7022009-07-28 14:33:42 -070040#define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, txd)
41#define to_dev(ioat_chan) (&(ioat_chan)->device->pdev->dev)
Dan Williams1f27adc22009-09-08 17:29:02 -070042
43#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
44
45#define RESET_DELAY msecs_to_jiffies(100)
46#define WATCHDOG_DELAY round_jiffies(msecs_to_jiffies(2000))
47
48/*
49 * workaround for IOAT ver.3.0 null descriptor issue
50 * (channel returns error when size is 0)
51 */
52#define NULL_DESC_BUFFER_SIZE 1
53
Chris Leech0bbd5f42006-05-23 17:35:34 -070054/**
Shannon Nelson8ab89562007-10-16 01:27:39 -070055 * struct ioatdma_device - internal representation of a IOAT device
Chris Leech0bbd5f42006-05-23 17:35:34 -070056 * @pdev: PCI-Express device
57 * @reg_base: MMIO register space base address
58 * @dma_pool: for allocating DMA descriptors
59 * @common: embedded struct dma_device
Shannon Nelson8ab89562007-10-16 01:27:39 -070060 * @version: version of ioatdma device
Shannon Nelson7bb67c12007-11-14 16:59:51 -080061 * @msix_entries: irq handlers
62 * @idx: per channel data
Dan Williamsf2427e22009-07-28 14:42:38 -070063 * @dca: direct cache access context
64 * @intr_quirk: interrupt setup quirk (for ioat_v1 devices)
Dan Williams5cbafa62009-08-26 13:01:44 -070065 * @enumerate_channels: hw version specific channel enumeration
Chris Leech0bbd5f42006-05-23 17:35:34 -070066 */
67
Shannon Nelson8ab89562007-10-16 01:27:39 -070068struct ioatdma_device {
Chris Leech0bbd5f42006-05-23 17:35:34 -070069 struct pci_dev *pdev;
Al Viro47b16532006-10-10 22:45:47 +010070 void __iomem *reg_base;
Chris Leech0bbd5f42006-05-23 17:35:34 -070071 struct pci_pool *dma_pool;
72 struct pci_pool *completion_pool;
Chris Leech0bbd5f42006-05-23 17:35:34 -070073 struct dma_device common;
Shannon Nelson8ab89562007-10-16 01:27:39 -070074 u8 version;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070075 struct delayed_work work;
Shannon Nelson3e037452007-10-16 01:27:40 -070076 struct msix_entry msix_entries[4];
Dan Williamsdcbc8532009-07-28 14:44:50 -070077 struct ioat_chan_common *idx[4];
Dan Williamsf2427e22009-07-28 14:42:38 -070078 struct dca_provider *dca;
79 void (*intr_quirk)(struct ioatdma_device *device);
Dan Williams5cbafa62009-08-26 13:01:44 -070080 int (*enumerate_channels)(struct ioatdma_device *device);
Chris Leech0bbd5f42006-05-23 17:35:34 -070081};
82
Dan Williamsdcbc8532009-07-28 14:44:50 -070083struct ioat_chan_common {
Al Viro47b16532006-10-10 22:45:47 +010084 void __iomem *reg_base;
Chris Leech0bbd5f42006-05-23 17:35:34 -070085
Chris Leech0bbd5f42006-05-23 17:35:34 -070086 unsigned long last_completion;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070087 unsigned long last_completion_time;
Chris Leech0bbd5f42006-05-23 17:35:34 -070088
Chris Leech0bbd5f42006-05-23 17:35:34 -070089 spinlock_t cleanup_lock;
Dan Williamsdcbc8532009-07-28 14:44:50 -070090 dma_cookie_t completed_cookie;
Maciej Sosnowski09177e82008-07-22 10:07:33 -070091 unsigned long watchdog_completion;
92 int watchdog_tcp_cookie;
93 u32 watchdog_last_tcp_cookie;
94 struct delayed_work work;
Chris Leech0bbd5f42006-05-23 17:35:34 -070095
Shannon Nelson8ab89562007-10-16 01:27:39 -070096 struct ioatdma_device *device;
Chris Leech0bbd5f42006-05-23 17:35:34 -070097 struct dma_chan common;
98
99 dma_addr_t completion_addr;
100 union {
101 u64 full; /* HW completion writeback */
102 struct {
103 u32 low;
104 u32 high;
105 };
106 } *completion_virt;
Maciej Sosnowski09177e82008-07-22 10:07:33 -0700107 unsigned long last_compl_desc_addr_hw;
Shannon Nelson3e037452007-10-16 01:27:40 -0700108 struct tasklet_struct cleanup_task;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700109};
110
Dan Williams5cbafa62009-08-26 13:01:44 -0700111
Dan Williamsdcbc8532009-07-28 14:44:50 -0700112/**
113 * struct ioat_dma_chan - internal representation of a DMA channel
114 */
115struct ioat_dma_chan {
116 struct ioat_chan_common base;
117
118 size_t xfercap; /* XFERCAP register value expanded out */
119
120 spinlock_t desc_lock;
121 struct list_head free_desc;
122 struct list_head used_desc;
123
124 int pending;
Dan Williamsdcbc8532009-07-28 14:44:50 -0700125 u16 desccount;
126};
127
128static inline struct ioat_chan_common *to_chan_common(struct dma_chan *c)
129{
130 return container_of(c, struct ioat_chan_common, common);
131}
132
133static inline struct ioat_dma_chan *to_ioat_chan(struct dma_chan *c)
134{
135 struct ioat_chan_common *chan = to_chan_common(c);
136
137 return container_of(chan, struct ioat_dma_chan, base);
138}
139
Dan Williams5cbafa62009-08-26 13:01:44 -0700140/**
141 * ioat_is_complete - poll the status of an ioat transaction
142 * @c: channel handle
143 * @cookie: transaction identifier
144 * @done: if set, updated with last completed transaction
145 * @used: if set, updated with last used transaction
146 */
147static inline enum dma_status
148ioat_is_complete(struct dma_chan *c, dma_cookie_t cookie,
149 dma_cookie_t *done, dma_cookie_t *used)
150{
151 struct ioat_chan_common *chan = to_chan_common(c);
152 dma_cookie_t last_used;
153 dma_cookie_t last_complete;
154
155 last_used = c->cookie;
156 last_complete = chan->completed_cookie;
157 chan->watchdog_tcp_cookie = cookie;
158
159 if (done)
160 *done = last_complete;
161 if (used)
162 *used = last_used;
163
164 return dma_async_is_complete(cookie, last_complete, last_used);
165}
166
Chris Leech0bbd5f42006-05-23 17:35:34 -0700167/* wrapper around hardware descriptor format + additional software fields */
168
169/**
170 * struct ioat_desc_sw - wrapper around hardware descriptor
171 * @hw: hardware DMA descriptor
Dan Williams7405f742007-01-02 11:10:43 -0700172 * @node: this descriptor will either be on the free list,
173 * or attached to a transaction list (async_tx.tx_list)
174 * @tx_cnt: number of descriptors required to complete the transaction
Dan Williamsbc3c7022009-07-28 14:33:42 -0700175 * @txd: the generic software descriptor for all engines
Chris Leech0bbd5f42006-05-23 17:35:34 -0700176 */
Chris Leech0bbd5f42006-05-23 17:35:34 -0700177struct ioat_desc_sw {
178 struct ioat_dma_descriptor *hw;
179 struct list_head node;
Dan Williams7405f742007-01-02 11:10:43 -0700180 int tx_cnt;
Shannon Nelson7f2b2912007-10-18 03:07:14 -0700181 size_t len;
182 dma_addr_t src;
183 dma_addr_t dst;
Dan Williamsbc3c7022009-07-28 14:33:42 -0700184 struct dma_async_tx_descriptor txd;
Chris Leech0bbd5f42006-05-23 17:35:34 -0700185};
186
Dan Williamsf2427e22009-07-28 14:42:38 -0700187static inline void ioat_set_tcp_copy_break(unsigned long copybreak)
Maciej Sosnowski16a37ac2008-07-22 17:30:57 -0700188{
189 #ifdef CONFIG_NET_DMA
Dan Williamsf2427e22009-07-28 14:42:38 -0700190 sysctl_tcp_dma_copybreak = copybreak;
Maciej Sosnowski16a37ac2008-07-22 17:30:57 -0700191 #endif
192}
193
Dan Williams5cbafa62009-08-26 13:01:44 -0700194static inline struct ioat_chan_common *
195ioat_chan_by_index(struct ioatdma_device *device, int index)
196{
197 return device->idx[index];
198}
199
200int ioat_probe(struct ioatdma_device *device);
201int ioat_register(struct ioatdma_device *device);
Dan Williamsf2427e22009-07-28 14:42:38 -0700202int ioat1_dma_probe(struct ioatdma_device *dev, int dca);
Shannon Nelson8ab89562007-10-16 01:27:39 -0700203void ioat_dma_remove(struct ioatdma_device *device);
Shannon Nelson7bb67c12007-11-14 16:59:51 -0800204struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
Dan Williams5cbafa62009-08-26 13:01:44 -0700205unsigned long ioat_get_current_completion(struct ioat_chan_common *chan);
206void ioat_init_channel(struct ioatdma_device *device,
207 struct ioat_chan_common *chan, int idx,
208 work_func_t work_fn, void (*tasklet)(unsigned long),
209 unsigned long tasklet_data);
210void ioat_dma_unmap(struct ioat_chan_common *chan, enum dma_ctrl_flags flags,
211 size_t len, struct ioat_dma_descriptor *hw);
Chris Leech0bbd5f42006-05-23 17:35:34 -0700212#endif /* IOATDMA_H */