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gerrit-public.fairphone.software / kernel / msm-4.9 / 5cbdf276bd9d9cd3cb9616f8253390096c1a237f / . / arch / arm / mach-davinci / da850.c
blob: e6e605bf15161706c64c2ed056c6deb5eaf051b3 [file] [log] [blame]
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]1/*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/clk.h>
17#include <linux/platform_device.h>
18
19#include <asm/mach/map.h>
20
21#include <mach/clock.h>
22#include <mach/psc.h>
23#include <mach/mux.h>
24#include <mach/irqs.h>
25#include <mach/cputype.h>
26#include <mach/common.h>
27#include <mach/time.h>
28#include <mach/da8xx.h>
29
30#include "clock.h"
31#include "mux.h"
32
33#define DA850_PLL1_BASE 0x01e1a000
34#define DA850_TIMER64P2_BASE 0x01f0c000
35#define DA850_TIMER64P3_BASE 0x01f0d000
36
37#define DA850_REF_FREQ 24000000
38
39static struct pll_data pll0_data = {
40 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE,
42 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
43};
44
45static struct clk ref_clk = {
46 .name = "ref_clk",
47 .rate = DA850_REF_FREQ,
48};
49
50static struct clk pll0_clk = {
51 .name = "pll0",
52 .parent = &ref_clk,
53 .pll_data = &pll0_data,
54 .flags = CLK_PLL,
55};
56
57static struct clk pll0_aux_clk = {
58 .name = "pll0_aux_clk",
59 .parent = &pll0_clk,
60 .flags = CLK_PLL | PRE_PLL,
61};
62
63static struct clk pll0_sysclk2 = {
64 .name = "pll0_sysclk2",
65 .parent = &pll0_clk,
66 .flags = CLK_PLL,
67 .div_reg = PLLDIV2,
68};
69
70static struct clk pll0_sysclk3 = {
71 .name = "pll0_sysclk3",
72 .parent = &pll0_clk,
73 .flags = CLK_PLL,
74 .div_reg = PLLDIV3,
75};
76
77static struct clk pll0_sysclk4 = {
78 .name = "pll0_sysclk4",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV4,
82};
83
84static struct clk pll0_sysclk5 = {
85 .name = "pll0_sysclk5",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV5,
89};
90
91static struct clk pll0_sysclk6 = {
92 .name = "pll0_sysclk6",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV6,
96};
97
98static struct clk pll0_sysclk7 = {
99 .name = "pll0_sysclk7",
100 .parent = &pll0_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV7,
103};
104
105static struct pll_data pll1_data = {
106 .num = 2,
107 .phys_base = DA850_PLL1_BASE,
108 .flags = PLL_HAS_POSTDIV,
109};
110
111static struct clk pll1_clk = {
112 .name = "pll1",
113 .parent = &ref_clk,
114 .pll_data = &pll1_data,
115 .flags = CLK_PLL,
116};
117
118static struct clk pll1_aux_clk = {
119 .name = "pll1_aux_clk",
120 .parent = &pll1_clk,
121 .flags = CLK_PLL | PRE_PLL,
122};
123
124static struct clk pll1_sysclk2 = {
125 .name = "pll1_sysclk2",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV2,
129};
130
131static struct clk pll1_sysclk3 = {
132 .name = "pll1_sysclk3",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL,
135 .div_reg = PLLDIV3,
136};
137
138static struct clk pll1_sysclk4 = {
139 .name = "pll1_sysclk4",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL,
142 .div_reg = PLLDIV4,
143};
144
145static struct clk pll1_sysclk5 = {
146 .name = "pll1_sysclk5",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL,
149 .div_reg = PLLDIV5,
150};
151
152static struct clk pll1_sysclk6 = {
153 .name = "pll0_sysclk6",
154 .parent = &pll0_clk,
155 .flags = CLK_PLL,
156 .div_reg = PLLDIV6,
157};
158
159static struct clk pll1_sysclk7 = {
160 .name = "pll1_sysclk7",
161 .parent = &pll1_clk,
162 .flags = CLK_PLL,
163 .div_reg = PLLDIV7,
164};
165
166static struct clk i2c0_clk = {
167 .name = "i2c0",
168 .parent = &pll0_aux_clk,
169};
170
171static struct clk timerp64_0_clk = {
172 .name = "timer0",
173 .parent = &pll0_aux_clk,
174};
175
176static struct clk timerp64_1_clk = {
177 .name = "timer1",
178 .parent = &pll0_aux_clk,
179};
180
181static struct clk arm_rom_clk = {
182 .name = "arm_rom",
183 .parent = &pll0_sysclk2,
184 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
185 .flags = ALWAYS_ENABLED,
186};
187
188static struct clk tpcc0_clk = {
189 .name = "tpcc0",
190 .parent = &pll0_sysclk2,
191 .lpsc = DA8XX_LPSC0_TPCC,
192 .flags = ALWAYS_ENABLED | CLK_PSC,
193};
194
195static struct clk tptc0_clk = {
196 .name = "tptc0",
197 .parent = &pll0_sysclk2,
198 .lpsc = DA8XX_LPSC0_TPTC0,
199 .flags = ALWAYS_ENABLED,
200};
201
202static struct clk tptc1_clk = {
203 .name = "tptc1",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_TPTC1,
206 .flags = ALWAYS_ENABLED,
207};
208
209static struct clk tpcc1_clk = {
210 .name = "tpcc1",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA850_LPSC1_TPCC1,
213 .flags = CLK_PSC | ALWAYS_ENABLED,
214 .psc_ctlr = 1,
215};
216
217static struct clk tptc2_clk = {
218 .name = "tptc2",
219 .parent = &pll0_sysclk2,
220 .lpsc = DA850_LPSC1_TPTC2,
221 .flags = ALWAYS_ENABLED,
222 .psc_ctlr = 1,
223};
224
225static struct clk uart0_clk = {
226 .name = "uart0",
227 .parent = &pll0_sysclk2,
228 .lpsc = DA8XX_LPSC0_UART0,
229};
230
231static struct clk uart1_clk = {
232 .name = "uart1",
233 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1,
235 .psc_ctlr = 1,
236};
237
238static struct clk uart2_clk = {
239 .name = "uart2",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2,
242 .psc_ctlr = 1,
243};
244
245static struct clk aintc_clk = {
246 .name = "aintc",
247 .parent = &pll0_sysclk4,
248 .lpsc = DA8XX_LPSC0_AINTC,
249 .flags = ALWAYS_ENABLED,
250};
251
252static struct clk gpio_clk = {
253 .name = "gpio",
254 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC1_GPIO,
256 .psc_ctlr = 1,
257};
258
259static struct clk i2c1_clk = {
260 .name = "i2c1",
261 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_I2C,
263 .psc_ctlr = 1,
264};
265
266static struct clk emif3_clk = {
267 .name = "emif3",
268 .parent = &pll0_sysclk5,
269 .lpsc = DA8XX_LPSC1_EMIF3C,
270 .flags = ALWAYS_ENABLED,
271 .psc_ctlr = 1,
272};
273
274static struct clk arm_clk = {
275 .name = "arm",
276 .parent = &pll0_sysclk6,
277 .lpsc = DA8XX_LPSC0_ARM,
278 .flags = ALWAYS_ENABLED,
279};
280
281static struct clk rmii_clk = {
282 .name = "rmii",
283 .parent = &pll0_sysclk7,
284};
285
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]286static struct clk emac_clk = {
287 .name = "emac",
288 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_CPGMAC,
Sudhakar Rajashekhara53ca5c92009-08-11 11:10:50 -0400[diff] [blame]290 .psc_ctlr = 1,
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]291};
292
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]293static struct clk mcasp_clk = {
294 .name = "mcasp",
295 .parent = &pll0_sysclk2,
296 .lpsc = DA8XX_LPSC1_McASP0,
297 .psc_ctlr = 1,
298};
299
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame^]300static struct clk lcdc_clk = {
301 .name = "lcdc",
302 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_LCDC,
304 .psc_ctlr = 1,
305};
306
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]307static struct davinci_clk da850_clks[] = {
308 CLK(NULL, "ref", &ref_clk),
309 CLK(NULL, "pll0", &pll0_clk),
310 CLK(NULL, "pll0_aux", &pll0_aux_clk),
311 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
312 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
313 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
314 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
315 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
316 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
317 CLK(NULL, "pll1", &pll1_clk),
318 CLK(NULL, "pll1_aux", &pll1_aux_clk),
319 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
320 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
321 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
322 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
323 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
324 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
325 CLK("i2c_davinci.1", NULL, &i2c0_clk),
326 CLK(NULL, "timer0", &timerp64_0_clk),
327 CLK("watchdog", NULL, &timerp64_1_clk),
328 CLK(NULL, "arm_rom", &arm_rom_clk),
329 CLK(NULL, "tpcc0", &tpcc0_clk),
330 CLK(NULL, "tptc0", &tptc0_clk),
331 CLK(NULL, "tptc1", &tptc1_clk),
332 CLK(NULL, "tpcc1", &tpcc1_clk),
333 CLK(NULL, "tptc2", &tptc2_clk),
334 CLK(NULL, "uart0", &uart0_clk),
335 CLK(NULL, "uart1", &uart1_clk),
336 CLK(NULL, "uart2", &uart2_clk),
337 CLK(NULL, "aintc", &aintc_clk),
338 CLK(NULL, "gpio", &gpio_clk),
339 CLK("i2c_davinci.2", NULL, &i2c1_clk),
340 CLK(NULL, "emif3", &emif3_clk),
341 CLK(NULL, "arm", &arm_clk),
342 CLK(NULL, "rmii", &rmii_clk),
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]343 CLK("davinci_emac.1", NULL, &emac_clk),
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]344 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame^]345 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]346 CLK(NULL, NULL, NULL),
347};
348
349/*
350 * Device specific mux setup
351 *
352 * soc description mux mode mode mux dbg
353 * reg offset mask mode
354 */
355static const struct mux_config da850_pins[] = {
356#ifdef CONFIG_DAVINCI_MUX
357 /* UART0 function */
358 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
359 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
360 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
361 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
362 /* UART1 function */
363 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
364 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
365 /* UART2 function */
366 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
367 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
368 /* I2C1 function */
369 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
370 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
371 /* I2C0 function */
372 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
373 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]374 /* EMAC function */
375 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
376 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
377 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
378 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
379 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
380 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
381 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
382 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
383 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
384 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
385 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
386 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
387 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
388 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
389 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
Sudhakar Rajashekhara53ca5c92009-08-11 11:10:50 -0400[diff] [blame]390 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
391 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]392 /* McASP function */
393 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
394 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
395 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
396 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
397 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
398 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
399 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
400 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
401 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
402 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
403 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
404 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
405 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
406 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
407 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
408 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
409 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
410 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
411 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
412 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
413 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
414 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
415 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame^]416 /* LCD function */
417 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
418 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
419 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
420 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
421 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
422 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
423 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
424 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
425 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
426 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
427 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
428 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
429 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
430 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
431 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
432 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
433 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
434 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
435 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
436 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
437 /* GPIO function */
438 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
439 MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]440#endif
441};
442
443const short da850_uart0_pins[] __initdata = {
444 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
445 -1
446};
447
448const short da850_uart1_pins[] __initdata = {
449 DA850_UART1_RXD, DA850_UART1_TXD,
450 -1
451};
452
453const short da850_uart2_pins[] __initdata = {
454 DA850_UART2_RXD, DA850_UART2_TXD,
455 -1
456};
457
458const short da850_i2c0_pins[] __initdata = {
459 DA850_I2C0_SDA, DA850_I2C0_SCL,
460 -1
461};
462
463const short da850_i2c1_pins[] __initdata = {
464 DA850_I2C1_SCL, DA850_I2C1_SDA,
465 -1
466};
467
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]468const short da850_cpgmac_pins[] __initdata = {
469 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
470 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
471 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
Sudhakar Rajashekhara53ca5c92009-08-11 11:10:50 -0400[diff] [blame]472 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
473 DA850_MDIO_D,
Sudhakar Rajashekhara5a4b1312009-07-17 04:47:10 -0400[diff] [blame]474 -1
475};
476
Chaithrika U S491214e2009-08-11 17:03:25 -0400[diff] [blame]477const short da850_mcasp_pins[] __initdata = {
478 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
479 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
480 DA850_AXR_11, DA850_AXR_12,
481 -1
482};
483
Sudhakar Rajashekhara5cbdf272009-08-13 14:33:14 -0400[diff] [blame^]484const short da850_lcdcntl_pins[] __initdata = {
485 DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4,
486 DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8,
487 DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12,
488 DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK,
489 DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15,
490 DA850_GPIO8_10,
491 -1
492};
493
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]494/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
495static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
496 [IRQ_DA8XX_COMMTX] = 7,
497 [IRQ_DA8XX_COMMRX] = 7,
498 [IRQ_DA8XX_NINT] = 7,
499 [IRQ_DA8XX_EVTOUT0] = 7,
500 [IRQ_DA8XX_EVTOUT1] = 7,
501 [IRQ_DA8XX_EVTOUT2] = 7,
502 [IRQ_DA8XX_EVTOUT3] = 7,
503 [IRQ_DA8XX_EVTOUT4] = 7,
504 [IRQ_DA8XX_EVTOUT5] = 7,
505 [IRQ_DA8XX_EVTOUT6] = 7,
506 [IRQ_DA8XX_EVTOUT6] = 7,
507 [IRQ_DA8XX_EVTOUT7] = 7,
508 [IRQ_DA8XX_CCINT0] = 7,
509 [IRQ_DA8XX_CCERRINT] = 7,
510 [IRQ_DA8XX_TCERRINT0] = 7,
511 [IRQ_DA8XX_AEMIFINT] = 7,
512 [IRQ_DA8XX_I2CINT0] = 7,
513 [IRQ_DA8XX_MMCSDINT0] = 7,
514 [IRQ_DA8XX_MMCSDINT1] = 7,
515 [IRQ_DA8XX_ALLINT0] = 7,
516 [IRQ_DA8XX_RTC] = 7,
517 [IRQ_DA8XX_SPINT0] = 7,
518 [IRQ_DA8XX_TINT12_0] = 7,
519 [IRQ_DA8XX_TINT34_0] = 7,
520 [IRQ_DA8XX_TINT12_1] = 7,
521 [IRQ_DA8XX_TINT34_1] = 7,
522 [IRQ_DA8XX_UARTINT0] = 7,
523 [IRQ_DA8XX_KEYMGRINT] = 7,
524 [IRQ_DA8XX_SECINT] = 7,
525 [IRQ_DA8XX_SECKEYERR] = 7,
526 [IRQ_DA850_MPUADDRERR0] = 7,
527 [IRQ_DA850_MPUPROTERR0] = 7,
528 [IRQ_DA850_IOPUADDRERR0] = 7,
529 [IRQ_DA850_IOPUPROTERR0] = 7,
530 [IRQ_DA850_IOPUADDRERR1] = 7,
531 [IRQ_DA850_IOPUPROTERR1] = 7,
532 [IRQ_DA850_IOPUADDRERR2] = 7,
533 [IRQ_DA850_IOPUPROTERR2] = 7,
534 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
535 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
536 [IRQ_DA850_MPUADDRERR1] = 7,
537 [IRQ_DA850_MPUPROTERR1] = 7,
538 [IRQ_DA850_IOPUADDRERR3] = 7,
539 [IRQ_DA850_IOPUPROTERR3] = 7,
540 [IRQ_DA850_IOPUADDRERR4] = 7,
541 [IRQ_DA850_IOPUPROTERR4] = 7,
542 [IRQ_DA850_IOPUADDRERR5] = 7,
543 [IRQ_DA850_IOPUPROTERR5] = 7,
544 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
545 [IRQ_DA8XX_CHIPINT0] = 7,
546 [IRQ_DA8XX_CHIPINT1] = 7,
547 [IRQ_DA8XX_CHIPINT2] = 7,
548 [IRQ_DA8XX_CHIPINT3] = 7,
549 [IRQ_DA8XX_TCERRINT1] = 7,
550 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
551 [IRQ_DA8XX_C0_RX_PULSE] = 7,
552 [IRQ_DA8XX_C0_TX_PULSE] = 7,
553 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
554 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
555 [IRQ_DA8XX_C1_RX_PULSE] = 7,
556 [IRQ_DA8XX_C1_TX_PULSE] = 7,
557 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
558 [IRQ_DA8XX_MEMERR] = 7,
559 [IRQ_DA8XX_GPIO0] = 7,
560 [IRQ_DA8XX_GPIO1] = 7,
561 [IRQ_DA8XX_GPIO2] = 7,
562 [IRQ_DA8XX_GPIO3] = 7,
563 [IRQ_DA8XX_GPIO4] = 7,
564 [IRQ_DA8XX_GPIO5] = 7,
565 [IRQ_DA8XX_GPIO6] = 7,
566 [IRQ_DA8XX_GPIO7] = 7,
567 [IRQ_DA8XX_GPIO8] = 7,
568 [IRQ_DA8XX_I2CINT1] = 7,
569 [IRQ_DA8XX_LCDINT] = 7,
570 [IRQ_DA8XX_UARTINT1] = 7,
571 [IRQ_DA8XX_MCASPINT] = 7,
572 [IRQ_DA8XX_ALLINT1] = 7,
573 [IRQ_DA8XX_SPINT1] = 7,
574 [IRQ_DA8XX_UHPI_INT1] = 7,
575 [IRQ_DA8XX_USB_INT] = 7,
576 [IRQ_DA8XX_IRQN] = 7,
577 [IRQ_DA8XX_RWAKEUP] = 7,
578 [IRQ_DA8XX_UARTINT2] = 7,
579 [IRQ_DA8XX_DFTSSINT] = 7,
580 [IRQ_DA8XX_EHRPWM0] = 7,
581 [IRQ_DA8XX_EHRPWM0TZ] = 7,
582 [IRQ_DA8XX_EHRPWM1] = 7,
583 [IRQ_DA8XX_EHRPWM1TZ] = 7,
584 [IRQ_DA850_SATAINT] = 7,
585 [IRQ_DA850_TINT12_2] = 7,
586 [IRQ_DA850_TINT34_2] = 7,
587 [IRQ_DA850_TINTALL_2] = 7,
588 [IRQ_DA8XX_ECAP0] = 7,
589 [IRQ_DA8XX_ECAP1] = 7,
590 [IRQ_DA8XX_ECAP2] = 7,
591 [IRQ_DA850_MMCSDINT0_1] = 7,
592 [IRQ_DA850_MMCSDINT1_1] = 7,
593 [IRQ_DA850_T12CMPINT0_2] = 7,
594 [IRQ_DA850_T12CMPINT1_2] = 7,
595 [IRQ_DA850_T12CMPINT2_2] = 7,
596 [IRQ_DA850_T12CMPINT3_2] = 7,
597 [IRQ_DA850_T12CMPINT4_2] = 7,
598 [IRQ_DA850_T12CMPINT5_2] = 7,
599 [IRQ_DA850_T12CMPINT6_2] = 7,
600 [IRQ_DA850_T12CMPINT7_2] = 7,
601 [IRQ_DA850_T12CMPINT0_3] = 7,
602 [IRQ_DA850_T12CMPINT1_3] = 7,
603 [IRQ_DA850_T12CMPINT2_3] = 7,
604 [IRQ_DA850_T12CMPINT3_3] = 7,
605 [IRQ_DA850_T12CMPINT4_3] = 7,
606 [IRQ_DA850_T12CMPINT5_3] = 7,
607 [IRQ_DA850_T12CMPINT6_3] = 7,
608 [IRQ_DA850_T12CMPINT7_3] = 7,
609 [IRQ_DA850_RPIINT] = 7,
610 [IRQ_DA850_VPIFINT] = 7,
611 [IRQ_DA850_CCINT1] = 7,
612 [IRQ_DA850_CCERRINT1] = 7,
613 [IRQ_DA850_TCERRINT2] = 7,
614 [IRQ_DA850_TINT12_3] = 7,
615 [IRQ_DA850_TINT34_3] = 7,
616 [IRQ_DA850_TINTALL_3] = 7,
617 [IRQ_DA850_MCBSP0RINT] = 7,
618 [IRQ_DA850_MCBSP0XINT] = 7,
619 [IRQ_DA850_MCBSP1RINT] = 7,
620 [IRQ_DA850_MCBSP1XINT] = 7,
621 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
622};
623
624static struct map_desc da850_io_desc[] = {
625 {
626 .virtual = IO_VIRT,
627 .pfn = __phys_to_pfn(IO_PHYS),
628 .length = IO_SIZE,
629 .type = MT_DEVICE
630 },
631 {
632 .virtual = DA8XX_CP_INTC_VIRT,
633 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
634 .length = DA8XX_CP_INTC_SIZE,
635 .type = MT_DEVICE
636 },
637};
638
639static void __iomem *da850_psc_bases[] = {
640 IO_ADDRESS(DA8XX_PSC0_BASE),
641 IO_ADDRESS(DA8XX_PSC1_BASE),
642};
643
644/* Contents of JTAG ID register used to identify exact cpu type */
645static struct davinci_id da850_ids[] = {
646 {
647 .variant = 0x0,
648 .part_no = 0xb7d1,
649 .manufacturer = 0x017, /* 0x02f >> 1 */
650 .cpu_id = DAVINCI_CPU_ID_DA850,
651 .name = "da850/omap-l138",
652 },
653};
654
655static struct davinci_timer_instance da850_timer_instance[4] = {
656 {
657 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
658 .bottom_irq = IRQ_DA8XX_TINT12_0,
659 .top_irq = IRQ_DA8XX_TINT34_0,
660 },
661 {
662 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
663 .bottom_irq = IRQ_DA8XX_TINT12_1,
664 .top_irq = IRQ_DA8XX_TINT34_1,
665 },
666 {
667 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
668 .bottom_irq = IRQ_DA850_TINT12_2,
669 .top_irq = IRQ_DA850_TINT34_2,
670 },
671 {
672 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
673 .bottom_irq = IRQ_DA850_TINT12_3,
674 .top_irq = IRQ_DA850_TINT34_3,
675 },
676};
677
678/*
679 * T0_BOT: Timer 0, bottom : Used for clock_event
680 * T0_TOP: Timer 0, top : Used for clocksource
681 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
682 */
683static struct davinci_timer_info da850_timer_info = {
684 .timers = da850_timer_instance,
685 .clockevent_id = T0_BOT,
686 .clocksource_id = T0_TOP,
687};
688
689static struct davinci_soc_info davinci_soc_info_da850 = {
690 .io_desc = da850_io_desc,
691 .io_desc_num = ARRAY_SIZE(da850_io_desc),
692 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
693 .ids = da850_ids,
694 .ids_num = ARRAY_SIZE(da850_ids),
695 .cpu_clks = da850_clks,
696 .psc_bases = da850_psc_bases,
697 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
698 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
699 .pinmux_pins = da850_pins,
700 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
701 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
702 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
703 .intc_irq_prios = da850_default_priorities,
704 .intc_irq_num = DA850_N_CP_INTC_IRQ,
705 .timer_info = &da850_timer_info,
706 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
Sudhakar Rajashekhara5a8d5442009-08-11 16:14:21 -0400[diff] [blame]707 .gpio_num = 144,
Sudhakar Rajashekharae1a8d7e2009-07-16 06:41:54 -0400[diff] [blame]708 .gpio_irq = IRQ_DA8XX_GPIO0,
709 .serial_dev = &da8xx_serial_device,
710 .emac_pdata = &da8xx_emac_pdata,
711};
712
713void __init da850_init(void)
714{
715 davinci_common_init(&davinci_soc_info_da850);
716}