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Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -05001/*
2 * CXL Flash Device Driver
3 *
4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 *
7 * Copyright (C) 2015 IBM Corporation
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#ifndef _CXLFLASH_COMMON_H
16#define _CXLFLASH_COMMON_H
17
18#include <linux/list.h>
19#include <linux/types.h>
20#include <scsi/scsi.h>
21#include <scsi/scsi_device.h>
22
23
24#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
25
26#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
27#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
28#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
29 max_sectors
30 in units of
31 512 byte
32 sectors
33 */
34
35#define NUM_RRQ_ENTRY 16 /* for master issued cmds */
36#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
37
38/* AFU command retry limit */
39#define MC_RETRY_CNT 5 /* sufficient for SCSI check and
40 certain AFU errors */
41
42/* Command management definitions */
43#define CXLFLASH_NUM_CMDS (2 * CXLFLASH_MAX_CMDS) /* Must be a pow2 for
44 alignment and more
45 efficient array
46 index derivation
47 */
48
49#define CXLFLASH_MAX_CMDS 16
50#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
51
52
53static inline void check_sizes(void)
54{
55 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_CMDS);
56}
57
58/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
59#define CMD_BUFSIZE SIZE_4K
60
61/* flags in IOA status area for host use */
62#define B_DONE 0x01
63#define B_ERROR 0x02 /* set with B_DONE */
64#define B_TIMEOUT 0x04 /* set with B_DONE & B_ERROR */
65
66enum cxlflash_lr_state {
67 LINK_RESET_INVALID,
68 LINK_RESET_REQUIRED,
69 LINK_RESET_COMPLETE
70};
71
72enum cxlflash_init_state {
73 INIT_STATE_NONE,
74 INIT_STATE_PCI,
75 INIT_STATE_AFU,
76 INIT_STATE_SCSI
77};
78
Matthew R. Ochs5cdac812015-08-13 21:47:34 -050079enum cxlflash_state {
80 STATE_NORMAL, /* Normal running state, everything good */
81 STATE_LIMBO, /* Limbo running state, trying to reset/recover */
82 STATE_FAILTERM /* Failed/terminating state, error out users/threads */
83};
84
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -050085/*
86 * Each context has its own set of resource handles that is visible
87 * only from that context.
88 */
89
90struct cxlflash_cfg {
91 struct afu *afu;
92 struct cxl_context *mcctx;
93
94 struct pci_dev *dev;
95 struct pci_device_id *dev_id;
96 struct Scsi_Host *host;
97
98 ulong cxlflash_regs_pci;
99
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500100 struct work_struct work_q;
101 enum cxlflash_init_state init_state;
102 enum cxlflash_lr_state lr_state;
103 int lr_port;
104
105 struct cxl_afu *cxl_afu;
106
107 struct pci_pool *cxlflash_cmd_pool;
108 struct pci_dev *parent_dev;
109
110 wait_queue_head_t tmf_waitq;
111 bool tmf_active;
Matthew R. Ochs5cdac812015-08-13 21:47:34 -0500112 wait_queue_head_t limbo_waitq;
113 enum cxlflash_state state;
Matthew R. Ochsc21e0bb2015-06-09 17:15:52 -0500114};
115
116struct afu_cmd {
117 struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
118 struct sisl_ioasa sa; /* IOASA must follow IOARCB */
119 spinlock_t slock;
120 struct completion cevent;
121 char *buf; /* per command buffer */
122 struct afu *parent;
123 int slot;
124 atomic_t free;
125
126 u8 cmd_tmf:1;
127
128 /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
129 * However for performance reasons the IOARCB/IOASA should be
130 * cache line aligned.
131 */
132} __aligned(cache_line_size());
133
134struct afu {
135 /* Stuff requiring alignment go first. */
136
137 u64 rrq_entry[NUM_RRQ_ENTRY]; /* 128B RRQ */
138 /*
139 * Command & data for AFU commands.
140 */
141 struct afu_cmd cmd[CXLFLASH_NUM_CMDS];
142
143 /* Beware of alignment till here. Preferably introduce new
144 * fields after this point
145 */
146
147 /* AFU HW */
148 struct cxl_ioctl_start_work work;
149 struct cxlflash_afu_map *afu_map; /* entire MMIO map */
150 struct sisl_host_map *host_map; /* MC host map */
151 struct sisl_ctrl_map *ctrl_map; /* MC control map */
152
153 ctx_hndl_t ctx_hndl; /* master's context handle */
154 u64 *hrrq_start;
155 u64 *hrrq_end;
156 u64 *hrrq_curr;
157 bool toggle;
158 bool read_room;
159 atomic64_t room;
160 u64 hb;
161 u32 cmd_couts; /* Number of command checkouts */
162 u32 internal_lun; /* User-desired LUN mode for this AFU */
163
164 char version[8];
165 u64 interface_version;
166
167 struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
168
169};
170
171static inline u64 lun_to_lunid(u64 lun)
172{
173 u64 lun_id;
174
175 int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
176 return swab64(lun_id);
177}
178
179int cxlflash_send_cmd(struct afu *, struct afu_cmd *);
180void cxlflash_wait_resp(struct afu *, struct afu_cmd *);
181int cxlflash_afu_reset(struct cxlflash_cfg *);
182struct afu_cmd *cxlflash_cmd_checkout(struct afu *);
183void cxlflash_cmd_checkin(struct afu_cmd *);
184int cxlflash_afu_sync(struct afu *, ctx_hndl_t, res_hndl_t, u8);
185#endif /* ifndef _CXLFLASH_COMMON_H */