Catalin Marinas | 53631b5 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_FP_H |
| 17 | #define __ASM_FP_H |
| 18 | |
| 19 | #include <asm/ptrace.h> |
| 20 | |
| 21 | #ifndef __ASSEMBLY__ |
| 22 | |
| 23 | /* |
| 24 | * FP/SIMD storage area has: |
| 25 | * - FPSR and FPCR |
| 26 | * - 32 128-bit data registers |
| 27 | * |
Will Deacon | 6ba1bc8 | 2012-11-06 19:28:48 +0000 | [diff] [blame] | 28 | * Note that user_fpsimd forms a prefix of this structure, which is |
| 29 | * relied upon in the ptrace FP/SIMD accessors. |
Catalin Marinas | 53631b5 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 30 | */ |
| 31 | struct fpsimd_state { |
| 32 | union { |
| 33 | struct user_fpsimd_state user_fpsimd; |
| 34 | struct { |
| 35 | __uint128_t vregs[32]; |
| 36 | u32 fpsr; |
| 37 | u32 fpcr; |
| 38 | }; |
| 39 | }; |
Ard Biesheuvel | 005f78c | 2014-05-08 11:20:23 +0200 | [diff] [blame] | 40 | /* the id of the last cpu to have restored this state */ |
| 41 | unsigned int cpu; |
Catalin Marinas | 53631b5 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 42 | }; |
| 43 | |
Ard Biesheuvel | 190f1ca | 2014-02-24 15:26:29 +0100 | [diff] [blame] | 44 | /* |
| 45 | * Struct for stacking the bottom 'n' FP/SIMD registers. |
| 46 | */ |
| 47 | struct fpsimd_partial_state { |
| 48 | u32 fpsr; |
| 49 | u32 fpcr; |
| 50 | u32 num_regs; |
| 51 | __uint128_t vregs[32]; |
| 52 | }; |
| 53 | |
| 54 | |
Catalin Marinas | 53631b5 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 55 | #if defined(__KERNEL__) && defined(CONFIG_COMPAT) |
| 56 | /* Masks for extracting the FPSR and FPCR from the FPSCR */ |
| 57 | #define VFP_FPSCR_STAT_MASK 0xf800009f |
| 58 | #define VFP_FPSCR_CTRL_MASK 0x07f79f00 |
| 59 | /* |
| 60 | * The VFP state has 32x64-bit registers and a single 32-bit |
| 61 | * control/status register. |
| 62 | */ |
| 63 | #define VFP_STATE_SIZE ((32 * 8) + 4) |
| 64 | #endif |
| 65 | |
| 66 | struct task_struct; |
| 67 | |
| 68 | extern void fpsimd_save_state(struct fpsimd_state *state); |
| 69 | extern void fpsimd_load_state(struct fpsimd_state *state); |
| 70 | |
| 71 | extern void fpsimd_thread_switch(struct task_struct *next); |
| 72 | extern void fpsimd_flush_thread(void); |
| 73 | |
Ard Biesheuvel | c51f926 | 2014-02-24 15:26:27 +0100 | [diff] [blame] | 74 | extern void fpsimd_preserve_current_state(void); |
Ard Biesheuvel | 005f78c | 2014-05-08 11:20:23 +0200 | [diff] [blame] | 75 | extern void fpsimd_restore_current_state(void); |
Ard Biesheuvel | c51f926 | 2014-02-24 15:26:27 +0100 | [diff] [blame] | 76 | extern void fpsimd_update_current_state(struct fpsimd_state *state); |
| 77 | |
Ard Biesheuvel | 005f78c | 2014-05-08 11:20:23 +0200 | [diff] [blame] | 78 | extern void fpsimd_flush_task_state(struct task_struct *target); |
| 79 | |
Ard Biesheuvel | 190f1ca | 2014-02-24 15:26:29 +0100 | [diff] [blame] | 80 | extern void fpsimd_save_partial_state(struct fpsimd_partial_state *state, |
| 81 | u32 num_regs); |
| 82 | extern void fpsimd_load_partial_state(struct fpsimd_partial_state *state); |
| 83 | |
Catalin Marinas | 53631b5 | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 84 | #endif |
| 85 | |
| 86 | #endif |