| Luciano Coelho | 5d4a9fa | 2012-05-10 12:13:10 +0300 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of wlcore |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Instruments Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * version 2 as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, but |
| 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 13 | * General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 18 | * 02110-1301 USA |
| 19 | * |
| 20 | */ |
| 21 | |
| 22 | #ifndef __REG_H__ |
| 23 | #define __REG_H__ |
| 24 | |
| 25 | #define WL18XX_REGISTERS_BASE 0x00800000 |
| 26 | #define WL18XX_CODE_BASE 0x00000000 |
| 27 | #define WL18XX_DATA_BASE 0x00400000 |
| 28 | #define WL18XX_DOUBLE_BUFFER_BASE 0x00600000 |
| 29 | #define WL18XX_MCU_KEY_SEARCH_BASE 0x00700000 |
| 30 | #define WL18XX_PHY_BASE 0x00900000 |
| 31 | #define WL18XX_TOP_OCP_BASE 0x00A00000 |
| 32 | #define WL18XX_PACKET_RAM_BASE 0x00B00000 |
| 33 | #define WL18XX_HOST_BASE 0x00C00000 |
| 34 | |
| 35 | #define WL18XX_REGISTERS_DOWN_SIZE 0x0000B000 |
| 36 | |
| 37 | #define WL18XX_REG_BOOT_PART_START 0x00802000 |
| 38 | #define WL18XX_REG_BOOT_PART_SIZE 0x00014578 |
| 39 | |
| 40 | #define WL18XX_PHY_INIT_MEM_ADDR 0x80926000 |
| 41 | |
| 42 | #define WL18XX_SDIO_WSPI_BASE (WL18XX_REGISTERS_BASE) |
| 43 | #define WL18XX_REG_CONFIG_BASE (WL18XX_REGISTERS_BASE + 0x02000) |
| 44 | #define WL18XX_WGCM_REGS_BASE (WL18XX_REGISTERS_BASE + 0x03000) |
| 45 | #define WL18XX_ENC_BASE (WL18XX_REGISTERS_BASE + 0x04000) |
| 46 | #define WL18XX_INTERRUPT_BASE (WL18XX_REGISTERS_BASE + 0x05000) |
| 47 | #define WL18XX_UART_BASE (WL18XX_REGISTERS_BASE + 0x06000) |
| 48 | #define WL18XX_WELP_BASE (WL18XX_REGISTERS_BASE + 0x07000) |
| 49 | #define WL18XX_TCP_CKSM_BASE (WL18XX_REGISTERS_BASE + 0x08000) |
| 50 | #define WL18XX_FIFO_BASE (WL18XX_REGISTERS_BASE + 0x09000) |
| 51 | #define WL18XX_OCP_BRIDGE_BASE (WL18XX_REGISTERS_BASE + 0x0A000) |
| 52 | #define WL18XX_PMAC_RX_BASE (WL18XX_REGISTERS_BASE + 0x14800) |
| 53 | #define WL18XX_PMAC_ACM_BASE (WL18XX_REGISTERS_BASE + 0x14C00) |
| 54 | #define WL18XX_PMAC_TX_BASE (WL18XX_REGISTERS_BASE + 0x15000) |
| 55 | #define WL18XX_PMAC_CSR_BASE (WL18XX_REGISTERS_BASE + 0x15400) |
| 56 | |
| 57 | #define WL18XX_REG_ECPU_CONTROL (WL18XX_REGISTERS_BASE + 0x02004) |
| 58 | #define WL18XX_REG_INTERRUPT_NO_CLEAR (WL18XX_REGISTERS_BASE + 0x050E8) |
| 59 | #define WL18XX_REG_INTERRUPT_ACK (WL18XX_REGISTERS_BASE + 0x050F0) |
| 60 | #define WL18XX_REG_INTERRUPT_TRIG (WL18XX_REGISTERS_BASE + 0x5074) |
| 61 | #define WL18XX_REG_INTERRUPT_TRIG_H (WL18XX_REGISTERS_BASE + 0x5078) |
| 62 | #define WL18XX_REG_INTERRUPT_MASK (WL18XX_REGISTERS_BASE + 0x0050DC) |
| 63 | |
| 64 | #define WL18XX_REG_CHIP_ID_B (WL18XX_REGISTERS_BASE + 0x01542C) |
| 65 | |
| 66 | #define WL18XX_SLV_MEM_DATA (WL18XX_HOST_BASE + 0x0018) |
| 67 | #define WL18XX_SLV_REG_DATA (WL18XX_HOST_BASE + 0x0008) |
| 68 | |
| 69 | /* Scratch Pad registers*/ |
| 70 | #define WL18XX_SCR_PAD0 (WL18XX_REGISTERS_BASE + 0x0154EC) |
| 71 | #define WL18XX_SCR_PAD1 (WL18XX_REGISTERS_BASE + 0x0154F0) |
| 72 | #define WL18XX_SCR_PAD2 (WL18XX_REGISTERS_BASE + 0x0154F4) |
| 73 | #define WL18XX_SCR_PAD3 (WL18XX_REGISTERS_BASE + 0x0154F8) |
| 74 | #define WL18XX_SCR_PAD4 (WL18XX_REGISTERS_BASE + 0x0154FC) |
| 75 | #define WL18XX_SCR_PAD4_SET (WL18XX_REGISTERS_BASE + 0x015504) |
| 76 | #define WL18XX_SCR_PAD4_CLR (WL18XX_REGISTERS_BASE + 0x015500) |
| 77 | #define WL18XX_SCR_PAD5 (WL18XX_REGISTERS_BASE + 0x015508) |
| 78 | #define WL18XX_SCR_PAD5_SET (WL18XX_REGISTERS_BASE + 0x015510) |
| 79 | #define WL18XX_SCR_PAD5_CLR (WL18XX_REGISTERS_BASE + 0x01550C) |
| 80 | #define WL18XX_SCR_PAD6 (WL18XX_REGISTERS_BASE + 0x015514) |
| 81 | #define WL18XX_SCR_PAD7 (WL18XX_REGISTERS_BASE + 0x015518) |
| 82 | #define WL18XX_SCR_PAD8 (WL18XX_REGISTERS_BASE + 0x01551C) |
| 83 | #define WL18XX_SCR_PAD9 (WL18XX_REGISTERS_BASE + 0x015520) |
| 84 | |
| 85 | /* Spare registers*/ |
| 86 | #define WL18XX_SPARE_A1 (WL18XX_REGISTERS_BASE + 0x002194) |
| 87 | #define WL18XX_SPARE_A2 (WL18XX_REGISTERS_BASE + 0x002198) |
| 88 | #define WL18XX_SPARE_A3 (WL18XX_REGISTERS_BASE + 0x00219C) |
| 89 | #define WL18XX_SPARE_A4 (WL18XX_REGISTERS_BASE + 0x0021A0) |
| 90 | #define WL18XX_SPARE_A5 (WL18XX_REGISTERS_BASE + 0x0021A4) |
| 91 | #define WL18XX_SPARE_A6 (WL18XX_REGISTERS_BASE + 0x0021A8) |
| 92 | #define WL18XX_SPARE_A7 (WL18XX_REGISTERS_BASE + 0x0021AC) |
| 93 | #define WL18XX_SPARE_A8 (WL18XX_REGISTERS_BASE + 0x0021B0) |
| 94 | #define WL18XX_SPARE_B1 (WL18XX_REGISTERS_BASE + 0x015524) |
| 95 | #define WL18XX_SPARE_B2 (WL18XX_REGISTERS_BASE + 0x015528) |
| 96 | #define WL18XX_SPARE_B3 (WL18XX_REGISTERS_BASE + 0x01552C) |
| 97 | #define WL18XX_SPARE_B4 (WL18XX_REGISTERS_BASE + 0x015530) |
| 98 | #define WL18XX_SPARE_B5 (WL18XX_REGISTERS_BASE + 0x015534) |
| 99 | #define WL18XX_SPARE_B6 (WL18XX_REGISTERS_BASE + 0x015538) |
| 100 | #define WL18XX_SPARE_B7 (WL18XX_REGISTERS_BASE + 0x01553C) |
| 101 | #define WL18XX_SPARE_B8 (WL18XX_REGISTERS_BASE + 0x015540) |
| 102 | |
| 103 | #define WL18XX_REG_COMMAND_MAILBOX_PTR (WL18XX_SCR_PAD0) |
| 104 | #define WL18XX_REG_EVENT_MAILBOX_PTR (WL18XX_SCR_PAD1) |
| 105 | |
| 106 | #define WL18XX_CMD_MBOX_ADDRESS 0xB007B4 |
| 107 | |
| 108 | #define WL18XX_FW_STATUS_ADDR 0x50F8 |
| 109 | |
| 110 | #define CHIP_ID_185x_PG10 (0x06030101) |
| 111 | |
| 112 | #endif /* __REG_H__ */ |