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gerrit-public.fairphone.software / kernel / msm-4.9 / 5db4187a037fb9e4b6908ef7bcef0f79395b398f / . / drivers / media / dvb-frontends / rtl2832_priv.h
blob: 75af963f444f4ca64ba76aed421364613a47bb1d [file] [log] [blame]
Thomas Mair82041c02012-05-18 14:47:40 -0300[diff] [blame]1/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#ifndef RTL2832_PRIV_H
22#define RTL2832_PRIV_H
23
24#include "dvb_frontend.h"
25#include "rtl2832.h"
26
27#define LOG_PREFIX "rtl2832"
28
29#undef dbg
30#define dbg(f, arg...) \
31do { \
32 if (rtl2832_debug) \
33 printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg); \
34} while (0)
35#undef err
36#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
37#undef info
38#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
39#undef warn
40#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
41
42struct rtl2832_priv {
43 struct i2c_adapter *i2c;
44 struct dvb_frontend fe;
45 struct rtl2832_config cfg;
46
47 bool i2c_gate_state;
48 bool sleeping;
49
50 u8 tuner;
51 u8 page; /* active register page */
52};
53
54struct rtl2832_reg_entry {
55 u8 page;
56 u8 start_address;
57 u8 msb;
58 u8 lsb;
59};
60
61struct rtl2832_reg_value {
62 int reg;
63 u32 value;
64};
65
66
67/* Demod register bit names */
68enum DVBT_REG_BIT_NAME {
69 DVBT_SOFT_RST,
70 DVBT_IIC_REPEAT,
71 DVBT_TR_WAIT_MIN_8K,
72 DVBT_RSD_BER_FAIL_VAL,
73 DVBT_EN_BK_TRK,
74 DVBT_REG_PI,
75 DVBT_REG_PFREQ_1_0,
76 DVBT_PD_DA8,
77 DVBT_LOCK_TH,
78 DVBT_BER_PASS_SCAL,
79 DVBT_CE_FFSM_BYPASS,
80 DVBT_ALPHAIIR_N,
81 DVBT_ALPHAIIR_DIF,
82 DVBT_EN_TRK_SPAN,
83 DVBT_LOCK_TH_LEN,
84 DVBT_CCI_THRE,
85 DVBT_CCI_MON_SCAL,
86 DVBT_CCI_M0,
87 DVBT_CCI_M1,
88 DVBT_CCI_M2,
89 DVBT_CCI_M3,
90 DVBT_SPEC_INIT_0,
91 DVBT_SPEC_INIT_1,
92 DVBT_SPEC_INIT_2,
93 DVBT_AD_EN_REG,
94 DVBT_AD_EN_REG1,
95 DVBT_EN_BBIN,
96 DVBT_MGD_THD0,
97 DVBT_MGD_THD1,
98 DVBT_MGD_THD2,
99 DVBT_MGD_THD3,
100 DVBT_MGD_THD4,
101 DVBT_MGD_THD5,
102 DVBT_MGD_THD6,
103 DVBT_MGD_THD7,
104 DVBT_EN_CACQ_NOTCH,
105 DVBT_AD_AV_REF,
106 DVBT_PIP_ON,
107 DVBT_SCALE1_B92,
108 DVBT_SCALE1_B93,
109 DVBT_SCALE1_BA7,
110 DVBT_SCALE1_BA9,
111 DVBT_SCALE1_BAA,
112 DVBT_SCALE1_BAB,
113 DVBT_SCALE1_BAC,
114 DVBT_SCALE1_BB0,
115 DVBT_SCALE1_BB1,
116 DVBT_KB_P1,
117 DVBT_KB_P2,
118 DVBT_KB_P3,
119 DVBT_OPT_ADC_IQ,
120 DVBT_AD_AVI,
121 DVBT_AD_AVQ,
122 DVBT_K1_CR_STEP12,
123 DVBT_TRK_KS_P2,
124 DVBT_TRK_KS_I2,
125 DVBT_TR_THD_SET2,
126 DVBT_TRK_KC_P2,
127 DVBT_TRK_KC_I2,
128 DVBT_CR_THD_SET2,
129 DVBT_PSET_IFFREQ,
130 DVBT_SPEC_INV,
131 DVBT_BW_INDEX,
132 DVBT_RSAMP_RATIO,
133 DVBT_CFREQ_OFF_RATIO,
134 DVBT_FSM_STAGE,
135 DVBT_RX_CONSTEL,
136 DVBT_RX_HIER,
137 DVBT_RX_C_RATE_LP,
138 DVBT_RX_C_RATE_HP,
139 DVBT_GI_IDX,
140 DVBT_FFT_MODE_IDX,
141 DVBT_RSD_BER_EST,
142 DVBT_CE_EST_EVM,
143 DVBT_RF_AGC_VAL,
144 DVBT_IF_AGC_VAL,
145 DVBT_DAGC_VAL,
146 DVBT_SFREQ_OFF,
147 DVBT_CFREQ_OFF,
148 DVBT_POLAR_RF_AGC,
149 DVBT_POLAR_IF_AGC,
150 DVBT_AAGC_HOLD,
151 DVBT_EN_RF_AGC,
152 DVBT_EN_IF_AGC,
153 DVBT_IF_AGC_MIN,
154 DVBT_IF_AGC_MAX,
155 DVBT_RF_AGC_MIN,
156 DVBT_RF_AGC_MAX,
157 DVBT_IF_AGC_MAN,
158 DVBT_IF_AGC_MAN_VAL,
159 DVBT_RF_AGC_MAN,
160 DVBT_RF_AGC_MAN_VAL,
161 DVBT_DAGC_TRG_VAL,
162 DVBT_AGC_TARG_VAL,
163 DVBT_LOOP_GAIN_3_0,
164 DVBT_LOOP_GAIN_4,
165 DVBT_VTOP,
166 DVBT_KRF,
167 DVBT_AGC_TARG_VAL_0,
168 DVBT_AGC_TARG_VAL_8_1,
169 DVBT_AAGC_LOOP_GAIN,
170 DVBT_LOOP_GAIN2_3_0,
171 DVBT_LOOP_GAIN2_4,
172 DVBT_LOOP_GAIN3,
173 DVBT_VTOP1,
174 DVBT_VTOP2,
175 DVBT_VTOP3,
176 DVBT_KRF1,
177 DVBT_KRF2,
178 DVBT_KRF3,
179 DVBT_KRF4,
180 DVBT_EN_GI_PGA,
181 DVBT_THD_LOCK_UP,
182 DVBT_THD_LOCK_DW,
183 DVBT_THD_UP1,
184 DVBT_THD_DW1,
185 DVBT_INTER_CNT_LEN,
186 DVBT_GI_PGA_STATE,
187 DVBT_EN_AGC_PGA,
188 DVBT_CKOUTPAR,
189 DVBT_CKOUT_PWR,
190 DVBT_SYNC_DUR,
191 DVBT_ERR_DUR,
192 DVBT_SYNC_LVL,
193 DVBT_ERR_LVL,
194 DVBT_VAL_LVL,
195 DVBT_SERIAL,
196 DVBT_SER_LSB,
197 DVBT_CDIV_PH0,
198 DVBT_CDIV_PH1,
199 DVBT_MPEG_IO_OPT_2_2,
200 DVBT_MPEG_IO_OPT_1_0,
201 DVBT_CKOUTPAR_PIP,
202 DVBT_CKOUT_PWR_PIP,
203 DVBT_SYNC_LVL_PIP,
204 DVBT_ERR_LVL_PIP,
205 DVBT_VAL_LVL_PIP,
206 DVBT_CKOUTPAR_PID,
207 DVBT_CKOUT_PWR_PID,
208 DVBT_SYNC_LVL_PID,
209 DVBT_ERR_LVL_PID,
210 DVBT_VAL_LVL_PID,
211 DVBT_SM_PASS,
212 DVBT_UPDATE_REG_2,
213 DVBT_BTHD_P3,
214 DVBT_BTHD_D3,
215 DVBT_FUNC4_REG0,
216 DVBT_FUNC4_REG1,
217 DVBT_FUNC4_REG2,
218 DVBT_FUNC4_REG3,
219 DVBT_FUNC4_REG4,
220 DVBT_FUNC4_REG5,
221 DVBT_FUNC4_REG6,
222 DVBT_FUNC4_REG7,
223 DVBT_FUNC4_REG8,
224 DVBT_FUNC4_REG9,
225 DVBT_FUNC4_REG10,
226 DVBT_FUNC5_REG0,
227 DVBT_FUNC5_REG1,
228 DVBT_FUNC5_REG2,
229 DVBT_FUNC5_REG3,
230 DVBT_FUNC5_REG4,
231 DVBT_FUNC5_REG5,
232 DVBT_FUNC5_REG6,
233 DVBT_FUNC5_REG7,
234 DVBT_FUNC5_REG8,
235 DVBT_FUNC5_REG9,
236 DVBT_FUNC5_REG10,
237 DVBT_FUNC5_REG11,
238 DVBT_FUNC5_REG12,
239 DVBT_FUNC5_REG13,
240 DVBT_FUNC5_REG14,
241 DVBT_FUNC5_REG15,
242 DVBT_FUNC5_REG16,
243 DVBT_FUNC5_REG17,
244 DVBT_FUNC5_REG18,
245 DVBT_AD7_SETTING,
246 DVBT_RSSI_R,
247 DVBT_ACI_DET_IND,
248 DVBT_REG_MON,
249 DVBT_REG_MONSEL,
250 DVBT_REG_GPE,
251 DVBT_REG_GPO,
252 DVBT_REG_4MSEL,
253 DVBT_TEST_REG_1,
254 DVBT_TEST_REG_2,
255 DVBT_TEST_REG_3,
256 DVBT_TEST_REG_4,
257 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
258};
259
Antti Palosaari5db41872012-09-11 22:27:08 -0300[diff] [blame^]260static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
261 {DVBT_DAGC_TRG_VAL, 0x39},
262 {DVBT_AGC_TARG_VAL_0, 0x0},
263 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
264 {DVBT_AAGC_LOOP_GAIN, 0x16},
265 {DVBT_LOOP_GAIN2_3_0, 0x6},
266 {DVBT_LOOP_GAIN2_4, 0x1},
267 {DVBT_LOOP_GAIN3, 0x16},
268 {DVBT_VTOP1, 0x35},
269 {DVBT_VTOP2, 0x21},
270 {DVBT_VTOP3, 0x21},
271 {DVBT_KRF1, 0x0},
272 {DVBT_KRF2, 0x40},
273 {DVBT_KRF3, 0x10},
274 {DVBT_KRF4, 0x10},
275 {DVBT_IF_AGC_MIN, 0x80},
276 {DVBT_IF_AGC_MAX, 0x7f},
277 {DVBT_RF_AGC_MIN, 0x9c},
278 {DVBT_RF_AGC_MAX, 0x7f},
279 {DVBT_POLAR_RF_AGC, 0x0},
280 {DVBT_POLAR_IF_AGC, 0x0},
281 {DVBT_AD7_SETTING, 0xe9f4},
282 {DVBT_OPT_ADC_IQ, 0x1},
283 {DVBT_AD_AVI, 0x0},
284 {DVBT_AD_AVQ, 0x0},
285};
286
Antti Palosaari832cc7c2012-09-11 22:27:04 -0300[diff] [blame]287static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
288 {DVBT_DAGC_TRG_VAL, 0x5a},
289 {DVBT_AGC_TARG_VAL_0, 0x0},
290 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
291 {DVBT_AAGC_LOOP_GAIN, 0x16},
292 {DVBT_LOOP_GAIN2_3_0, 0x6},
293 {DVBT_LOOP_GAIN2_4, 0x1},
294 {DVBT_LOOP_GAIN3, 0x16},
295 {DVBT_VTOP1, 0x35},
296 {DVBT_VTOP2, 0x21},
297 {DVBT_VTOP3, 0x21},
298 {DVBT_KRF1, 0x0},
299 {DVBT_KRF2, 0x40},
300 {DVBT_KRF3, 0x10},
301 {DVBT_KRF4, 0x10},
302 {DVBT_IF_AGC_MIN, 0x80},
303 {DVBT_IF_AGC_MAX, 0x7f},
304 {DVBT_RF_AGC_MIN, 0x80},
305 {DVBT_RF_AGC_MAX, 0x7f},
306 {DVBT_POLAR_RF_AGC, 0x0},
307 {DVBT_POLAR_IF_AGC, 0x0},
308 {DVBT_AD7_SETTING, 0xe9bf},
309 {DVBT_EN_GI_PGA, 0x0},
310 {DVBT_THD_LOCK_UP, 0x0},
311 {DVBT_THD_LOCK_DW, 0x0},
312 {DVBT_THD_UP1, 0x11},
313 {DVBT_THD_DW1, 0xef},
314 {DVBT_INTER_CNT_LEN, 0xc},
315 {DVBT_GI_PGA_STATE, 0x0},
316 {DVBT_EN_AGC_PGA, 0x1},
317 {DVBT_IF_AGC_MAN, 0x0},
318};
319
Thomas Mair82041c02012-05-18 14:47:40 -0300[diff] [blame]320#endif /* RTL2832_PRIV_H */