blob: 313c2c64498a2753ff0340ae5e5905ac2bca8ce8 [file] [log] [blame]
Florian Fainelli7f646e92014-05-23 17:40:53 -07001/*
2 * Generic Broadcom Set Top Box Level 2 Interrupt controller driver
3 *
4 * Copyright (C) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/init.h>
19#include <linux/slab.h>
20#include <linux/module.h>
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080021#include <linux/kconfig.h>
Florian Fainelli7f646e92014-05-23 17:40:53 -070022#include <linux/platform_device.h>
Kevin Cernekee05f12752014-11-06 22:44:20 -080023#include <linux/spinlock.h>
Florian Fainelli7f646e92014-05-23 17:40:53 -070024#include <linux/of.h>
25#include <linux/of_irq.h>
26#include <linux/of_address.h>
27#include <linux/of_platform.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/irqdomain.h>
32#include <linux/irqchip.h>
33#include <linux/irqchip/chained_irq.h>
34
Florian Fainelli7f646e92014-05-23 17:40:53 -070035#include "irqchip.h"
36
37/* Register offsets in the L2 interrupt controller */
38#define CPU_STATUS 0x00
39#define CPU_SET 0x04
40#define CPU_CLEAR 0x08
41#define CPU_MASK_STATUS 0x0c
42#define CPU_MASK_SET 0x10
43#define CPU_MASK_CLEAR 0x14
44
45/* L2 intc private data structure */
46struct brcmstb_l2_intc_data {
47 int parent_irq;
48 void __iomem *base;
49 struct irq_domain *domain;
50 bool can_wake;
51 u32 saved_mask; /* for suspend/resume */
52};
53
54static void brcmstb_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
55{
56 struct brcmstb_l2_intc_data *b = irq_desc_get_handler_data(desc);
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080057 struct irq_chip_generic *gc = irq_get_domain_generic_chip(b->domain, 0);
Florian Fainelli7f646e92014-05-23 17:40:53 -070058 struct irq_chip *chip = irq_desc_get_chip(desc);
59 u32 status;
60
61 chained_irq_enter(chip, desc);
62
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080063 status = irq_reg_readl(gc, CPU_STATUS) &
64 ~(irq_reg_readl(gc, CPU_MASK_STATUS));
Florian Fainelli7f646e92014-05-23 17:40:53 -070065
66 if (status == 0) {
Kevin Cernekee05f12752014-11-06 22:44:20 -080067 raw_spin_lock(&desc->lock);
68 handle_bad_irq(irq, desc);
69 raw_spin_unlock(&desc->lock);
Florian Fainelli7f646e92014-05-23 17:40:53 -070070 goto out;
71 }
72
73 do {
74 irq = ffs(status) - 1;
75 /* ack at our level */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080076 irq_reg_writel(gc, 1 << irq, CPU_CLEAR);
Florian Fainelli7f646e92014-05-23 17:40:53 -070077 status &= ~(1 << irq);
78 generic_handle_irq(irq_find_mapping(b->domain, irq));
79 } while (status);
80out:
81 chained_irq_exit(chip, desc);
82}
83
84static void brcmstb_l2_intc_suspend(struct irq_data *d)
85{
86 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
87 struct brcmstb_l2_intc_data *b = gc->private;
88
89 irq_gc_lock(gc);
90 /* Save the current mask */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080091 b->saved_mask = irq_reg_readl(gc, CPU_MASK_STATUS);
Florian Fainelli7f646e92014-05-23 17:40:53 -070092
93 if (b->can_wake) {
94 /* Program the wakeup mask */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -080095 irq_reg_writel(gc, ~gc->wake_active, CPU_MASK_SET);
96 irq_reg_writel(gc, gc->wake_active, CPU_MASK_CLEAR);
Florian Fainelli7f646e92014-05-23 17:40:53 -070097 }
98 irq_gc_unlock(gc);
99}
100
101static void brcmstb_l2_intc_resume(struct irq_data *d)
102{
103 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
104 struct brcmstb_l2_intc_data *b = gc->private;
105
106 irq_gc_lock(gc);
107 /* Clear unmasked non-wakeup interrupts */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800108 irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active, CPU_CLEAR);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700109
110 /* Restore the saved mask */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800111 irq_reg_writel(gc, b->saved_mask, CPU_MASK_SET);
112 irq_reg_writel(gc, ~b->saved_mask, CPU_MASK_CLEAR);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700113 irq_gc_unlock(gc);
114}
115
116int __init brcmstb_l2_intc_of_init(struct device_node *np,
117 struct device_node *parent)
118{
119 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
120 struct brcmstb_l2_intc_data *data;
121 struct irq_chip_generic *gc;
122 struct irq_chip_type *ct;
123 int ret;
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800124 unsigned int flags;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700125
126 data = kzalloc(sizeof(*data), GFP_KERNEL);
127 if (!data)
128 return -ENOMEM;
129
130 data->base = of_iomap(np, 0);
131 if (!data->base) {
132 pr_err("failed to remap intc L2 registers\n");
133 ret = -ENOMEM;
134 goto out_free;
135 }
136
137 /* Disable all interrupts by default */
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800138 writel(0xffffffff, data->base + CPU_MASK_SET);
139 writel(0xffffffff, data->base + CPU_CLEAR);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700140
141 data->parent_irq = irq_of_parse_and_map(np, 0);
Dmitry Torokhovd99ba442014-11-14 14:16:42 -0800142 if (!data->parent_irq) {
Florian Fainelli7f646e92014-05-23 17:40:53 -0700143 pr_err("failed to find parent interrupt\n");
Dmitry Torokhovd99ba442014-11-14 14:16:42 -0800144 ret = -EINVAL;
Florian Fainelli7f646e92014-05-23 17:40:53 -0700145 goto out_unmap;
146 }
147
148 data->domain = irq_domain_add_linear(np, 32,
149 &irq_generic_chip_ops, NULL);
150 if (!data->domain) {
151 ret = -ENOMEM;
152 goto out_unmap;
153 }
154
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800155 /* MIPS chips strapped for BE will automagically configure the
156 * peripheral registers for CPU-native byte order.
157 */
158 flags = 0;
159 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
160 flags |= IRQ_GC_BE_IO;
161
Florian Fainelli7f646e92014-05-23 17:40:53 -0700162 /* Allocate a single Generic IRQ chip for this node */
163 ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,
Kevin Cernekee1abbdba2014-11-06 22:44:29 -0800164 np->full_name, handle_edge_irq, clr, 0, flags);
Florian Fainelli7f646e92014-05-23 17:40:53 -0700165 if (ret) {
166 pr_err("failed to allocate generic irq chip\n");
167 goto out_free_domain;
168 }
169
170 /* Set the IRQ chaining logic */
171 irq_set_handler_data(data->parent_irq, data);
172 irq_set_chained_handler(data->parent_irq, brcmstb_l2_intc_irq_handle);
173
174 gc = irq_get_domain_generic_chip(data->domain, 0);
175 gc->reg_base = data->base;
176 gc->private = data;
177 ct = gc->chip_types;
178
179 ct->chip.irq_ack = irq_gc_ack_set_bit;
180 ct->regs.ack = CPU_CLEAR;
181
182 ct->chip.irq_mask = irq_gc_mask_disable_reg;
183 ct->regs.disable = CPU_MASK_SET;
184
185 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
186 ct->regs.enable = CPU_MASK_CLEAR;
187
188 ct->chip.irq_suspend = brcmstb_l2_intc_suspend;
189 ct->chip.irq_resume = brcmstb_l2_intc_resume;
190
191 if (of_property_read_bool(np, "brcm,irq-can-wake")) {
192 data->can_wake = true;
193 /* This IRQ chip can wake the system, set all child interrupts
194 * in wake_enabled mask
195 */
196 gc->wake_enabled = 0xffffffff;
197 ct->chip.irq_set_wake = irq_gc_set_wake;
198 }
199
200 pr_info("registered L2 intc (mem: 0x%p, parent irq: %d)\n",
201 data->base, data->parent_irq);
202
203 return 0;
204
205out_free_domain:
206 irq_domain_remove(data->domain);
207out_unmap:
208 iounmap(data->base);
209out_free:
210 kfree(data);
211 return ret;
212}
213IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_intc_of_init);