blob: 9a0767b9c89da656be79048b109bda47fcd58ef6 [file] [log] [blame]
Magnus Damm44358042013-02-18 23:28:34 +09001/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Geert Uytterhoeven705bc962014-09-12 15:15:18 +020020#include <linux/clk.h>
Magnus Damm44358042013-02-18 23:28:34 +090021#include <linux/init.h>
Guennadi Liakhovetski894db162013-06-13 11:23:38 +020022#include <linux/of.h>
Magnus Damm44358042013-02-18 23:28:34 +090023#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26#include <linux/ioport.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/irqdomain.h>
30#include <linux/err.h>
31#include <linux/slab.h>
32#include <linux/module.h>
Magnus Damme03f9082014-12-03 21:18:03 +090033#include <linux/of_device.h>
Magnus Damm44358042013-02-18 23:28:34 +090034#include <linux/platform_data/irq-renesas-intc-irqpin.h>
Geert Uytterhoeven705bc962014-09-12 15:15:18 +020035#include <linux/pm_runtime.h>
Magnus Damm44358042013-02-18 23:28:34 +090036
37#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
38
39#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
40#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
41#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
42#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
43#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
Magnus Damme03f9082014-12-03 21:18:03 +090044#define INTC_IRQPIN_REG_NR_MANDATORY 5
45#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
46#define INTC_IRQPIN_REG_NR 6
Magnus Damm44358042013-02-18 23:28:34 +090047
48/* INTC external IRQ PIN hardware register access:
49 *
50 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
51 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
52 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
53 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
54 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
55 *
56 * (*) May be accessed by more than one driver instance - lock needed
57 * (**) Read-modify-write access by one driver instance - lock needed
58 * (***) Accessed by one driver instance only - no locking needed
59 */
60
61struct intc_irqpin_iomem {
62 void __iomem *iomem;
63 unsigned long (*read)(void __iomem *iomem);
64 void (*write)(void __iomem *iomem, unsigned long data);
65 int width;
Magnus Damm862d3092013-02-26 20:58:44 +090066};
Magnus Damm44358042013-02-18 23:28:34 +090067
68struct intc_irqpin_irq {
69 int hw_irq;
Magnus Damm33f958f2013-02-26 20:58:54 +090070 int requested_irq;
71 int domain_irq;
Magnus Damm44358042013-02-18 23:28:34 +090072 struct intc_irqpin_priv *p;
Magnus Damm862d3092013-02-26 20:58:44 +090073};
Magnus Damm44358042013-02-18 23:28:34 +090074
75struct intc_irqpin_priv {
76 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
77 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
78 struct renesas_intc_irqpin_config config;
79 unsigned int number_of_irqs;
80 struct platform_device *pdev;
81 struct irq_chip irq_chip;
82 struct irq_domain *irq_domain;
Geert Uytterhoeven705bc962014-09-12 15:15:18 +020083 struct clk *clk;
Bastian Hecht427cc722013-03-27 14:54:03 +010084 bool shared_irqs;
85 u8 shared_irq_mask;
Magnus Damm44358042013-02-18 23:28:34 +090086};
87
Magnus Damme03f9082014-12-03 21:18:03 +090088struct intc_irqpin_irlm_config {
89 unsigned int irlm_bit;
90};
91
Magnus Damm44358042013-02-18 23:28:34 +090092static unsigned long intc_irqpin_read32(void __iomem *iomem)
93{
94 return ioread32(iomem);
95}
96
97static unsigned long intc_irqpin_read8(void __iomem *iomem)
98{
99 return ioread8(iomem);
100}
101
102static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
103{
104 iowrite32(data, iomem);
105}
106
107static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
108{
109 iowrite8(data, iomem);
110}
111
112static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
113 int reg)
114{
115 struct intc_irqpin_iomem *i = &p->iomem[reg];
Magnus Damm862d3092013-02-26 20:58:44 +0900116
Magnus Damm44358042013-02-18 23:28:34 +0900117 return i->read(i->iomem);
118}
119
120static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
121 int reg, unsigned long data)
122{
123 struct intc_irqpin_iomem *i = &p->iomem[reg];
Magnus Damm862d3092013-02-26 20:58:44 +0900124
Magnus Damm44358042013-02-18 23:28:34 +0900125 i->write(i->iomem, data);
126}
127
128static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
129 int reg, int hw_irq)
130{
131 return BIT((p->iomem[reg].width - 1) - hw_irq);
132}
133
134static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
135 int reg, int hw_irq)
136{
137 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
138}
139
140static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
141
142static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
143 int reg, int shift,
144 int width, int value)
145{
146 unsigned long flags;
147 unsigned long tmp;
148
149 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
150
151 tmp = intc_irqpin_read(p, reg);
152 tmp &= ~(((1 << width) - 1) << shift);
153 tmp |= value << shift;
154 intc_irqpin_write(p, reg, tmp);
155
156 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
157}
158
159static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
160 int irq, int do_mask)
161{
Laurent Pincharte55bc552013-11-09 13:18:01 +0100162 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
163 int bitfield_width = 4;
164 int shift = 32 - (irq + 1) * bitfield_width;
Magnus Damm44358042013-02-18 23:28:34 +0900165
166 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
167 shift, bitfield_width,
168 do_mask ? 0 : (1 << bitfield_width) - 1);
169}
170
171static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
172{
Laurent Pincharte55bc552013-11-09 13:18:01 +0100173 /* The SENSE register is assumed to be 32-bit. */
Magnus Damm44358042013-02-18 23:28:34 +0900174 int bitfield_width = p->config.sense_bitfield_width;
Laurent Pincharte55bc552013-11-09 13:18:01 +0100175 int shift = 32 - (irq + 1) * bitfield_width;
Magnus Damm44358042013-02-18 23:28:34 +0900176
177 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
178
179 if (value >= (1 << bitfield_width))
180 return -EINVAL;
181
182 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
183 bitfield_width, value);
184 return 0;
185}
186
187static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
188{
189 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
Magnus Damm33f958f2013-02-26 20:58:54 +0900190 str, i->requested_irq, i->hw_irq, i->domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900191}
192
193static void intc_irqpin_irq_enable(struct irq_data *d)
194{
195 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
196 int hw_irq = irqd_to_hwirq(d);
197
198 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
199 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
200}
201
202static void intc_irqpin_irq_disable(struct irq_data *d)
203{
204 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
205 int hw_irq = irqd_to_hwirq(d);
206
207 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
208 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
209}
210
Bastian Hecht427cc722013-03-27 14:54:03 +0100211static void intc_irqpin_shared_irq_enable(struct irq_data *d)
212{
213 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
214 int hw_irq = irqd_to_hwirq(d);
215
216 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
217 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
218
219 p->shared_irq_mask &= ~BIT(hw_irq);
220}
221
222static void intc_irqpin_shared_irq_disable(struct irq_data *d)
223{
224 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
225 int hw_irq = irqd_to_hwirq(d);
226
227 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
228 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
229
230 p->shared_irq_mask |= BIT(hw_irq);
231}
232
Magnus Damm44358042013-02-18 23:28:34 +0900233static void intc_irqpin_irq_enable_force(struct irq_data *d)
234{
235 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damm33f958f2013-02-26 20:58:54 +0900236 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
Magnus Damm44358042013-02-18 23:28:34 +0900237
238 intc_irqpin_irq_enable(d);
Magnus Dammd1b6aec2013-02-26 20:59:04 +0900239
240 /* enable interrupt through parent interrupt controller,
241 * assumes non-shared interrupt with 1:1 mapping
242 * needed for busted IRQs on some SoCs like sh73a0
243 */
Magnus Damm44358042013-02-18 23:28:34 +0900244 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
245}
246
247static void intc_irqpin_irq_disable_force(struct irq_data *d)
248{
249 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
Magnus Damm33f958f2013-02-26 20:58:54 +0900250 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
Magnus Damm44358042013-02-18 23:28:34 +0900251
Magnus Dammd1b6aec2013-02-26 20:59:04 +0900252 /* disable interrupt through parent interrupt controller,
253 * assumes non-shared interrupt with 1:1 mapping
254 * needed for busted IRQs on some SoCs like sh73a0
255 */
Magnus Damm44358042013-02-18 23:28:34 +0900256 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
257 intc_irqpin_irq_disable(d);
258}
259
260#define INTC_IRQ_SENSE_VALID 0x10
261#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
262
263static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
264 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
265 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
266 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
267 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
268 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
269};
270
271static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
272{
273 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
274 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
275
276 if (!(value & INTC_IRQ_SENSE_VALID))
277 return -EINVAL;
278
279 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
280 value ^ INTC_IRQ_SENSE_VALID);
281}
282
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200283static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
284{
285 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
286
287 if (!p->clk)
288 return 0;
289
290 if (on)
291 clk_enable(p->clk);
292 else
293 clk_disable(p->clk);
294
295 return 0;
296}
297
Magnus Damm44358042013-02-18 23:28:34 +0900298static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
299{
300 struct intc_irqpin_irq *i = dev_id;
301 struct intc_irqpin_priv *p = i->p;
302 unsigned long bit;
303
304 intc_irqpin_dbg(i, "demux1");
305 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
306
307 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
308 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
309 intc_irqpin_dbg(i, "demux2");
Magnus Damm33f958f2013-02-26 20:58:54 +0900310 generic_handle_irq(i->domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900311 return IRQ_HANDLED;
312 }
313 return IRQ_NONE;
314}
315
Bastian Hecht427cc722013-03-27 14:54:03 +0100316static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
317{
318 struct intc_irqpin_priv *p = dev_id;
319 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
320 irqreturn_t status = IRQ_NONE;
321 int k;
322
323 for (k = 0; k < 8; k++) {
324 if (reg_source & BIT(7 - k)) {
325 if (BIT(k) & p->shared_irq_mask)
326 continue;
327
328 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
329 }
330 }
331
332 return status;
333}
334
Magnus Damm44358042013-02-18 23:28:34 +0900335static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
336 irq_hw_number_t hw)
337{
338 struct intc_irqpin_priv *p = h->host_data;
339
Magnus Damm33f958f2013-02-26 20:58:54 +0900340 p->irq[hw].domain_irq = virq;
341 p->irq[hw].hw_irq = hw;
342
Magnus Damm44358042013-02-18 23:28:34 +0900343 intc_irqpin_dbg(&p->irq[hw], "map");
344 irq_set_chip_data(virq, h->host_data);
345 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
346 set_irq_flags(virq, IRQF_VALID); /* kill me now */
347 return 0;
348}
349
350static struct irq_domain_ops intc_irqpin_irq_domain_ops = {
351 .map = intc_irqpin_irq_domain_map,
Magnus Damm9d833bbe2013-03-06 15:16:08 +0900352 .xlate = irq_domain_xlate_twocell,
Magnus Damm44358042013-02-18 23:28:34 +0900353};
354
Magnus Damme03f9082014-12-03 21:18:03 +0900355static const struct intc_irqpin_irlm_config intc_irqpin_irlm_r8a7779 = {
356 .irlm_bit = 23, /* ICR0.IRLM0 */
357};
358
359static const struct of_device_id intc_irqpin_dt_ids[] = {
360 { .compatible = "renesas,intc-irqpin", },
361 { .compatible = "renesas,intc-irqpin-r8a7779",
362 .data = &intc_irqpin_irlm_r8a7779 },
363 {},
364};
365MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
366
Magnus Damm44358042013-02-18 23:28:34 +0900367static int intc_irqpin_probe(struct platform_device *pdev)
368{
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200369 struct device *dev = &pdev->dev;
370 struct renesas_intc_irqpin_config *pdata = dev->platform_data;
Magnus Damme03f9082014-12-03 21:18:03 +0900371 const struct of_device_id *of_id;
Magnus Damm44358042013-02-18 23:28:34 +0900372 struct intc_irqpin_priv *p;
373 struct intc_irqpin_iomem *i;
374 struct resource *io[INTC_IRQPIN_REG_NR];
375 struct resource *irq;
376 struct irq_chip *irq_chip;
377 void (*enable_fn)(struct irq_data *d);
378 void (*disable_fn)(struct irq_data *d);
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200379 const char *name = dev_name(dev);
Bastian Hecht427cc722013-03-27 14:54:03 +0100380 int ref_irq;
Magnus Damm44358042013-02-18 23:28:34 +0900381 int ret;
382 int k;
383
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200384 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
Magnus Damm44358042013-02-18 23:28:34 +0900385 if (!p) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200386 dev_err(dev, "failed to allocate driver data\n");
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200387 return -ENOMEM;
Magnus Damm44358042013-02-18 23:28:34 +0900388 }
389
390 /* deal with driver instance configuration */
Guennadi Liakhovetskic4fa4942013-06-19 07:53:09 +0200391 if (pdata) {
Magnus Damm44358042013-02-18 23:28:34 +0900392 memcpy(&p->config, pdata, sizeof(*pdata));
Guennadi Liakhovetskic4fa4942013-06-19 07:53:09 +0200393 } else {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200394 of_property_read_u32(dev->of_node, "sense-bitfield-width",
Guennadi Liakhovetski894db162013-06-13 11:23:38 +0200395 &p->config.sense_bitfield_width);
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200396 p->config.control_parent = of_property_read_bool(dev->of_node,
Guennadi Liakhovetskic4fa4942013-06-19 07:53:09 +0200397 "control-parent");
398 }
Magnus Damm44358042013-02-18 23:28:34 +0900399 if (!p->config.sense_bitfield_width)
400 p->config.sense_bitfield_width = 4; /* default to 4 bits */
401
402 p->pdev = pdev;
403 platform_set_drvdata(pdev, p);
404
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200405 p->clk = devm_clk_get(dev, NULL);
406 if (IS_ERR(p->clk)) {
407 dev_warn(dev, "unable to get clock\n");
408 p->clk = NULL;
409 }
410
411 pm_runtime_enable(dev);
412 pm_runtime_get_sync(dev);
413
Magnus Damme03f9082014-12-03 21:18:03 +0900414 /* get hold of register banks */
415 memset(io, 0, sizeof(io));
Magnus Damm44358042013-02-18 23:28:34 +0900416 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
417 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
Magnus Damme03f9082014-12-03 21:18:03 +0900418 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200419 dev_err(dev, "not enough IOMEM resources\n");
Magnus Damm44358042013-02-18 23:28:34 +0900420 ret = -EINVAL;
Magnus Damm08eba5b2013-02-26 20:59:13 +0900421 goto err0;
Magnus Damm44358042013-02-18 23:28:34 +0900422 }
423 }
424
425 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
426 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
427 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
428 if (!irq)
429 break;
430
Magnus Damm44358042013-02-18 23:28:34 +0900431 p->irq[k].p = p;
Magnus Damm33f958f2013-02-26 20:58:54 +0900432 p->irq[k].requested_irq = irq->start;
Magnus Damm44358042013-02-18 23:28:34 +0900433 }
434
435 p->number_of_irqs = k;
436 if (p->number_of_irqs < 1) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200437 dev_err(dev, "not enough IRQ resources\n");
Magnus Damm44358042013-02-18 23:28:34 +0900438 ret = -EINVAL;
Magnus Damm08eba5b2013-02-26 20:59:13 +0900439 goto err0;
Magnus Damm44358042013-02-18 23:28:34 +0900440 }
441
442 /* ioremap IOMEM and setup read/write callbacks */
443 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
444 i = &p->iomem[k];
445
Magnus Damme03f9082014-12-03 21:18:03 +0900446 /* handle optional registers */
447 if (!io[k])
448 continue;
449
Magnus Damm44358042013-02-18 23:28:34 +0900450 switch (resource_size(io[k])) {
451 case 1:
452 i->width = 8;
453 i->read = intc_irqpin_read8;
454 i->write = intc_irqpin_write8;
455 break;
456 case 4:
457 i->width = 32;
458 i->read = intc_irqpin_read32;
459 i->write = intc_irqpin_write32;
460 break;
461 default:
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200462 dev_err(dev, "IOMEM size mismatch\n");
Magnus Damm44358042013-02-18 23:28:34 +0900463 ret = -EINVAL;
Magnus Damm08eba5b2013-02-26 20:59:13 +0900464 goto err0;
Magnus Damm44358042013-02-18 23:28:34 +0900465 }
466
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200467 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
Magnus Damm08eba5b2013-02-26 20:59:13 +0900468 resource_size(io[k]));
Magnus Damm44358042013-02-18 23:28:34 +0900469 if (!i->iomem) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200470 dev_err(dev, "failed to remap IOMEM\n");
Magnus Damm44358042013-02-18 23:28:34 +0900471 ret = -ENXIO;
Magnus Damm08eba5b2013-02-26 20:59:13 +0900472 goto err0;
Magnus Damm44358042013-02-18 23:28:34 +0900473 }
474 }
475
Magnus Damme03f9082014-12-03 21:18:03 +0900476 /* configure "individual IRQ mode" where needed */
477 of_id = of_match_device(intc_irqpin_dt_ids, dev);
478 if (of_id && of_id->data) {
479 const struct intc_irqpin_irlm_config *irlm_config = of_id->data;
480
481 if (io[INTC_IRQPIN_REG_IRLM])
482 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
483 irlm_config->irlm_bit,
484 1, 1);
485 else
486 dev_warn(dev, "unable to select IRLM mode\n");
487 }
488
Magnus Damm44358042013-02-18 23:28:34 +0900489 /* mask all interrupts using priority */
490 for (k = 0; k < p->number_of_irqs; k++)
491 intc_irqpin_mask_unmask_prio(p, k, 1);
492
Bastian Hecht427cc722013-03-27 14:54:03 +0100493 /* clear all pending interrupts */
494 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
495
496 /* scan for shared interrupt lines */
497 ref_irq = p->irq[0].requested_irq;
498 p->shared_irqs = true;
499 for (k = 1; k < p->number_of_irqs; k++) {
500 if (ref_irq != p->irq[k].requested_irq) {
501 p->shared_irqs = false;
502 break;
503 }
504 }
505
Magnus Damm44358042013-02-18 23:28:34 +0900506 /* use more severe masking method if requested */
507 if (p->config.control_parent) {
508 enable_fn = intc_irqpin_irq_enable_force;
509 disable_fn = intc_irqpin_irq_disable_force;
Bastian Hecht427cc722013-03-27 14:54:03 +0100510 } else if (!p->shared_irqs) {
Magnus Damm44358042013-02-18 23:28:34 +0900511 enable_fn = intc_irqpin_irq_enable;
512 disable_fn = intc_irqpin_irq_disable;
Bastian Hecht427cc722013-03-27 14:54:03 +0100513 } else {
514 enable_fn = intc_irqpin_shared_irq_enable;
515 disable_fn = intc_irqpin_shared_irq_disable;
Magnus Damm44358042013-02-18 23:28:34 +0900516 }
517
518 irq_chip = &p->irq_chip;
519 irq_chip->name = name;
520 irq_chip->irq_mask = disable_fn;
521 irq_chip->irq_unmask = enable_fn;
Magnus Damm44358042013-02-18 23:28:34 +0900522 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200523 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
524 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
Magnus Damm44358042013-02-18 23:28:34 +0900525
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200526 p->irq_domain = irq_domain_add_simple(dev->of_node,
Magnus Damm44358042013-02-18 23:28:34 +0900527 p->number_of_irqs,
528 p->config.irq_base,
529 &intc_irqpin_irq_domain_ops, p);
530 if (!p->irq_domain) {
531 ret = -ENXIO;
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200532 dev_err(dev, "cannot initialize irq domain\n");
Magnus Damm08eba5b2013-02-26 20:59:13 +0900533 goto err0;
Magnus Damm44358042013-02-18 23:28:34 +0900534 }
535
Bastian Hecht427cc722013-03-27 14:54:03 +0100536 if (p->shared_irqs) {
537 /* request one shared interrupt */
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200538 if (devm_request_irq(dev, p->irq[0].requested_irq,
Bastian Hecht427cc722013-03-27 14:54:03 +0100539 intc_irqpin_shared_irq_handler,
540 IRQF_SHARED, name, p)) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200541 dev_err(dev, "failed to request low IRQ\n");
Magnus Damm44358042013-02-18 23:28:34 +0900542 ret = -ENOENT;
Magnus Damm08eba5b2013-02-26 20:59:13 +0900543 goto err1;
Magnus Damm44358042013-02-18 23:28:34 +0900544 }
Bastian Hecht427cc722013-03-27 14:54:03 +0100545 } else {
546 /* request interrupts one by one */
547 for (k = 0; k < p->number_of_irqs; k++) {
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200548 if (devm_request_irq(dev, p->irq[k].requested_irq,
549 intc_irqpin_irq_handler, 0, name,
550 &p->irq[k])) {
551 dev_err(dev, "failed to request low IRQ\n");
Bastian Hecht427cc722013-03-27 14:54:03 +0100552 ret = -ENOENT;
553 goto err1;
554 }
555 }
Magnus Damm44358042013-02-18 23:28:34 +0900556 }
557
Bastian Hecht427cc722013-03-27 14:54:03 +0100558 /* unmask all interrupts on prio level */
559 for (k = 0; k < p->number_of_irqs; k++)
560 intc_irqpin_mask_unmask_prio(p, k, 0);
561
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200562 dev_info(dev, "driving %d irqs\n", p->number_of_irqs);
Magnus Damm44358042013-02-18 23:28:34 +0900563
564 /* warn in case of mismatch if irq base is specified */
565 if (p->config.irq_base) {
Magnus Damm33f958f2013-02-26 20:58:54 +0900566 if (p->config.irq_base != p->irq[0].domain_irq)
Geert Uytterhoeven36845f12014-09-12 15:15:17 +0200567 dev_warn(dev, "irq base mismatch (%d/%d)\n",
Magnus Damm33f958f2013-02-26 20:58:54 +0900568 p->config.irq_base, p->irq[0].domain_irq);
Magnus Damm44358042013-02-18 23:28:34 +0900569 }
Magnus Damm862d3092013-02-26 20:58:44 +0900570
Magnus Damm44358042013-02-18 23:28:34 +0900571 return 0;
572
Magnus Damm44358042013-02-18 23:28:34 +0900573err1:
Magnus Damm08eba5b2013-02-26 20:59:13 +0900574 irq_domain_remove(p->irq_domain);
Magnus Damm44358042013-02-18 23:28:34 +0900575err0:
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200576 pm_runtime_put(dev);
577 pm_runtime_disable(dev);
Magnus Damm44358042013-02-18 23:28:34 +0900578 return ret;
579}
580
581static int intc_irqpin_remove(struct platform_device *pdev)
582{
583 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
Magnus Damm44358042013-02-18 23:28:34 +0900584
585 irq_domain_remove(p->irq_domain);
Geert Uytterhoeven705bc962014-09-12 15:15:18 +0200586 pm_runtime_put(&pdev->dev);
587 pm_runtime_disable(&pdev->dev);
Magnus Damm44358042013-02-18 23:28:34 +0900588 return 0;
589}
590
591static struct platform_driver intc_irqpin_device_driver = {
592 .probe = intc_irqpin_probe,
593 .remove = intc_irqpin_remove,
594 .driver = {
595 .name = "renesas_intc_irqpin",
Magnus Damm9d833bbe2013-03-06 15:16:08 +0900596 .of_match_table = intc_irqpin_dt_ids,
Magnus Damm44358042013-02-18 23:28:34 +0900597 }
598};
599
600static int __init intc_irqpin_init(void)
601{
602 return platform_driver_register(&intc_irqpin_device_driver);
603}
604postcore_initcall(intc_irqpin_init);
605
606static void __exit intc_irqpin_exit(void)
607{
608 platform_driver_unregister(&intc_irqpin_device_driver);
609}
610module_exit(intc_irqpin_exit);
611
612MODULE_AUTHOR("Magnus Damm");
613MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
614MODULE_LICENSE("GPL v2");