| Jongpill Lee | 7d44d2b | 2012-02-17 09:51:31 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 3 | * http://www.samsung.com |
| 4 | * |
| Jongpill Lee | 7d44d2b | 2012-02-17 09:51:31 +0900 | [diff] [blame] | 5 | * EXYNOS - Power management unit definition |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #ifndef __ASM_ARCH_REGS_PMU_H |
| 13 | #define __ASM_ARCH_REGS_PMU_H __FILE__ |
| 14 | |
| 15 | #include <mach/map.h> |
| 16 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 17 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 18 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 19 | #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) |
| Sylwester Nawrocki | 1d45ac4 | 2011-03-10 21:53:40 +0900 | [diff] [blame] | 20 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 21 | #define S5P_CENTRAL_LOWPWR_CFG (1 << 16) |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 22 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 23 | #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) |
| 24 | |
| 25 | #define S5P_USE_STANDBY_WFI0 (1 << 16) |
| 26 | #define S5P_USE_STANDBY_WFI1 (1 << 17) |
| Jongpill Lee | 9a94296 | 2011-09-27 07:24:58 +0900 | [diff] [blame] | 27 | #define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 28 | #define S5P_USE_STANDBY_WFE0 (1 << 24) |
| 29 | #define S5P_USE_STANDBY_WFE1 (1 << 25) |
| Jongpill Lee | 9a94296 | 2011-09-27 07:24:58 +0900 | [diff] [blame] | 30 | #define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 31 | |
| Kyungmin Park | d2edddf | 2011-08-19 20:25:05 +0900 | [diff] [blame] | 32 | #define S5P_SWRESET S5P_PMUREG(0x0400) |
| Kukjin Kim | 94c7ca7 | 2012-02-11 22:15:45 +0900 | [diff] [blame] | 33 | #define EXYNOS_SWRESET S5P_PMUREG(0x0400) |
| Kyungmin Park | d2edddf | 2011-08-19 20:25:05 +0900 | [diff] [blame] | 34 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 35 | #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) |
| 36 | #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) |
| 37 | #define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) |
| 38 | |
| Tomasz Stanislawski | fbf0556 | 2011-09-19 16:44:42 +0900 | [diff] [blame] | 39 | #define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) |
| 40 | #define S5P_HDMI_PHY_ENABLE (1 << 0) |
| 41 | |
| Tomasz Stanislawski | fbf0556 | 2011-09-19 16:44:42 +0900 | [diff] [blame] | 42 | #define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) |
| 43 | #define S5P_DAC_PHY_ENABLE (1 << 0) |
| 44 | |
| Kukjin Kim | be7004f | 2011-03-12 10:20:07 +0900 | [diff] [blame] | 45 | #define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4) |
| 46 | #define S5P_MIPI_DPHY_ENABLE (1 << 0) |
| 47 | #define S5P_MIPI_DPHY_SRESETN (1 << 1) |
| 48 | #define S5P_MIPI_DPHY_MRESETN (1 << 2) |
| 49 | |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 50 | #define S5P_INFORM0 S5P_PMUREG(0x0800) |
| 51 | #define S5P_INFORM1 S5P_PMUREG(0x0804) |
| 52 | #define S5P_INFORM2 S5P_PMUREG(0x0808) |
| 53 | #define S5P_INFORM3 S5P_PMUREG(0x080C) |
| 54 | #define S5P_INFORM4 S5P_PMUREG(0x0810) |
| 55 | #define S5P_INFORM5 S5P_PMUREG(0x0814) |
| 56 | #define S5P_INFORM6 S5P_PMUREG(0x0818) |
| 57 | #define S5P_INFORM7 S5P_PMUREG(0x081C) |
| 58 | |
| 59 | #define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000) |
| 60 | #define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004) |
| 61 | #define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008) |
| 62 | #define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010) |
| 63 | #define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014) |
| 64 | #define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018) |
| 65 | #define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080) |
| 66 | #define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0) |
| 67 | #define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4) |
| 68 | #define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100) |
| 69 | #define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104) |
| 70 | #define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C) |
| 71 | #define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120) |
| 72 | #define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124) |
| 73 | #define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128) |
| 74 | #define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C) |
| 75 | #define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138) |
| 76 | #define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C) |
| 77 | #define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140) |
| 78 | #define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144) |
| 79 | #define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148) |
| 80 | #define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C) |
| 81 | #define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 82 | #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158) |
| 83 | #define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C) |
| 84 | #define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160) |
| 85 | #define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164) |
| 86 | #define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168) |
| 87 | #define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C) |
| 88 | #define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 89 | #define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178) |
| 90 | #define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C) |
| 91 | #define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180) |
| 92 | #define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184) |
| 93 | #define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188) |
| 94 | #define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0) |
| 95 | #define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 96 | #define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8) |
| 97 | #define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC) |
| 98 | #define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0) |
| 99 | #define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4) |
| 100 | #define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 101 | #define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200) |
| 102 | #define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204) |
| 103 | #define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220) |
| 104 | #define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224) |
| 105 | #define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228) |
| 106 | #define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C) |
| 107 | #define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230) |
| 108 | #define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234) |
| 109 | #define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240) |
| 110 | #define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260) |
| 111 | #define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280) |
| 112 | #define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284) |
| 113 | #define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0) |
| 114 | #define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300) |
| 115 | #define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340) |
| 116 | #define S5P_CAM_LOWPWR S5P_PMUREG(0x1380) |
| 117 | #define S5P_TV_LOWPWR S5P_PMUREG(0x1384) |
| 118 | #define S5P_MFC_LOWPWR S5P_PMUREG(0x1388) |
| 119 | #define S5P_G3D_LOWPWR S5P_PMUREG(0x138C) |
| 120 | #define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 121 | #define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398) |
| 122 | #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) |
| 123 | #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) |
| 124 | |
| 125 | #define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) |
| 126 | #define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) |
| 127 | #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) |
| 128 | #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) |
| 129 | #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) |
| 130 | |
| 131 | #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) |
| 132 | #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) |
| 133 | #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) |
| 134 | #define S5P_TV_OPTION S5P_PMUREG(0x3C28) |
| 135 | #define S5P_MFC_OPTION S5P_PMUREG(0x3C48) |
| 136 | #define S5P_G3D_OPTION S5P_PMUREG(0x3C68) |
| 137 | #define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) |
| 138 | #define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) |
| 139 | #define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) |
| 140 | #define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) |
| 141 | #define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) |
| 142 | |
| 143 | #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) |
| 144 | #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) |
| 145 | #define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128) |
| 146 | #define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148) |
| 147 | #define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168) |
| 148 | #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) |
| 149 | #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) |
| 150 | |
| 151 | #define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) |
| 152 | #define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) |
| 153 | #define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) |
| 154 | #define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) |
| 155 | #define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 156 | #define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) |
| 157 | |
| Abhilash Kesavan | 4036021 | 2011-03-15 18:35:24 +0900 | [diff] [blame] | 158 | #define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 |
| JungHi Min | 911c29b | 2011-07-16 13:39:09 +0900 | [diff] [blame] | 159 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
| Jaecheol Lee | b77ca65 | 2011-03-10 13:21:51 +0900 | [diff] [blame] | 160 | #define S5P_INT_LOCAL_PWR_EN 0x7 |
| 161 | |
| 162 | #define S5P_CHECK_SLEEP 0x00000BAD |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 163 | |
| Jongpill Lee | 9a94296 | 2011-09-27 07:24:58 +0900 | [diff] [blame] | 164 | /* Only for EXYNOS4210 */ |
| Lukasz Majewski | 8ea2d9e | 2012-05-13 08:28:28 +0900 | [diff] [blame] | 165 | #define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704) |
| 166 | #define S5P_USBDEVICE_PHY_ENABLE (1 << 0) |
| 167 | |
| Jongpill Lee | 9a94296 | 2011-09-27 07:24:58 +0900 | [diff] [blame] | 168 | #define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) |
| 169 | #define S5P_USBHOST_PHY_ENABLE (1 << 0) |
| 170 | |
| 171 | #define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) |
| 172 | |
| 173 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) |
| 174 | #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) |
| 175 | #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) |
| 176 | #define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0) |
| 177 | #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) |
| 178 | #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) |
| 179 | |
| 180 | #define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) |
| 181 | |
| Inderpal Singh | 5ddfa84 | 2012-05-15 00:20:09 +0900 | [diff] [blame] | 182 | /* Only for EXYNOS4x12 */ |
| Jongpill Lee | 9a94296 | 2011-09-27 07:24:58 +0900 | [diff] [blame] | 183 | #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) |
| 184 | #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) |
| 185 | #define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR S5P_PMUREG(0x1058) |
| 186 | #define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1110) |
| 187 | #define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR S5P_PMUREG(0x1114) |
| 188 | #define S5P_CMU_RESET_COREBLK_LOWPWR S5P_PMUREG(0x111C) |
| 189 | #define S5P_MPLLUSER_SYSCLK_LOWPWR S5P_PMUREG(0x1130) |
| 190 | #define S5P_CMU_CLKSTOP_ISP_LOWPWR S5P_PMUREG(0x1154) |
| 191 | #define S5P_CMU_RESET_ISP_LOWPWR S5P_PMUREG(0x1174) |
| 192 | #define S5P_TOP_BUS_COREBLK_LOWPWR S5P_PMUREG(0x1190) |
| 193 | #define S5P_TOP_RETENTION_COREBLK_LOWPWR S5P_PMUREG(0x1194) |
| 194 | #define S5P_TOP_PWR_COREBLK_LOWPWR S5P_PMUREG(0x1198) |
| 195 | #define S5P_OSCCLK_GATE_LOWPWR S5P_PMUREG(0x11A4) |
| 196 | #define S5P_LOGIC_RESET_COREBLK_LOWPWR S5P_PMUREG(0x11B0) |
| 197 | #define S5P_OSCCLK_GATE_COREBLK_LOWPWR S5P_PMUREG(0x11B4) |
| 198 | #define S5P_HSI_MEM_LOWPWR S5P_PMUREG(0x11C4) |
| 199 | #define S5P_ROTATOR_MEM_LOWPWR S5P_PMUREG(0x11DC) |
| 200 | #define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR S5P_PMUREG(0x123C) |
| 201 | #define S5P_PAD_ISOLATION_COREBLK_LOWPWR S5P_PMUREG(0x1250) |
| 202 | #define S5P_GPIO_MODE_COREBLK_LOWPWR S5P_PMUREG(0x1320) |
| 203 | #define S5P_TOP_ASB_RESET_LOWPWR S5P_PMUREG(0x1344) |
| 204 | #define S5P_TOP_ASB_ISOLATION_LOWPWR S5P_PMUREG(0x1348) |
| 205 | #define S5P_ISP_LOWPWR S5P_PMUREG(0x1394) |
| 206 | #define S5P_DRAM_FREQ_DOWN_LOWPWR S5P_PMUREG(0x13B0) |
| 207 | #define S5P_DDRPHY_DLLOFF_LOWPWR S5P_PMUREG(0x13B4) |
| 208 | #define S5P_CMU_SYSCLK_ISP_LOWPWR S5P_PMUREG(0x13B8) |
| 209 | #define S5P_CMU_SYSCLK_GPS_LOWPWR S5P_PMUREG(0x13BC) |
| 210 | #define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR S5P_PMUREG(0x13C0) |
| 211 | |
| 212 | #define S5P_ARM_L2_0_OPTION S5P_PMUREG(0x2608) |
| 213 | #define S5P_ARM_L2_1_OPTION S5P_PMUREG(0x2628) |
| 214 | #define S5P_ONENAND_MEM_OPTION S5P_PMUREG(0x2E08) |
| 215 | #define S5P_HSI_MEM_OPTION S5P_PMUREG(0x2E28) |
| 216 | #define S5P_G2D_ACP_MEM_OPTION S5P_PMUREG(0x2E48) |
| 217 | #define S5P_USBOTG_MEM_OPTION S5P_PMUREG(0x2E68) |
| 218 | #define S5P_HSMMC_MEM_OPTION S5P_PMUREG(0x2E88) |
| 219 | #define S5P_CSSYS_MEM_OPTION S5P_PMUREG(0x2EA8) |
| 220 | #define S5P_SECSS_MEM_OPTION S5P_PMUREG(0x2EC8) |
| 221 | #define S5P_ROTATOR_MEM_OPTION S5P_PMUREG(0x2F48) |
| 222 | |
| Inderpal Singh | 5ddfa84 | 2012-05-15 00:20:09 +0900 | [diff] [blame] | 223 | /* Only for EXYNOS4412 */ |
| 224 | #define S5P_ARM_CORE2_LOWPWR S5P_PMUREG(0x1020) |
| 225 | #define S5P_DIS_IRQ_CORE2 S5P_PMUREG(0x1024) |
| 226 | #define S5P_DIS_IRQ_CENTRAL2 S5P_PMUREG(0x1028) |
| 227 | #define S5P_ARM_CORE3_LOWPWR S5P_PMUREG(0x1030) |
| 228 | #define S5P_DIS_IRQ_CORE3 S5P_PMUREG(0x1034) |
| 229 | #define S5P_DIS_IRQ_CENTRAL3 S5P_PMUREG(0x1038) |
| 230 | |
| Jongpill Lee | 7d44d2b | 2012-02-17 09:51:31 +0900 | [diff] [blame] | 231 | /* For EXYNOS5 */ |
| 232 | |
| 233 | #define EXYNOS5_USB_CFG S5P_PMUREG(0x0230) |
| 234 | |
| Jonghwan Choi | 7d896aa | 2012-06-27 09:47:35 +0900 | [diff] [blame] | 235 | #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) |
| 236 | #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) |
| 237 | |
| 238 | #define EXYNOS5_SYS_WDTRESET (1 << 20) |
| 239 | |
| Jongpill Lee | 7d44d2b | 2012-02-17 09:51:31 +0900 | [diff] [blame] | 240 | #define EXYNOS5_ARM_CORE0_SYS_PWR_REG S5P_PMUREG(0x1000) |
| 241 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1004) |
| 242 | #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1008) |
| 243 | #define EXYNOS5_ARM_CORE1_SYS_PWR_REG S5P_PMUREG(0x1010) |
| 244 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1014) |
| 245 | #define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1018) |
| 246 | #define EXYNOS5_FSYS_ARM_SYS_PWR_REG S5P_PMUREG(0x1040) |
| 247 | #define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1048) |
| 248 | #define EXYNOS5_ISP_ARM_SYS_PWR_REG S5P_PMUREG(0x1050) |
| 249 | #define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG S5P_PMUREG(0x1054) |
| 250 | #define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG S5P_PMUREG(0x1058) |
| 251 | #define EXYNOS5_ARM_COMMON_SYS_PWR_REG S5P_PMUREG(0x1080) |
| 252 | #define EXYNOS5_ARM_L2_SYS_PWR_REG S5P_PMUREG(0x10C0) |
| 253 | #define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1100) |
| 254 | #define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG S5P_PMUREG(0x1104) |
| 255 | #define EXYNOS5_CMU_RESET_SYS_PWR_REG S5P_PMUREG(0x110C) |
| 256 | #define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1120) |
| 257 | #define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1124) |
| 258 | #define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x112C) |
| 259 | #define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG S5P_PMUREG(0x1130) |
| 260 | #define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG S5P_PMUREG(0x1134) |
| 261 | #define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG S5P_PMUREG(0x1138) |
| 262 | #define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1140) |
| 263 | #define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1144) |
| 264 | #define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1148) |
| 265 | #define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x114C) |
| 266 | #define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1150) |
| 267 | #define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1154) |
| 268 | #define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1164) |
| 269 | #define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG S5P_PMUREG(0x1170) |
| 270 | #define EXYNOS5_TOP_BUS_SYS_PWR_REG S5P_PMUREG(0x1180) |
| 271 | #define EXYNOS5_TOP_RETENTION_SYS_PWR_REG S5P_PMUREG(0x1184) |
| 272 | #define EXYNOS5_TOP_PWR_SYS_PWR_REG S5P_PMUREG(0x1188) |
| 273 | #define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1190) |
| 274 | #define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1194) |
| 275 | #define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1198) |
| 276 | #define EXYNOS5_LOGIC_RESET_SYS_PWR_REG S5P_PMUREG(0x11A0) |
| 277 | #define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG S5P_PMUREG(0x11A4) |
| 278 | #define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B0) |
| 279 | #define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x11B4) |
| 280 | #define EXYNOS5_USBOTG_MEM_SYS_PWR_REG S5P_PMUREG(0x11C0) |
| 281 | #define EXYNOS5_G2D_MEM_SYS_PWR_REG S5P_PMUREG(0x11C8) |
| 282 | #define EXYNOS5_USBDRD_MEM_SYS_PWR_REG S5P_PMUREG(0x11CC) |
| 283 | #define EXYNOS5_SDMMC_MEM_SYS_PWR_REG S5P_PMUREG(0x11D0) |
| 284 | #define EXYNOS5_CSSYS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D4) |
| 285 | #define EXYNOS5_SECSS_MEM_SYS_PWR_REG S5P_PMUREG(0x11D8) |
| 286 | #define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG S5P_PMUREG(0x11DC) |
| 287 | #define EXYNOS5_INTRAM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E0) |
| 288 | #define EXYNOS5_INTROM_MEM_SYS_PWR_REG S5P_PMUREG(0x11E4) |
| 289 | #define EXYNOS5_JPEG_MEM_SYS_PWR_REG S5P_PMUREG(0x11E8) |
| 290 | #define EXYNOS5_HSI_MEM_SYS_PWR_REG S5P_PMUREG(0x11EC) |
| 291 | #define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG S5P_PMUREG(0x11F4) |
| 292 | #define EXYNOS5_SATA_MEM_SYS_PWR_REG S5P_PMUREG(0x11FC) |
| 293 | #define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG S5P_PMUREG(0x1200) |
| 294 | #define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG S5P_PMUREG(0x1204) |
| 295 | #define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG S5P_PMUREG(0x1208) |
| 296 | #define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG S5P_PMUREG(0x1220) |
| 297 | #define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG S5P_PMUREG(0x1224) |
| 298 | #define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG S5P_PMUREG(0x1228) |
| 299 | #define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG S5P_PMUREG(0x122C) |
| 300 | #define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG S5P_PMUREG(0x1230) |
| 301 | #define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG S5P_PMUREG(0x1234) |
| 302 | #define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG S5P_PMUREG(0x1238) |
| 303 | #define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x123C) |
| 304 | #define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1240) |
| 305 | #define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1250) |
| 306 | #define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG S5P_PMUREG(0x1260) |
| 307 | #define EXYNOS5_XUSBXTI_SYS_PWR_REG S5P_PMUREG(0x1280) |
| 308 | #define EXYNOS5_XXTI_SYS_PWR_REG S5P_PMUREG(0x1284) |
| 309 | #define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG S5P_PMUREG(0x12C0) |
| 310 | #define EXYNOS5_GPIO_MODE_SYS_PWR_REG S5P_PMUREG(0x1300) |
| 311 | #define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG S5P_PMUREG(0x1320) |
| 312 | #define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG S5P_PMUREG(0x1340) |
| 313 | #define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG S5P_PMUREG(0x1344) |
| 314 | #define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG S5P_PMUREG(0x1348) |
| 315 | #define EXYNOS5_GSCL_SYS_PWR_REG S5P_PMUREG(0x1400) |
| 316 | #define EXYNOS5_ISP_SYS_PWR_REG S5P_PMUREG(0x1404) |
| 317 | #define EXYNOS5_MFC_SYS_PWR_REG S5P_PMUREG(0x1408) |
| 318 | #define EXYNOS5_G3D_SYS_PWR_REG S5P_PMUREG(0x140C) |
| 319 | #define EXYNOS5_DISP1_SYS_PWR_REG S5P_PMUREG(0x1414) |
| 320 | #define EXYNOS5_MAU_SYS_PWR_REG S5P_PMUREG(0x1418) |
| 321 | #define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG S5P_PMUREG(0x1480) |
| 322 | #define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG S5P_PMUREG(0x1484) |
| 323 | #define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG S5P_PMUREG(0x1488) |
| 324 | #define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG S5P_PMUREG(0x148C) |
| 325 | #define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG S5P_PMUREG(0x1494) |
| 326 | #define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG S5P_PMUREG(0x1498) |
| 327 | #define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG S5P_PMUREG(0x14C0) |
| 328 | #define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG S5P_PMUREG(0x14C4) |
| 329 | #define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG S5P_PMUREG(0x14C8) |
| 330 | #define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG S5P_PMUREG(0x14CC) |
| 331 | #define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG S5P_PMUREG(0x14D4) |
| 332 | #define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG S5P_PMUREG(0x14D8) |
| 333 | #define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG S5P_PMUREG(0x1580) |
| 334 | #define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG S5P_PMUREG(0x1584) |
| 335 | #define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG S5P_PMUREG(0x1588) |
| 336 | #define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG S5P_PMUREG(0x158C) |
| 337 | #define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG S5P_PMUREG(0x1594) |
| 338 | #define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG S5P_PMUREG(0x1598) |
| 339 | |
| 340 | #define EXYNOS5_ARM_CORE0_OPTION S5P_PMUREG(0x2008) |
| 341 | #define EXYNOS5_ARM_CORE1_OPTION S5P_PMUREG(0x2088) |
| 342 | #define EXYNOS5_FSYS_ARM_OPTION S5P_PMUREG(0x2208) |
| 343 | #define EXYNOS5_ISP_ARM_OPTION S5P_PMUREG(0x2288) |
| 344 | #define EXYNOS5_ARM_COMMON_OPTION S5P_PMUREG(0x2408) |
| 345 | #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) |
| 346 | #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) |
| 347 | #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) |
| 348 | #define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004) |
| 349 | #define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024) |
| 350 | #define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) |
| 351 | #define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) |
| 352 | #define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) |
| 353 | #define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060) |
| 354 | #define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064) |
| 355 | #define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) |
| 356 | #define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) |
| 357 | #define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) |
| 358 | |
| 359 | #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) |
| 360 | #define EXYNOS5_USE_SC_COUNTER (1 << 0) |
| 361 | |
| 362 | #define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2) |
| 363 | #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) |
| 364 | |
| 365 | #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) |
| 366 | #define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) |
| 367 | |
| 368 | #define EXYNOS5_OPTION_USE_RETENTION (1 << 4) |
| 369 | |
| Changhwan Youn | d6d8b48 | 2010-12-03 17:15:40 +0900 | [diff] [blame] | 370 | #endif /* __ASM_ARCH_REGS_PMU_H */ |