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Jon Loeliger6b543402006-06-17 17:52:51 -05001/*
2 * MPC86xx Internal Memory Map
3 *
4 * Author: Jeff Brown
5 *
6 * Copyright 2004 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __ASM_POWERPC_IMMAP_86XX_H__
16#define __ASM_POWERPC_IMMAP_86XX_H__
17#ifdef __KERNEL__
18
19/* Eventually this should define all the IO block registers in 86xx */
20
21/* PCI Registers */
22typedef struct ccsr_pci {
23 uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
24 uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
25 uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
26 char res1[3060];
27 uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
28 uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
29 uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
30 char res2[4];
31 uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
32 char res3[12];
33 uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
34 uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
35 uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
36 char res4[4];
37 uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
38 char res5[12];
39 uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
40 uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
41 uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
42 char res6[4];
43 uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
44 char res7[12];
45 uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
46 uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
47 uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
48 char res8[4];
49 uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
50 char res9[12];
51 uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
52 uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
53 uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
54 char res10[4];
55 uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
56 char res11[268];
57 uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
58 char res12[4];
59 uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
60 uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
61 uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
62 char res13[12];
63 uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
64 char res14[4];
65 uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
66 uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
67 uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
68 char res15[12];
69 uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
70 char res16[4];
71 uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
72 char res17[4];
73 uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
74 char res18[12];
75 uint err_dr; /* 0x.e00 - PCI Error Detect Register */
76 uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
77 uint err_en; /* 0x.e08 - PCI Error Enable Register */
78 uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
79 uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
80 uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
81 uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
82 uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
83 uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
84 uint pci_timr; /* 0x.e24 - PCI Timer Register */
85 char res19[472];
86} ccsr_pci_t;
87
Jon Loeliger6b543402006-06-17 17:52:51 -050088/* Global Utility Registers */
89typedef struct ccsr_guts {
90 uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
91 uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
92 uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
93 uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
94 uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
95 char res1[12];
96 uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
97 char res2[12];
98 uint gpiocr; /* 0x.0030 - GPIO Control Register */
99 char res3[12];
100 uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
101 char res4[12];
102 uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
103 char res5[12];
104 uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
105 char res6[12];
106 uint devdisr; /* 0x.0070 - Device Disable Control */
107 char res7[12];
108 uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
109 char res8[12];
110 uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
111 char res9[12];
112 uint pvr; /* 0x.00a0 - Processor Version Register */
113 uint svr; /* 0x.00a4 - System Version Register */
114 char res10[3416];
115 uint clkocr; /* 0x.0e00 - Clock Out Select Register */
116 char res11[12];
117 uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
118 char res12[12];
119 uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
120 char res13[61916];
121} ccsr_guts_t;
122
123#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
124#endif /* __KERNEL__ */