Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * - Redistributions in binary form must reproduce the above |
| 18 | * copyright notice, this list of conditions and the following |
| 19 | * disclaimer in the documentation and/or other materials |
| 20 | * provided with the distribution. |
| 21 | * |
| 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 23 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 24 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 25 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 26 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 27 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 28 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 29 | * SOFTWARE. |
| 30 | */ |
| 31 | #ifndef __T4_H__ |
| 32 | #define __T4_H__ |
| 33 | |
| 34 | #include "t4_hw.h" |
| 35 | #include "t4_regs.h" |
| 36 | #include "t4_msg.h" |
| 37 | #include "t4fw_ri_api.h" |
| 38 | |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 39 | #define T4_MAX_NUM_QP 65536 |
| 40 | #define T4_MAX_NUM_CQ 65536 |
| 41 | #define T4_MAX_NUM_PD 65536 |
Steve Wise | f64b884 | 2010-05-20 16:58:05 -0500 | [diff] [blame] | 42 | #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) |
| 43 | #define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES) |
| 44 | #define T4_MAX_IQ_SIZE (65520 - 1) |
| 45 | #define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES) |
| 46 | #define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1) |
| 47 | #define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1) |
| 48 | #define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 49 | #define T4_MAX_NUM_STAG (1<<15) |
Steve Wise | a2de149 | 2013-08-06 21:04:39 +0530 | [diff] [blame] | 50 | #define T4_MAX_MR_SIZE (~0ULL) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 51 | #define T4_PAGESIZE_MASK 0xffff000 /* 4KB-128MB */ |
| 52 | #define T4_STAG_UNSET 0xffffffff |
| 53 | #define T4_FW_MAJ 0 |
| 54 | #define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1) |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 55 | #define A_PCIE_MA_SYNC 0x30b4 |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 56 | |
| 57 | struct t4_status_page { |
| 58 | __be32 rsvd1; /* flit 0 - hw owns */ |
| 59 | __be16 rsvd2; |
| 60 | __be16 qid; |
| 61 | __be16 cidx; |
| 62 | __be16 pidx; |
| 63 | u8 qp_err; /* flit 1 - sw owns */ |
| 64 | u8 db_off; |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 65 | u8 pad; |
| 66 | u16 host_wq_pidx; |
| 67 | u16 host_cidx; |
| 68 | u16 host_pidx; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 69 | }; |
| 70 | |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 71 | #define T4_EQ_ENTRY_SIZE 64 |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 72 | |
Steve Wise | 40dbf6e | 2010-09-17 15:40:15 -0500 | [diff] [blame] | 73 | #define T4_SQ_NUM_SLOTS 5 |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 74 | #define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 75 | #define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ |
| 76 | sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) |
| 77 | #define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - \ |
| 78 | sizeof(struct fw_ri_immd))) |
| 79 | #define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - \ |
| 80 | sizeof(struct fw_ri_rdma_write_wr) - \ |
| 81 | sizeof(struct fw_ri_immd))) |
| 82 | #define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - \ |
| 83 | sizeof(struct fw_ri_rdma_write_wr) - \ |
| 84 | sizeof(struct fw_ri_isgl)) / sizeof(struct fw_ri_sge)) |
| 85 | #define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - \ |
Steve Wise | 40dbf6e | 2010-09-17 15:40:15 -0500 | [diff] [blame] | 86 | sizeof(struct fw_ri_immd)) & ~31UL) |
Steve Wise | a03d9f9 | 2014-04-09 09:38:27 -0500 | [diff] [blame] | 87 | #define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64)) |
| 88 | #define T4_MAX_FR_DSGL 1024 |
| 89 | #define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64)) |
| 90 | |
| 91 | static inline int t4_max_fr_depth(int use_dsgl) |
| 92 | { |
| 93 | return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH; |
| 94 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 95 | |
| 96 | #define T4_RQ_NUM_SLOTS 2 |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 97 | #define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS) |
Steve Wise | f64b884 | 2010-05-20 16:58:05 -0500 | [diff] [blame] | 98 | #define T4_MAX_RECV_SGE 4 |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 99 | |
| 100 | union t4_wr { |
| 101 | struct fw_ri_res_wr res; |
| 102 | struct fw_ri_wr ri; |
| 103 | struct fw_ri_rdma_write_wr write; |
| 104 | struct fw_ri_send_wr send; |
| 105 | struct fw_ri_rdma_read_wr read; |
| 106 | struct fw_ri_bind_mw_wr bind; |
| 107 | struct fw_ri_fr_nsmr_wr fr; |
| 108 | struct fw_ri_inv_lstag_wr inv; |
| 109 | struct t4_status_page status; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 110 | __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS]; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 111 | }; |
| 112 | |
| 113 | union t4_recv_wr { |
| 114 | struct fw_ri_recv_wr recv; |
| 115 | struct t4_status_page status; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 116 | __be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS]; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 117 | }; |
| 118 | |
| 119 | static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid, |
| 120 | enum fw_wr_opcodes opcode, u8 flags, u8 len16) |
| 121 | { |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 122 | wqe->send.opcode = (u8)opcode; |
| 123 | wqe->send.flags = flags; |
| 124 | wqe->send.wrid = wrid; |
| 125 | wqe->send.r1[0] = 0; |
| 126 | wqe->send.r1[1] = 0; |
| 127 | wqe->send.r1[2] = 0; |
| 128 | wqe->send.len16 = len16; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | /* CQE/AE status codes */ |
| 132 | #define T4_ERR_SUCCESS 0x0 |
| 133 | #define T4_ERR_STAG 0x1 /* STAG invalid: either the */ |
| 134 | /* STAG is offlimt, being 0, */ |
| 135 | /* or STAG_key mismatch */ |
| 136 | #define T4_ERR_PDID 0x2 /* PDID mismatch */ |
| 137 | #define T4_ERR_QPID 0x3 /* QPID mismatch */ |
| 138 | #define T4_ERR_ACCESS 0x4 /* Invalid access right */ |
| 139 | #define T4_ERR_WRAP 0x5 /* Wrap error */ |
| 140 | #define T4_ERR_BOUND 0x6 /* base and bounds voilation */ |
| 141 | #define T4_ERR_INVALIDATE_SHARED_MR 0x7 /* attempt to invalidate a */ |
| 142 | /* shared memory region */ |
| 143 | #define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8 /* attempt to invalidate a */ |
| 144 | /* shared memory region */ |
| 145 | #define T4_ERR_ECC 0x9 /* ECC error detected */ |
| 146 | #define T4_ERR_ECC_PSTAG 0xA /* ECC error detected when */ |
| 147 | /* reading PSTAG for a MW */ |
| 148 | /* Invalidate */ |
| 149 | #define T4_ERR_PBL_ADDR_BOUND 0xB /* pbl addr out of bounds: */ |
| 150 | /* software error */ |
| 151 | #define T4_ERR_SWFLUSH 0xC /* SW FLUSHED */ |
| 152 | #define T4_ERR_CRC 0x10 /* CRC error */ |
| 153 | #define T4_ERR_MARKER 0x11 /* Marker error */ |
| 154 | #define T4_ERR_PDU_LEN_ERR 0x12 /* invalid PDU length */ |
| 155 | #define T4_ERR_OUT_OF_RQE 0x13 /* out of RQE */ |
| 156 | #define T4_ERR_DDP_VERSION 0x14 /* wrong DDP version */ |
| 157 | #define T4_ERR_RDMA_VERSION 0x15 /* wrong RDMA version */ |
| 158 | #define T4_ERR_OPCODE 0x16 /* invalid rdma opcode */ |
| 159 | #define T4_ERR_DDP_QUEUE_NUM 0x17 /* invalid ddp queue number */ |
| 160 | #define T4_ERR_MSN 0x18 /* MSN error */ |
| 161 | #define T4_ERR_TBIT 0x19 /* tag bit not set correctly */ |
| 162 | #define T4_ERR_MO 0x1A /* MO not 0 for TERMINATE */ |
| 163 | /* or READ_REQ */ |
| 164 | #define T4_ERR_MSN_GAP 0x1B |
| 165 | #define T4_ERR_MSN_RANGE 0x1C |
| 166 | #define T4_ERR_IRD_OVERFLOW 0x1D |
| 167 | #define T4_ERR_RQE_ADDR_BOUND 0x1E /* RQE addr out of bounds: */ |
| 168 | /* software error */ |
| 169 | #define T4_ERR_INTERNAL_ERR 0x1F /* internal error (opcode */ |
| 170 | /* mismatch) */ |
| 171 | /* |
| 172 | * CQE defs |
| 173 | */ |
| 174 | struct t4_cqe { |
| 175 | __be32 header; |
| 176 | __be32 len; |
| 177 | union { |
| 178 | struct { |
| 179 | __be32 stag; |
| 180 | __be32 msn; |
| 181 | } rcqe; |
| 182 | struct { |
| 183 | u32 nada1; |
| 184 | u16 nada2; |
| 185 | u16 cidx; |
| 186 | } scqe; |
| 187 | struct { |
| 188 | __be32 wrid_hi; |
| 189 | __be32 wrid_low; |
| 190 | } gen; |
| 191 | } u; |
| 192 | __be64 reserved; |
| 193 | __be64 bits_type_ts; |
| 194 | }; |
| 195 | |
| 196 | /* macros for flit 0 of the cqe */ |
| 197 | |
| 198 | #define S_CQE_QPID 12 |
| 199 | #define M_CQE_QPID 0xFFFFF |
| 200 | #define G_CQE_QPID(x) ((((x) >> S_CQE_QPID)) & M_CQE_QPID) |
| 201 | #define V_CQE_QPID(x) ((x)<<S_CQE_QPID) |
| 202 | |
| 203 | #define S_CQE_SWCQE 11 |
| 204 | #define M_CQE_SWCQE 0x1 |
| 205 | #define G_CQE_SWCQE(x) ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE) |
| 206 | #define V_CQE_SWCQE(x) ((x)<<S_CQE_SWCQE) |
| 207 | |
| 208 | #define S_CQE_STATUS 5 |
| 209 | #define M_CQE_STATUS 0x1F |
| 210 | #define G_CQE_STATUS(x) ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS) |
| 211 | #define V_CQE_STATUS(x) ((x)<<S_CQE_STATUS) |
| 212 | |
| 213 | #define S_CQE_TYPE 4 |
| 214 | #define M_CQE_TYPE 0x1 |
| 215 | #define G_CQE_TYPE(x) ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE) |
| 216 | #define V_CQE_TYPE(x) ((x)<<S_CQE_TYPE) |
| 217 | |
| 218 | #define S_CQE_OPCODE 0 |
| 219 | #define M_CQE_OPCODE 0xF |
| 220 | #define G_CQE_OPCODE(x) ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE) |
| 221 | #define V_CQE_OPCODE(x) ((x)<<S_CQE_OPCODE) |
| 222 | |
| 223 | #define SW_CQE(x) (G_CQE_SWCQE(be32_to_cpu((x)->header))) |
| 224 | #define CQE_QPID(x) (G_CQE_QPID(be32_to_cpu((x)->header))) |
| 225 | #define CQE_TYPE(x) (G_CQE_TYPE(be32_to_cpu((x)->header))) |
| 226 | #define SQ_TYPE(x) (CQE_TYPE((x))) |
| 227 | #define RQ_TYPE(x) (!CQE_TYPE((x))) |
| 228 | #define CQE_STATUS(x) (G_CQE_STATUS(be32_to_cpu((x)->header))) |
| 229 | #define CQE_OPCODE(x) (G_CQE_OPCODE(be32_to_cpu((x)->header))) |
| 230 | |
| 231 | #define CQE_SEND_OPCODE(x)( \ |
| 232 | (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \ |
| 233 | (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \ |
| 234 | (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \ |
| 235 | (G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV)) |
| 236 | |
| 237 | #define CQE_LEN(x) (be32_to_cpu((x)->len)) |
| 238 | |
| 239 | /* used for RQ completion processing */ |
| 240 | #define CQE_WRID_STAG(x) (be32_to_cpu((x)->u.rcqe.stag)) |
| 241 | #define CQE_WRID_MSN(x) (be32_to_cpu((x)->u.rcqe.msn)) |
| 242 | |
| 243 | /* used for SQ completion processing */ |
| 244 | #define CQE_WRID_SQ_IDX(x) ((x)->u.scqe.cidx) |
| 245 | |
| 246 | /* generic accessor macros */ |
| 247 | #define CQE_WRID_HI(x) ((x)->u.gen.wrid_hi) |
| 248 | #define CQE_WRID_LOW(x) ((x)->u.gen.wrid_low) |
| 249 | |
| 250 | /* macros for flit 3 of the cqe */ |
| 251 | #define S_CQE_GENBIT 63 |
| 252 | #define M_CQE_GENBIT 0x1 |
| 253 | #define G_CQE_GENBIT(x) (((x) >> S_CQE_GENBIT) & M_CQE_GENBIT) |
| 254 | #define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT) |
| 255 | |
| 256 | #define S_CQE_OVFBIT 62 |
| 257 | #define M_CQE_OVFBIT 0x1 |
| 258 | #define G_CQE_OVFBIT(x) ((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT) |
| 259 | |
| 260 | #define S_CQE_IQTYPE 60 |
| 261 | #define M_CQE_IQTYPE 0x3 |
| 262 | #define G_CQE_IQTYPE(x) ((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE) |
| 263 | |
| 264 | #define M_CQE_TS 0x0fffffffffffffffULL |
| 265 | #define G_CQE_TS(x) ((x) & M_CQE_TS) |
| 266 | |
| 267 | #define CQE_OVFBIT(x) ((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts))) |
| 268 | #define CQE_GENBIT(x) ((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts))) |
| 269 | #define CQE_TS(x) (G_CQE_TS(be64_to_cpu((x)->bits_type_ts))) |
| 270 | |
| 271 | struct t4_swsqe { |
| 272 | u64 wr_id; |
| 273 | struct t4_cqe cqe; |
| 274 | int read_len; |
| 275 | int opcode; |
| 276 | int complete; |
| 277 | int signaled; |
| 278 | u16 idx; |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 279 | int flushed; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 280 | }; |
| 281 | |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 282 | static inline pgprot_t t4_pgprot_wc(pgprot_t prot) |
| 283 | { |
Nishanth Aravamudan | e297d9d | 2011-03-14 10:36:11 +0000 | [diff] [blame] | 284 | #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 285 | return pgprot_writecombine(prot); |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 286 | #else |
| 287 | return pgprot_noncached(prot); |
| 288 | #endif |
| 289 | } |
| 290 | |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 291 | enum { |
| 292 | T4_SQ_ONCHIP = (1<<0), |
| 293 | }; |
| 294 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 295 | struct t4_sq { |
| 296 | union t4_wr *queue; |
| 297 | dma_addr_t dma_addr; |
FUJITA Tomonori | f38926a | 2010-06-03 05:37:50 +0000 | [diff] [blame] | 298 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 299 | unsigned long phys_addr; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 300 | struct t4_swsqe *sw_sq; |
| 301 | struct t4_swsqe *oldest_read; |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 302 | u64 __iomem *udb; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 303 | size_t memsize; |
| 304 | u32 qid; |
| 305 | u16 in_use; |
| 306 | u16 size; |
| 307 | u16 cidx; |
| 308 | u16 pidx; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 309 | u16 wq_pidx; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 310 | u16 wq_pidx_inc; |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 311 | u16 flags; |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 312 | short flush_cidx; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 313 | }; |
| 314 | |
| 315 | struct t4_swrqe { |
| 316 | u64 wr_id; |
| 317 | }; |
| 318 | |
| 319 | struct t4_rq { |
| 320 | union t4_recv_wr *queue; |
| 321 | dma_addr_t dma_addr; |
FUJITA Tomonori | f38926a | 2010-06-03 05:37:50 +0000 | [diff] [blame] | 322 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 323 | struct t4_swrqe *sw_rq; |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 324 | u64 __iomem *udb; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 325 | size_t memsize; |
| 326 | u32 qid; |
| 327 | u32 msn; |
| 328 | u32 rqt_hwaddr; |
| 329 | u16 rqt_size; |
| 330 | u16 in_use; |
| 331 | u16 size; |
| 332 | u16 cidx; |
| 333 | u16 pidx; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 334 | u16 wq_pidx; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 335 | u16 wq_pidx_inc; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 336 | }; |
| 337 | |
| 338 | struct t4_wq { |
| 339 | struct t4_sq sq; |
| 340 | struct t4_rq rq; |
| 341 | void __iomem *db; |
| 342 | void __iomem *gts; |
| 343 | struct c4iw_rdev *rdev; |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 344 | int flushed; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 345 | }; |
| 346 | |
| 347 | static inline int t4_rqes_posted(struct t4_wq *wq) |
| 348 | { |
| 349 | return wq->rq.in_use; |
| 350 | } |
| 351 | |
| 352 | static inline int t4_rq_empty(struct t4_wq *wq) |
| 353 | { |
| 354 | return wq->rq.in_use == 0; |
| 355 | } |
| 356 | |
| 357 | static inline int t4_rq_full(struct t4_wq *wq) |
| 358 | { |
| 359 | return wq->rq.in_use == (wq->rq.size - 1); |
| 360 | } |
| 361 | |
| 362 | static inline u32 t4_rq_avail(struct t4_wq *wq) |
| 363 | { |
| 364 | return wq->rq.size - 1 - wq->rq.in_use; |
| 365 | } |
| 366 | |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 367 | static inline void t4_rq_produce(struct t4_wq *wq, u8 len16) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 368 | { |
| 369 | wq->rq.in_use++; |
| 370 | if (++wq->rq.pidx == wq->rq.size) |
| 371 | wq->rq.pidx = 0; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 372 | wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); |
| 373 | if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS) |
| 374 | wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | static inline void t4_rq_consume(struct t4_wq *wq) |
| 378 | { |
| 379 | wq->rq.in_use--; |
| 380 | wq->rq.msn++; |
| 381 | if (++wq->rq.cidx == wq->rq.size) |
| 382 | wq->rq.cidx = 0; |
| 383 | } |
| 384 | |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 385 | static inline u16 t4_rq_host_wq_pidx(struct t4_wq *wq) |
| 386 | { |
| 387 | return wq->rq.queue[wq->rq.size].status.host_wq_pidx; |
| 388 | } |
| 389 | |
| 390 | static inline u16 t4_rq_wq_size(struct t4_wq *wq) |
| 391 | { |
| 392 | return wq->rq.size * T4_RQ_NUM_SLOTS; |
| 393 | } |
| 394 | |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 395 | static inline int t4_sq_onchip(struct t4_sq *sq) |
| 396 | { |
| 397 | return sq->flags & T4_SQ_ONCHIP; |
| 398 | } |
| 399 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 400 | static inline int t4_sq_empty(struct t4_wq *wq) |
| 401 | { |
| 402 | return wq->sq.in_use == 0; |
| 403 | } |
| 404 | |
| 405 | static inline int t4_sq_full(struct t4_wq *wq) |
| 406 | { |
| 407 | return wq->sq.in_use == (wq->sq.size - 1); |
| 408 | } |
| 409 | |
| 410 | static inline u32 t4_sq_avail(struct t4_wq *wq) |
| 411 | { |
| 412 | return wq->sq.size - 1 - wq->sq.in_use; |
| 413 | } |
| 414 | |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 415 | static inline void t4_sq_produce(struct t4_wq *wq, u8 len16) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 416 | { |
| 417 | wq->sq.in_use++; |
| 418 | if (++wq->sq.pidx == wq->sq.size) |
| 419 | wq->sq.pidx = 0; |
Steve Wise | d37ac31 | 2010-06-10 19:03:00 +0000 | [diff] [blame] | 420 | wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); |
| 421 | if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS) |
| 422 | wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static inline void t4_sq_consume(struct t4_wq *wq) |
| 426 | { |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 427 | BUG_ON(wq->sq.in_use < 1); |
| 428 | if (wq->sq.cidx == wq->sq.flush_cidx) |
| 429 | wq->sq.flush_cidx = -1; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 430 | wq->sq.in_use--; |
| 431 | if (++wq->sq.cidx == wq->sq.size) |
| 432 | wq->sq.cidx = 0; |
| 433 | } |
| 434 | |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 435 | static inline u16 t4_sq_host_wq_pidx(struct t4_wq *wq) |
| 436 | { |
| 437 | return wq->sq.queue[wq->sq.size].status.host_wq_pidx; |
| 438 | } |
| 439 | |
| 440 | static inline u16 t4_sq_wq_size(struct t4_wq *wq) |
| 441 | { |
| 442 | return wq->sq.size * T4_SQ_NUM_SLOTS; |
| 443 | } |
| 444 | |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 445 | /* This function copies 64 byte coalesced work request to memory |
| 446 | * mapped BAR2 space. For coalesced WRs, the SGE fetches data |
| 447 | * from the FIFO instead of from Host. |
| 448 | */ |
| 449 | static inline void pio_copy(u64 __iomem *dst, u64 *src) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 450 | { |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 451 | int count = 8; |
| 452 | |
| 453 | while (count) { |
| 454 | writeq(*src, dst); |
| 455 | src++; |
| 456 | dst++; |
| 457 | count--; |
| 458 | } |
| 459 | } |
| 460 | |
| 461 | static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, |
| 462 | union t4_wr *wqe) |
| 463 | { |
| 464 | |
| 465 | /* Flush host queue memory writes. */ |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 466 | wmb(); |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 467 | if (t5) { |
| 468 | if (inc == 1 && wqe) { |
| 469 | PDBG("%s: WC wq->sq.pidx = %d\n", |
| 470 | __func__, wq->sq.pidx); |
| 471 | pio_copy(wq->sq.udb + 7, (void *)wqe); |
| 472 | } else { |
| 473 | PDBG("%s: DB wq->sq.pidx = %d\n", |
| 474 | __func__, wq->sq.pidx); |
| 475 | writel(PIDX_T5(inc), wq->sq.udb); |
| 476 | } |
| 477 | |
| 478 | /* Flush user doorbell area writes. */ |
| 479 | wmb(); |
| 480 | return; |
| 481 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 482 | writel(QID(wq->sq.qid) | PIDX(inc), wq->db); |
| 483 | } |
| 484 | |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 485 | static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, |
| 486 | union t4_recv_wr *wqe) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 487 | { |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 488 | |
| 489 | /* Flush host queue memory writes. */ |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 490 | wmb(); |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 491 | if (t5) { |
| 492 | if (inc == 1 && wqe) { |
| 493 | PDBG("%s: WC wq->rq.pidx = %d\n", |
| 494 | __func__, wq->rq.pidx); |
| 495 | pio_copy(wq->rq.udb + 7, (void *)wqe); |
| 496 | } else { |
| 497 | PDBG("%s: DB wq->rq.pidx = %d\n", |
| 498 | __func__, wq->rq.pidx); |
| 499 | writel(PIDX_T5(inc), wq->rq.udb); |
| 500 | } |
| 501 | |
| 502 | /* Flush user doorbell area writes. */ |
| 503 | wmb(); |
| 504 | return; |
| 505 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 506 | writel(QID(wq->rq.qid) | PIDX(inc), wq->db); |
| 507 | } |
| 508 | |
| 509 | static inline int t4_wq_in_error(struct t4_wq *wq) |
| 510 | { |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 511 | return wq->rq.queue[wq->rq.size].status.qp_err; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 512 | } |
| 513 | |
| 514 | static inline void t4_set_wq_in_error(struct t4_wq *wq) |
| 515 | { |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 516 | wq->rq.queue[wq->rq.size].status.qp_err = 1; |
| 517 | } |
| 518 | |
| 519 | static inline void t4_disable_wq_db(struct t4_wq *wq) |
| 520 | { |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 521 | wq->rq.queue[wq->rq.size].status.db_off = 1; |
| 522 | } |
| 523 | |
| 524 | static inline void t4_enable_wq_db(struct t4_wq *wq) |
| 525 | { |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 526 | wq->rq.queue[wq->rq.size].status.db_off = 0; |
| 527 | } |
| 528 | |
| 529 | static inline int t4_wq_db_enabled(struct t4_wq *wq) |
| 530 | { |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 531 | return !wq->rq.queue[wq->rq.size].status.db_off; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 532 | } |
| 533 | |
| 534 | struct t4_cq { |
| 535 | struct t4_cqe *queue; |
| 536 | dma_addr_t dma_addr; |
FUJITA Tomonori | f38926a | 2010-06-03 05:37:50 +0000 | [diff] [blame] | 537 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 538 | struct t4_cqe *sw_queue; |
| 539 | void __iomem *gts; |
| 540 | struct c4iw_rdev *rdev; |
| 541 | u64 ugts; |
| 542 | size_t memsize; |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 543 | __be64 bits_type_ts; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 544 | u32 cqid; |
Hariprasad Shenai | cf38be6 | 2014-06-06 21:40:42 +0530 | [diff] [blame] | 545 | int vector; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 546 | u16 size; /* including status page */ |
| 547 | u16 cidx; |
| 548 | u16 sw_pidx; |
| 549 | u16 sw_cidx; |
| 550 | u16 sw_in_use; |
| 551 | u16 cidx_inc; |
| 552 | u8 gen; |
| 553 | u8 error; |
| 554 | }; |
| 555 | |
| 556 | static inline int t4_arm_cq(struct t4_cq *cq, int se) |
| 557 | { |
| 558 | u32 val; |
| 559 | |
Steve Wise | 7ec45b9 | 2010-05-20 16:57:49 -0500 | [diff] [blame] | 560 | while (cq->cidx_inc > CIDXINC_MASK) { |
| 561 | val = SEINTARM(0) | CIDXINC(CIDXINC_MASK) | TIMERREG(7) | |
| 562 | INGRESSQID(cq->cqid); |
Roland Dreier | be4c9ba | 2010-05-05 14:45:40 -0700 | [diff] [blame] | 563 | writel(val, cq->gts); |
Steve Wise | 7ec45b9 | 2010-05-20 16:57:49 -0500 | [diff] [blame] | 564 | cq->cidx_inc -= CIDXINC_MASK; |
| 565 | } |
| 566 | val = SEINTARM(se) | CIDXINC(cq->cidx_inc) | TIMERREG(6) | |
| 567 | INGRESSQID(cq->cqid); |
| 568 | writel(val, cq->gts); |
| 569 | cq->cidx_inc = 0; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 570 | return 0; |
| 571 | } |
| 572 | |
| 573 | static inline void t4_swcq_produce(struct t4_cq *cq) |
| 574 | { |
| 575 | cq->sw_in_use++; |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 576 | if (cq->sw_in_use == cq->size) { |
| 577 | PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid); |
| 578 | cq->error = 1; |
| 579 | BUG_ON(1); |
| 580 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 581 | if (++cq->sw_pidx == cq->size) |
| 582 | cq->sw_pidx = 0; |
| 583 | } |
| 584 | |
| 585 | static inline void t4_swcq_consume(struct t4_cq *cq) |
| 586 | { |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 587 | BUG_ON(cq->sw_in_use < 1); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 588 | cq->sw_in_use--; |
| 589 | if (++cq->sw_cidx == cq->size) |
| 590 | cq->sw_cidx = 0; |
| 591 | } |
| 592 | |
| 593 | static inline void t4_hwcq_consume(struct t4_cq *cq) |
| 594 | { |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 595 | cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts; |
Steve Wise | b298881 | 2013-08-06 21:04:38 +0530 | [diff] [blame] | 596 | if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == CIDXINC_MASK) { |
Steve Wise | ffc3f74 | 2011-03-11 22:30:42 +0000 | [diff] [blame] | 597 | u32 val; |
| 598 | |
| 599 | val = SEINTARM(0) | CIDXINC(cq->cidx_inc) | TIMERREG(7) | |
| 600 | INGRESSQID(cq->cqid); |
| 601 | writel(val, cq->gts); |
Steve Wise | 7ec45b9 | 2010-05-20 16:57:49 -0500 | [diff] [blame] | 602 | cq->cidx_inc = 0; |
Steve Wise | ffc3f74 | 2011-03-11 22:30:42 +0000 | [diff] [blame] | 603 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 604 | if (++cq->cidx == cq->size) { |
| 605 | cq->cidx = 0; |
| 606 | cq->gen ^= 1; |
| 607 | } |
| 608 | } |
| 609 | |
| 610 | static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe) |
| 611 | { |
| 612 | return (CQE_GENBIT(cqe) == cq->gen); |
| 613 | } |
| 614 | |
| 615 | static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe) |
| 616 | { |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 617 | int ret; |
| 618 | u16 prev_cidx; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 619 | |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 620 | if (cq->cidx == 0) |
| 621 | prev_cidx = cq->size - 1; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 622 | else |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 623 | prev_cidx = cq->cidx - 1; |
| 624 | |
| 625 | if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) { |
| 626 | ret = -EOVERFLOW; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 627 | cq->error = 1; |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 628 | printk(KERN_ERR MOD "cq overflow cqid %u\n", cq->cqid); |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 629 | BUG_ON(1); |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 630 | } else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) { |
Steve Wise | def4771 | 2014-04-09 09:38:26 -0500 | [diff] [blame] | 631 | |
| 632 | /* Ensure CQE is flushed to memory */ |
| 633 | rmb(); |
Steve Wise | 84172de | 2010-05-20 16:57:43 -0500 | [diff] [blame] | 634 | *cqe = &cq->queue[cq->cidx]; |
| 635 | ret = 0; |
| 636 | } else |
| 637 | ret = -ENODATA; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 638 | return ret; |
| 639 | } |
| 640 | |
| 641 | static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq) |
| 642 | { |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 643 | if (cq->sw_in_use == cq->size) { |
| 644 | PDBG("%s cxgb4 sw cq overflow cqid %u\n", __func__, cq->cqid); |
| 645 | cq->error = 1; |
| 646 | BUG_ON(1); |
| 647 | return NULL; |
| 648 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 649 | if (cq->sw_in_use) |
| 650 | return &cq->sw_queue[cq->sw_cidx]; |
| 651 | return NULL; |
| 652 | } |
| 653 | |
| 654 | static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe) |
| 655 | { |
| 656 | int ret = 0; |
| 657 | |
| 658 | if (cq->error) |
| 659 | ret = -ENODATA; |
| 660 | else if (cq->sw_in_use) |
| 661 | *cqe = &cq->sw_queue[cq->sw_cidx]; |
| 662 | else |
| 663 | ret = t4_next_hw_cqe(cq, cqe); |
| 664 | return ret; |
| 665 | } |
| 666 | |
| 667 | static inline int t4_cq_in_error(struct t4_cq *cq) |
| 668 | { |
| 669 | return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err; |
| 670 | } |
| 671 | |
| 672 | static inline void t4_set_cq_in_error(struct t4_cq *cq) |
| 673 | { |
| 674 | ((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1; |
| 675 | } |
| 676 | #endif |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 677 | |
| 678 | struct t4_dev_status_page { |
| 679 | u8 db_off; |
| 680 | }; |