Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * The OPP code in function cpu0_set_target() is reused from |
| 5 | * drivers/cpufreq/omap-cpufreq.c |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | |
| 12 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 13 | |
| 14 | #include <linux/clk.h> |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 15 | #include <linux/cpu.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 16 | #include <linux/cpu_cooling.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 17 | #include <linux/cpufreq.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 18 | #include <linux/cpumask.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 19 | #include <linux/err.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
Nishanth Menon | e4db1c7 | 2013-09-19 16:03:52 -0500 | [diff] [blame] | 22 | #include <linux/pm_opp.h> |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 23 | #include <linux/platform_device.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 24 | #include <linux/regulator/consumer.h> |
| 25 | #include <linux/slab.h> |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 26 | #include <linux/thermal.h> |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 27 | |
| 28 | static unsigned int transition_latency; |
| 29 | static unsigned int voltage_tolerance; /* in percentage */ |
| 30 | |
| 31 | static struct device *cpu_dev; |
| 32 | static struct clk *cpu_clk; |
| 33 | static struct regulator *cpu_reg; |
| 34 | static struct cpufreq_frequency_table *freq_table; |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 35 | static struct thermal_cooling_device *cdev; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 36 | |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 37 | static int cpu0_set_target(struct cpufreq_policy *policy, unsigned int index) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 38 | { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 39 | struct dev_pm_opp *opp; |
jhbird.choi@samsung.com | 5df6055 | 2013-03-18 08:09:42 +0000 | [diff] [blame] | 40 | unsigned long volt = 0, volt_old = 0, tol = 0; |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 41 | unsigned int old_freq, new_freq; |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 42 | long freq_Hz, freq_exact; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 43 | int ret; |
| 44 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 45 | freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000); |
Paul Walmsley | 2209b0c | 2013-11-25 18:01:18 -0800 | [diff] [blame] | 46 | if (freq_Hz <= 0) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 47 | freq_Hz = freq_table[index].frequency * 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 48 | |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 49 | freq_exact = freq_Hz; |
| 50 | new_freq = freq_Hz / 1000; |
| 51 | old_freq = clk_get_rate(cpu_clk) / 1000; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 52 | |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 53 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 54 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 55 | opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_Hz); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 56 | if (IS_ERR(opp)) { |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 57 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 58 | pr_err("failed to find OPP for %ld\n", freq_Hz); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 59 | return PTR_ERR(opp); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 60 | } |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 61 | volt = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 62 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 63 | tol = volt * voltage_tolerance / 100; |
| 64 | volt_old = regulator_get_voltage(cpu_reg); |
| 65 | } |
| 66 | |
| 67 | pr_debug("%u MHz, %ld mV --> %u MHz, %ld mV\n", |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 68 | old_freq / 1000, volt_old ? volt_old / 1000 : -1, |
| 69 | new_freq / 1000, volt ? volt / 1000 : -1); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 70 | |
| 71 | /* scaling up? scale voltage before frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 72 | if (!IS_ERR(cpu_reg) && new_freq > old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 73 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 74 | if (ret) { |
| 75 | pr_err("failed to scale voltage up: %d\n", ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 76 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 77 | } |
| 78 | } |
| 79 | |
Guennadi Liakhovetski | 0ca6843 | 2013-02-25 18:22:37 +0100 | [diff] [blame] | 80 | ret = clk_set_rate(cpu_clk, freq_exact); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 81 | if (ret) { |
| 82 | pr_err("failed to set clock rate: %d\n", ret); |
Mark Brown | 4a511de | 2013-08-13 14:58:24 +0200 | [diff] [blame] | 83 | if (!IS_ERR(cpu_reg)) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 84 | regulator_set_voltage_tol(cpu_reg, volt_old, tol); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 85 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | /* scaling down? scale voltage after frequency */ |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 89 | if (!IS_ERR(cpu_reg) && new_freq < old_freq) { |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 90 | ret = regulator_set_voltage_tol(cpu_reg, volt, tol); |
| 91 | if (ret) { |
| 92 | pr_err("failed to scale voltage down: %d\n", ret); |
Viresh Kumar | d4019f0 | 2013-08-14 19:38:24 +0530 | [diff] [blame] | 93 | clk_set_rate(cpu_clk, old_freq * 1000); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 94 | } |
| 95 | } |
| 96 | |
Viresh Kumar | fd143b4 | 2013-04-01 12:57:44 +0000 | [diff] [blame] | 97 | return ret; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 98 | } |
| 99 | |
| 100 | static int cpu0_cpufreq_init(struct cpufreq_policy *policy) |
| 101 | { |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 102 | policy->clk = cpu_clk; |
Viresh Kumar | 78b3d10 | 2013-10-03 20:29:09 +0530 | [diff] [blame] | 103 | return cpufreq_generic_init(policy, freq_table, transition_latency); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 104 | } |
| 105 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 106 | static struct cpufreq_driver cpu0_cpufreq_driver = { |
Viresh Kumar | 93575b7 | 2014-06-09 19:06:17 +0530 | [diff] [blame] | 107 | .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK, |
Viresh Kumar | f793d79 | 2013-10-03 20:28:00 +0530 | [diff] [blame] | 108 | .verify = cpufreq_generic_frequency_table_verify, |
Viresh Kumar | 9c0ebcf | 2013-10-25 19:45:48 +0530 | [diff] [blame] | 109 | .target_index = cpu0_set_target, |
Viresh Kumar | 652ed95 | 2014-01-09 20:38:43 +0530 | [diff] [blame] | 110 | .get = cpufreq_generic_get, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 111 | .init = cpu0_cpufreq_init, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 112 | .name = "generic_cpu0", |
Viresh Kumar | f793d79 | 2013-10-03 20:28:00 +0530 | [diff] [blame] | 113 | .attr = cpufreq_generic_attr, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 116 | static int cpu0_cpufreq_probe(struct platform_device *pdev) |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 117 | { |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 118 | struct device_node *np; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 119 | int ret; |
| 120 | |
Sudeep KarkadaNagesha | e1825b2 | 2013-09-10 18:59:46 +0100 | [diff] [blame] | 121 | cpu_dev = get_cpu_device(0); |
| 122 | if (!cpu_dev) { |
| 123 | pr_err("failed to get cpu0 device\n"); |
| 124 | return -ENODEV; |
| 125 | } |
Paolo Pisati | f5c3ef2 | 2013-03-28 09:24:29 +0000 | [diff] [blame] | 126 | |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 127 | np = of_node_get(cpu_dev->of_node); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 128 | if (!np) { |
| 129 | pr_err("failed to find cpu0 node\n"); |
Sudeep KarkadaNagesha | f837a9b | 2013-06-17 15:04:19 +0100 | [diff] [blame] | 130 | return -ENOENT; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 131 | } |
| 132 | |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 133 | cpu_reg = regulator_get_optional(cpu_dev, "cpu0"); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 134 | if (IS_ERR(cpu_reg)) { |
| 135 | /* |
| 136 | * If cpu0 regulator supply node is present, but regulator is |
| 137 | * not yet registered, we should try defering probe. |
| 138 | */ |
| 139 | if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) { |
| 140 | dev_err(cpu_dev, "cpu0 regulator not ready, retry\n"); |
| 141 | ret = -EPROBE_DEFER; |
| 142 | goto out_put_node; |
| 143 | } |
| 144 | pr_warn("failed to get cpu0 regulator: %ld\n", |
| 145 | PTR_ERR(cpu_reg)); |
Nishanth Menon | fc31d6f | 2013-05-01 13:38:12 +0000 | [diff] [blame] | 146 | } |
| 147 | |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 148 | cpu_clk = clk_get(cpu_dev, NULL); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 149 | if (IS_ERR(cpu_clk)) { |
| 150 | ret = PTR_ERR(cpu_clk); |
| 151 | pr_err("failed to get cpu0 clock: %d\n", ret); |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 152 | goto out_put_reg; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 153 | } |
| 154 | |
Viresh Kumar | 1bf8cc3 | 2014-07-11 20:24:19 +0530 | [diff] [blame] | 155 | /* OPPs might be populated at runtime, don't check for error here */ |
| 156 | of_init_opp_table(cpu_dev); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 157 | |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 158 | ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 159 | if (ret) { |
| 160 | pr_err("failed to init cpufreq table: %d\n", ret); |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 161 | goto out_put_clk; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | of_property_read_u32(np, "voltage-tolerance", &voltage_tolerance); |
| 165 | |
| 166 | if (of_property_read_u32(np, "clock-latency", &transition_latency)) |
| 167 | transition_latency = CPUFREQ_ETERNAL; |
| 168 | |
Philipp Zabel | 43c638e | 2013-09-26 11:19:37 +0200 | [diff] [blame] | 169 | if (!IS_ERR(cpu_reg)) { |
Nishanth Menon | 47d43ba | 2013-09-19 16:03:51 -0500 | [diff] [blame] | 170 | struct dev_pm_opp *opp; |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 171 | unsigned long min_uV, max_uV; |
| 172 | int i; |
| 173 | |
| 174 | /* |
| 175 | * OPP is maintained in order of increasing frequency, and |
| 176 | * freq_table initialised from OPP is therefore sorted in the |
| 177 | * same order. |
| 178 | */ |
| 179 | for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) |
| 180 | ; |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 181 | rcu_read_lock(); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 182 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 183 | freq_table[0].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 184 | min_uV = dev_pm_opp_get_voltage(opp); |
| 185 | opp = dev_pm_opp_find_freq_exact(cpu_dev, |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 186 | freq_table[i-1].frequency * 1000, true); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 187 | max_uV = dev_pm_opp_get_voltage(opp); |
Nishanth Menon | 78e8eb8 | 2013-01-18 19:52:33 +0000 | [diff] [blame] | 188 | rcu_read_unlock(); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 189 | ret = regulator_set_voltage_time(cpu_reg, min_uV, max_uV); |
| 190 | if (ret > 0) |
| 191 | transition_latency += ret * 1000; |
| 192 | } |
| 193 | |
| 194 | ret = cpufreq_register_driver(&cpu0_cpufreq_driver); |
| 195 | if (ret) { |
| 196 | pr_err("failed register driver: %d\n", ret); |
| 197 | goto out_free_table; |
| 198 | } |
| 199 | |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 200 | /* |
| 201 | * For now, just loading the cooling device; |
| 202 | * thermal DT code takes care of matching them. |
| 203 | */ |
| 204 | if (of_find_property(np, "#cooling-cells", NULL)) { |
| 205 | cdev = of_cpufreq_cooling_register(np, cpu_present_mask); |
| 206 | if (IS_ERR(cdev)) |
| 207 | pr_err("running cpufreq without cooling device: %ld\n", |
| 208 | PTR_ERR(cdev)); |
| 209 | } |
| 210 | |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 211 | of_node_put(np); |
| 212 | return 0; |
| 213 | |
| 214 | out_free_table: |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 215 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Lucas Stach | e3beb0a | 2014-05-16 12:20:42 +0200 | [diff] [blame] | 216 | out_put_clk: |
| 217 | if (!IS_ERR(cpu_clk)) |
| 218 | clk_put(cpu_clk); |
| 219 | out_put_reg: |
| 220 | if (!IS_ERR(cpu_reg)) |
| 221 | regulator_put(cpu_reg); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 222 | out_put_node: |
| 223 | of_node_put(np); |
| 224 | return ret; |
| 225 | } |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 226 | |
| 227 | static int cpu0_cpufreq_remove(struct platform_device *pdev) |
| 228 | { |
Eduardo Valentin | 77cff59 | 2013-07-15 09:09:14 -0400 | [diff] [blame] | 229 | cpufreq_cooling_unregister(cdev); |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 230 | cpufreq_unregister_driver(&cpu0_cpufreq_driver); |
Nishanth Menon | 5d4879c | 2013-09-19 16:03:50 -0500 | [diff] [blame] | 231 | dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); |
Shawn Guo | 5553f9e | 2013-01-30 14:27:49 +0000 | [diff] [blame] | 232 | |
| 233 | return 0; |
| 234 | } |
| 235 | |
| 236 | static struct platform_driver cpu0_cpufreq_platdrv = { |
| 237 | .driver = { |
| 238 | .name = "cpufreq-cpu0", |
| 239 | .owner = THIS_MODULE, |
| 240 | }, |
| 241 | .probe = cpu0_cpufreq_probe, |
| 242 | .remove = cpu0_cpufreq_remove, |
| 243 | }; |
| 244 | module_platform_driver(cpu0_cpufreq_platdrv); |
Shawn Guo | 95ceafd | 2012-09-06 07:09:11 +0000 | [diff] [blame] | 245 | |
| 246 | MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); |
| 247 | MODULE_DESCRIPTION("Generic CPU0 cpufreq driver"); |
| 248 | MODULE_LICENSE("GPL"); |