blob: cb20e0f74670aefb7e2765043c82b302d62bc4f7 [file] [log] [blame]
Lakshmi Narayana Kalavalac0dac062016-12-01 17:20:09 -08001/*
2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14&soc {
15 qcom,cam-req-mgr {
16 compatible = "qcom,cam-req-mgr";
17 status = "ok";
18 };
Jigarkumar Zala861231152017-02-28 14:05:11 -080019
20 qcom,csiphy@ac65000 {
21 cell-index = <0>;
22 compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
23 reg = <0x0ac65000 0x1000>;
24 reg-names = "csiphy";
25 interrupts = <0 477 0>;
26 interrupt-names = "csiphy";
27 gdscr-supply = <&titan_top_gdsc>;
28 qcom,cam-vreg-name = "gdscr";
29 qcom,csi-vdd-voltage = <1200000>;
30 qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
31 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
32 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
33 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
34 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
35 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
36 <&clock_camcc CAM_CC_CSIPHY0_CLK>,
37 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
38 <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>,
39 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
40 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>;
41 clock-names = "camnoc_axi_clk",
42 "soc_ahb_clk",
43 "slow_ahb_src_clk",
44 "cpas_ahb_clk",
45 "cphy_rx_clk_src",
46 "csiphy0_clk",
47 "csi0phytimer_clk_src",
48 "csi0phytimer_clk",
49 "ife_0_csid_clk",
50 "ife_0_csid_clk_src";
51 qcom,clock-rates =
52 <0 0 80000000 0 320000000 0 269333333 0 0 384000000>;
53 status = "ok";
54 };
55
56 qcom,csiphy@ac66000{
57 cell-index = <1>;
58 compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
59 reg = <0xac66000 0x1000>;
60 reg-names = "csiphy";
61 interrupts = <0 478 0>;
62 interrupt-names = "csiphy";
63 gdscr-supply = <&titan_top_gdsc>;
64 qcom,cam-vreg-name = "gdscr";
65 qcom,csi-vdd-voltage = <1200000>;
66 qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
67 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
68 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
69 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
70 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
71 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
72 <&clock_camcc CAM_CC_CSIPHY1_CLK>,
73 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
Viswanadha Raju Thotakuraeed9bb62017-05-03 12:10:19 -070074 <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>,
Jigarkumar Zala861231152017-02-28 14:05:11 -080075 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
76 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>;
77 clock-names = "camnoc_axi_clk",
78 "soc_ahb_clk",
79 "slow_ahb_src_clk",
80 "cpas_ahb_clk",
81 "cphy_rx_clk_src",
82 "csiphy1_clk",
83 "csi1phytimer_clk_src",
84 "csi1phytimer_clk",
85 "ife_1_csid_clk",
86 "ife_1_csid_clk_src";
87 qcom,clock-rates =
88 <0 0 80000000 0 320000000 0 269333333 0 0 384000000>;
89
90 status = "ok";
91 };
92
93 qcom,csiphy@ac67000 {
94 cell-index = <2>;
95 compatible = "qcom,csiphy-v1.0", "qcom,csiphy";
96 reg = <0xac67000 0x1000>;
97 reg-names = "csiphy";
98 interrupts = <0 479 0>;
99 interrupt-names = "csiphy";
100 gdscr-supply = <&titan_top_gdsc>;
101 qcom,cam-vreg-name = "gdscr";
102 qcom,csi-vdd-voltage = <1200000>;
103 qcom,mipi-csi-vdd-supply = <&pm8998_l26>;
104 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
105 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
106 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
107 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
108 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
109 <&clock_camcc CAM_CC_CSIPHY2_CLK>,
110 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
111 <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>,
112 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
113 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>;
114 clock-names = "camnoc_axi_clk",
115 "soc_ahb_clk",
116 "slow_ahb_src_clk",
117 "cpas_ahb_clk",
118 "cphy_rx_clk_src",
119 "csiphy2_clk",
120 "csi2phytimer_clk_src",
121 "csi2phytimer_clk",
122 "ife_lite_csid_clk",
123 "ife_lite_csid_clk_src";
124 qcom,clock-rates =
125 <0 0 80000000 0 320000000 0 269333333 0 0 384000000>;
126 status = "ok";
127 };
128
129 cci: qcom,cci@ac4a000 {
130 cell-index = <0>;
131 compatible = "qcom,cci";
132 reg = <0xac4a000 0x4000>;
133 #address-cells = <1>;
134 #size-cells = <0>;
135 reg-names = "cci";
136 interrupts = <0 460 0>;
137 interrupt-names = "cci";
138 status = "ok";
139 gdscr-supply = <&titan_top_gdsc>;
140 qcom,cam-vreg-name = "gdscr";
141 clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
142 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
143 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
144 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
145 <&clock_camcc CAM_CC_CCI_CLK>,
146 <&clock_camcc CAM_CC_CCI_CLK_SRC>;
147 clock-names = "camnoc_axi_clk",
148 "soc_ahb_clk",
149 "slow_ahb_src_clk",
150 "cpas_ahb_clk",
151 "cci_clk",
152 "cci_clk_src";
153 qcom,clock-rates = <0 0 80000000 0 0 37500000>;
154 pinctrl-names = "cci_default", "cci_suspend";
155 pinctrl-0 = <&cci0_active &cci1_active>;
156 pinctrl-1 = <&cci0_suspend &cci1_suspend>;
157 gpios = <&tlmm 17 0>,
158 <&tlmm 18 0>,
159 <&tlmm 19 0>,
160 <&tlmm 20 0>;
161 qcom,gpio-tbl-num = <0 1 2 3>;
162 qcom,gpio-tbl-flags = <1 1 1 1>;
163 qcom,gpio-tbl-label = "CCI_I2C_DATA0",
164 "CCI_I2C_CLK0",
165 "CCI_I2C_DATA1",
166 "CCI_I2C_CLK1";
167
168 i2c_freq_100Khz: qcom,i2c_standard_mode {
169 qcom,hw-thigh = <201>;
170 qcom,hw-tlow = <174>;
171 qcom,hw-tsu-sto = <204>;
172 qcom,hw-tsu-sta = <231>;
173 qcom,hw-thd-dat = <22>;
174 qcom,hw-thd-sta = <162>;
175 qcom,hw-tbuf = <227>;
176 qcom,hw-scl-stretch-en = <0>;
177 qcom,hw-trdhld = <6>;
178 qcom,hw-tsp = <3>;
179 qcom,cci-clk-src = <37500000>;
180 status = "ok";
181 };
182
183 i2c_freq_400Khz: qcom,i2c_fast_mode {
184 qcom,hw-thigh = <38>;
185 qcom,hw-tlow = <56>;
186 qcom,hw-tsu-sto = <40>;
187 qcom,hw-tsu-sta = <40>;
188 qcom,hw-thd-dat = <22>;
189 qcom,hw-thd-sta = <35>;
190 qcom,hw-tbuf = <62>;
191 qcom,hw-scl-stretch-en = <0>;
192 qcom,hw-trdhld = <6>;
193 qcom,hw-tsp = <3>;
194 qcom,cci-clk-src = <37500000>;
195 status = "ok";
196 };
197
198 i2c_freq_custom: qcom,i2c_custom_mode {
199 qcom,hw-thigh = <38>;
200 qcom,hw-tlow = <56>;
201 qcom,hw-tsu-sto = <40>;
202 qcom,hw-tsu-sta = <40>;
203 qcom,hw-thd-dat = <22>;
204 qcom,hw-thd-sta = <35>;
205 qcom,hw-tbuf = <62>;
206 qcom,hw-scl-stretch-en = <1>;
207 qcom,hw-trdhld = <6>;
208 qcom,hw-tsp = <3>;
209 qcom,cci-clk-src = <37500000>;
210 status = "ok";
211 };
212
213 i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
214 qcom,hw-thigh = <16>;
215 qcom,hw-tlow = <22>;
216 qcom,hw-tsu-sto = <17>;
217 qcom,hw-tsu-sta = <18>;
218 qcom,hw-thd-dat = <16>;
219 qcom,hw-thd-sta = <15>;
220 qcom,hw-tbuf = <24>;
221 qcom,hw-scl-stretch-en = <0>;
222 qcom,hw-trdhld = <3>;
223 qcom,hw-tsp = <3>;
224 qcom,cci-clk-src = <37500000>;
225 status = "ok";
226 };
227 };
Seemanta Duttadf1dde72017-04-05 17:33:02 -0700228
229 qcom,cam_smmu {
230 compatible = "qcom,msm-cam-smmu";
231 status = "ok";
232
233 msm_cam_smmu_ife {
234 compatible = "qcom,msm-cam-smmu-cb";
Patrick Daly8cb8d962017-05-08 14:46:09 -0700235 iommus = <&apps_smmu 0x808 0x0>,
236 <&apps_smmu 0x810 0x8>,
237 <&apps_smmu 0xc08 0x0>,
238 <&apps_smmu 0xc10 0x8>;
Seemanta Duttadf1dde72017-04-05 17:33:02 -0700239 label = "ife";
240 ife_iova_mem_map: iova-mem-map {
241 /* IO region is approximately 3.4 GB */
242 iova-mem-region-io {
243 iova-region-name = "io";
244 iova-region-start = <0x7400000>;
245 iova-region-len = <0xd8c00000>;
246 iova-region-id = <0x3>;
247 status = "ok";
248 };
249 };
250 };
251
252 msm_cam_icp_fw {
253 compatible = "qcom,msm-cam-smmu-fw-dev";
254 label="icp";
255 memory-region = <&pil_camera_mem>;
256 };
257
258 msm_cam_smmu_icp {
259 compatible = "qcom,msm-cam-smmu-cb";
Patrick Daly8cb8d962017-05-08 14:46:09 -0700260 iommus = <&apps_smmu 0x1078 0x2>,
261 <&apps_smmu 0x1020 0x8>,
262 <&apps_smmu 0x1040 0x8>,
263 <&apps_smmu 0x1030 0x0>,
264 <&apps_smmu 0x1050 0x0>;
Seemanta Duttadf1dde72017-04-05 17:33:02 -0700265 label = "icp";
266 icp_iova_mem_map: iova-mem-map {
267 iova-mem-region-firmware {
268 /* Firmware region is 5MB */
269 iova-region-name = "firmware";
270 iova-region-start = <0x0>;
271 iova-region-len = <0x500000>;
272 iova-region-id = <0x0>;
273 status = "ok";
274 };
275
276 iova-mem-region-shared {
277 /* Shared region is 100MB long */
278 iova-region-name = "shared";
279 iova-region-start = <0x7400000>;
280 iova-region-len = <0x6400000>;
281 iova-region-id = <0x1>;
282 status = "ok";
283 };
284
285 iova-mem-region-io {
286 /* IO region is approximately 3.3 GB */
287 iova-region-name = "io";
288 iova-region-start = <0xd800000>;
289 iova-region-len = <0xd2800000>;
290 iova-region-id = <0x3>;
291 status = "ok";
292 };
293 };
294 };
295
296 msm_cam_smmu_cpas_cdm {
297 compatible = "qcom,msm-cam-smmu-cb";
Patrick Daly8cb8d962017-05-08 14:46:09 -0700298 iommus = <&apps_smmu 0x1000 0x0>;
Seemanta Duttadf1dde72017-04-05 17:33:02 -0700299 label = "cpas-cdm0";
300 cpas_cdm_iova_mem_map: iova-mem-map {
301 iova-mem-region-io {
302 /* IO region is approximately 3.4 GB */
303 iova-region-name = "io";
304 iova-region-start = <0x7400000>;
305 iova-region-len = <0xd8c00000>;
306 iova-region-id = <0x3>;
307 status = "ok";
308 };
309 };
310 };
311
312 msm_cam_smmu_secure {
313 compatible = "qcom,msm-cam-smmu-cb";
Patrick Daly8cb8d962017-05-08 14:46:09 -0700314 iommus = <&apps_smmu 0x1001 0x0>;
Seemanta Duttadf1dde72017-04-05 17:33:02 -0700315 label = "cam-secure";
316 cam_secure_iova_mem_map: iova-mem-map {
317 /* Secure IO region is approximately 3.4 GB */
318 iova-mem-region-io {
319 iova-region-name = "io";
320 iova-region-start = <0x7400000>;
321 iova-region-len = <0xd8c00000>;
322 iova-region-id = <0x3>;
323 status = "ok";
324 };
325 };
326 };
327 };
Pavan Kumar Chilamkurthib6aa86d2017-05-01 23:47:11 -0700328
329 qcom,cam-cpas@ac40000 {
330 cell-index = <0>;
331 compatible = "qcom,cam-cpas";
332 label = "cpas";
333 arch-compat = "cpas_top";
334 status = "ok";
335 reg-names = "cam_cpas_top", "cam_camnoc";
336 reg = <0xac40000 0x1000>,
337 <0xac42000 0x5000>;
338 reg-cam-base = <0x40000 0x42000>;
339 interrupt-names = "cpas_camnoc";
340 interrupts = <0 459 0>;
341 regulator-names = "camss-vdd";
342 camss-vdd-supply = <&titan_top_gdsc>;
343 clock-names = "gcc_ahb_clk",
344 "gcc_axi_clk",
345 "soc_ahb_clk",
346 "cpas_ahb_clk",
347 "slow_ahb_clk_src",
348 "camnoc_axi_clk";
349 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
350 <&clock_gcc GCC_CAMERA_AXI_CLK>,
351 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
352 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
353 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
354 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
355 src-clock-name = "slow_ahb_clk_src";
356 clock-rates = <0 0 0 0 80000000 0>;
357 qcom,msm-bus,name = "cam_ahb";
358 qcom,msm-bus,num-cases = <4>;
359 qcom,msm-bus,num-paths = <1>;
360 qcom,msm-bus,vectors-KBps =
361 <MSM_BUS_MASTER_AMPSS_M0
362 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
363 <MSM_BUS_MASTER_AMPSS_M0
364 MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
365 <MSM_BUS_MASTER_AMPSS_M0
366 MSM_BUS_SLAVE_CAMERA_CFG 0 640000>,
367 <MSM_BUS_MASTER_AMPSS_M0
368 MSM_BUS_SLAVE_CAMERA_CFG 0 640000>;
369 client-id-based;
370 client-names =
371 "csiphy0", "csiphy1", "csiphy2", "cci0",
Pavan Kumar Chilamkurthi4e070ba2017-05-12 14:47:04 -0700372 "csid0", "csid1", "csid2",
Pavan Kumar Chilamkurthib6aa86d2017-05-01 23:47:11 -0700373 "ife0", "ife1", "ife2", "ipe0",
374 "ipe1", "cam-cdm-intf0", "cpas-cdm0", "bps0",
375 "icp0", "jpeg-dma0", "jpeg0", "fd0";
376 client-axi-port-names =
377 "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1",
Pavan Kumar Chilamkurthi4e070ba2017-05-12 14:47:04 -0700378 "cam_hf_1", "cam_hf_2", "cam_hf_2",
Pavan Kumar Chilamkurthib6aa86d2017-05-01 23:47:11 -0700379 "cam_hf_1", "cam_hf_2", "cam_hf_2", "cam_sf_1",
380 "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1",
381 "cam_sf_1", "cam_sf_1", "cam_sf_1", "cam_sf_1";
382 client-bus-camnoc-based;
383 qcom,axi-port-list {
384 qcom,axi-port1 {
385 qcom,axi-port-name = "cam_hf_1";
386 qcom,axi-port-mnoc {
387 qcom,msm-bus,name = "cam_hf_1_mnoc";
388 qcom,msm-bus-vector-dyn-vote;
389 qcom,msm-bus,num-cases = <2>;
390 qcom,msm-bus,num-paths = <1>;
391 qcom,msm-bus,vectors-KBps =
392 <MSM_BUS_MASTER_CAMNOC_HF
393 MSM_BUS_SLAVE_EBI_CH0 0 0>,
394 <MSM_BUS_MASTER_CAMNOC_HF
395 MSM_BUS_SLAVE_EBI_CH0 0 0>;
396 };
397 qcom,axi-port-camnoc {
398 qcom,msm-bus,name = "cam_hf_1_camnoc";
399 qcom,msm-bus-vector-dyn-vote;
400 qcom,msm-bus,num-cases = <2>;
401 qcom,msm-bus,num-paths = <1>;
402 qcom,msm-bus,vectors-KBps =
403 <MSM_BUS_MASTER_CAMNOC_HF
404 MSM_BUS_SLAVE_EBI_CH0 0 0>,
405 <MSM_BUS_MASTER_CAMNOC_HF
406 MSM_BUS_SLAVE_EBI_CH0 0 0>;
407 };
408 };
409 qcom,axi-port2 {
410 qcom,axi-port-name = "cam_hf_2";
411 qcom,axi-port-mnoc {
412 qcom,msm-bus,name = "cam_hf_2_mnoc";
413 qcom,msm-bus-vector-dyn-vote;
414 qcom,msm-bus,num-cases = <2>;
415 qcom,msm-bus,num-paths = <1>;
416 qcom,msm-bus,vectors-KBps =
417 <MSM_BUS_MASTER_CAMNOC_HF
418 MSM_BUS_SLAVE_EBI_CH0 0 0>,
419 <MSM_BUS_MASTER_CAMNOC_HF
420 MSM_BUS_SLAVE_EBI_CH0 0 0>;
421 };
422 qcom,axi-port-camnoc {
423 qcom,msm-bus,name = "cam_hf_1_camnoc";
424 qcom,msm-bus-vector-dyn-vote;
425 qcom,msm-bus,num-cases = <2>;
426 qcom,msm-bus,num-paths = <1>;
427 qcom,msm-bus,vectors-KBps =
428 <MSM_BUS_MASTER_CAMNOC_HF
429 MSM_BUS_SLAVE_EBI_CH0 0 0>,
430 <MSM_BUS_MASTER_CAMNOC_HF
431 MSM_BUS_SLAVE_EBI_CH0 0 0>;
432 };
433 };
434 qcom,axi-port3 {
435 qcom,axi-port-name = "cam_sf_1";
436 qcom,axi-port-mnoc {
437 qcom,msm-bus,name = "cam_sf_1_mnoc";
438 qcom,msm-bus-vector-dyn-vote;
439 qcom,msm-bus,num-cases = <2>;
440 qcom,msm-bus,num-paths = <1>;
441 qcom,msm-bus,vectors-KBps =
442 <MSM_BUS_MASTER_CAMNOC_SF
443 MSM_BUS_SLAVE_EBI_CH0 0 0>,
444 <MSM_BUS_MASTER_CAMNOC_SF
445 MSM_BUS_SLAVE_EBI_CH0 0 0>;
446 };
447 qcom,axi-port-camnoc {
448 qcom,msm-bus,name = "cam_sf_1_camnoc";
449 qcom,msm-bus-vector-dyn-vote;
450 qcom,msm-bus,num-cases = <2>;
451 qcom,msm-bus,num-paths = <1>;
452 qcom,msm-bus,vectors-KBps =
453 <MSM_BUS_MASTER_CAMNOC_SF
454 MSM_BUS_SLAVE_EBI_CH0 0 0>,
455 <MSM_BUS_MASTER_CAMNOC_SF
456 MSM_BUS_SLAVE_EBI_CH0 0 0>;
457 };
458 };
459 };
460 };
Hariram Purushothamane87b44e02017-03-29 13:53:01 -0700461
462 qcom,cam-cdm-intf {
463 compatible = "qcom,cam-cdm-intf";
464 cell-index = <0>;
465 label = "cam-cdm-intf";
466 num-hw-cdm = <1>;
Hariram Purushothaman91c8cb52017-04-24 21:53:36 -0700467 cdm-client-names = "vfe",
Hariram Purushothamane87b44e02017-03-29 13:53:01 -0700468 "jpeg-dma",
469 "jpeg",
470 "fd";
471 status = "ok";
472 };
473
474 qcom,cpas-cdm0@ac48000 {
475 cell-index = <0>;
476 compatible = "qcom,cam170-cpas-cdm0";
477 label = "cpas-cdm";
478 reg = <0xac48000 0x1000>;
479 reg-names = "cpas-cdm";
480 reg-cam-base = <0x48000>;
481 interrupts = <0 461 0>;
482 interrupt-names = "cpas-cdm";
483 regulator-names = "camss";
484 camss-supply = <&titan_top_gdsc>;
485 clock-names = "gcc_camera_ahb",
486 "gcc_camera_axi",
487 "cam_cc_soc_ahb_clk",
488 "cam_cc_cpas_ahb_clk",
489 "cam_cc_camnoc_axi_clk";
490 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
491 <&clock_gcc GCC_CAMERA_AXI_CLK>,
492 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
493 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
494 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
495 clock-rates = <0 0 0 0 0>;
Hariram Purushothaman91c8cb52017-04-24 21:53:36 -0700496 cdm-client-names = "ife";
Hariram Purushothamane87b44e02017-03-29 13:53:01 -0700497 status = "ok";
498 };
Jing Zhoud4020692017-02-09 15:16:49 -0800499
500 qcom,cam-isp {
501 compatible = "qcom,cam-isp";
502 arch-compat = "ife";
503 status = "ok";
504 };
505
506 qcom,csid0@acb3000 {
507 cell-index = <0>;
508 compatible = "qcom,csid170";
509 reg-names = "csid";
510 reg = <0xacb3000 0x1000>;
511 reg-cam-base = <0xb3000>;
512 interrupt-names = "csid";
513 interrupts = <0 464 0>;
514 regulator-names = "camss", "ife0";
515 camss-supply = <&titan_top_gdsc>;
516 ife0-supply = <&ife_0_gdsc>;
517 clock-names = "camera_ahb",
518 "camera_axi",
519 "soc_ahb_clk",
520 "cpas_ahb_clk",
521 "slow_ahb_clk_src",
522 "ife_csid_clk",
523 "ife_csid_clk_src",
524 "ife_cphy_rx_clk",
525 "cphy_rx_clk_src",
526 "ife_clk",
527 "ife_clk_src",
528 "camnoc_axi_clk",
529 "ife_axi_clk";
530 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
531 <&clock_gcc GCC_CAMERA_AXI_CLK>,
532 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
533 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
534 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
535 <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
536 <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
537 <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
538 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
539 <&clock_camcc CAM_CC_IFE_0_CLK>,
540 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
541 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
542 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
Harsh Shahff6bc352017-05-16 18:03:08 -0700543 clock-rates = <0 0 0 0 0 0 500000000 0 0 0 60000000 0 0>;
Jing Zhoud4020692017-02-09 15:16:49 -0800544 src-clock-name = "ife_csid_clk_src";
545 status = "ok";
546 };
547
548 qcom,vfe0@acaf000 {
549 cell-index = <0>;
550 compatible = "qcom,vfe170";
551 reg-names = "ife";
552 reg = <0xacaf000 0x4000>;
553 reg-cam-base = <0xaf000>;
554 interrupt-names = "ife";
555 interrupts = <0 465 0>;
556 regulator-names = "camss", "ife0";
557 camss-supply = <&titan_top_gdsc>;
558 ife0-supply = <&ife_0_gdsc>;
559 clock-names = "camera_ahb",
560 "camera_axi",
561 "soc_ahb_clk",
562 "cpas_ahb_clk",
563 "slow_ahb_clk_src",
564 "ife_clk",
565 "ife_clk_src",
566 "camnoc_axi_clk",
567 "ife_axi_clk";
568 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
569 <&clock_gcc GCC_CAMERA_AXI_CLK>,
570 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
571 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
572 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
573 <&clock_camcc CAM_CC_IFE_0_CLK>,
574 <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
575 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
576 <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
Harsh Shahff6bc352017-05-16 18:03:08 -0700577 clock-rates = <0 0 0 0 0 0 600000000 0 0>;
Jing Zhoud4020692017-02-09 15:16:49 -0800578 src-clock-name = "ife_clk_src";
579 clock-names-option = "ife_dsp_clk";
580 clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;
581 clock-rates-option = <404000000>;
582 status = "ok";
583 };
584
585 qcom,csid1@acba000 {
586 cell-index = <1>;
587 compatible = "qcom,csid170";
588 reg-names = "csid";
589 reg = <0xacba000 0x1000>;
590 reg-cam-base = <0xba000>;
591 interrupt-names = "csid";
592 interrupts = <0 466 0>;
593 regulator-names = "camss", "ife1";
594 camss-supply = <&titan_top_gdsc>;
595 ife1-supply = <&ife_1_gdsc>;
596 clock-names = "camera_ahb",
597 "camera_axi",
598 "soc_ahb_clk",
599 "cpas_ahb_clk",
600 "slow_ahb_clk_src",
601 "ife_csid_clk",
602 "ife_csid_clk_src",
603 "ife_cphy_rx_clk",
604 "cphy_rx_clk_src",
605 "ife_clk",
606 "ife_clk_src",
607 "camnoc_axi_clk",
608 "ife_axi_clk";
609 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
610 <&clock_gcc GCC_CAMERA_AXI_CLK>,
611 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
612 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
613 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
614 <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
615 <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
616 <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
617 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
618 <&clock_camcc CAM_CC_IFE_1_CLK>,
619 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
620 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
621 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
Harsh Shahff6bc352017-05-16 18:03:08 -0700622 clock-rates = <0 0 0 0 0 0 500000000 0 0 0 60000000 0 0>;
Jing Zhoud4020692017-02-09 15:16:49 -0800623 src-clock-name = "ife_csid_clk_src";
624 status = "ok";
625 };
626
627 qcom,vfe1@acb6000 {
628 cell-index = <1>;
629 compatible = "qcom,vfe170";
630 reg-names = "ife";
631 reg = <0xacb6000 0x4000>;
632 reg-cam-base = <0xb6000>;
633 interrupt-names = "ife";
634 interrupts = <0 467 0>;
635 regulator-names = "camss", "ife1";
636 camss-supply = <&titan_top_gdsc>;
637 ife1-supply = <&ife_1_gdsc>;
638 clock-names = "camera_ahb",
639 "camera_axi",
640 "soc_ahb_clk",
641 "cpas_ahb_clk",
642 "slow_ahb_clk_src",
643 "ife_clk",
644 "ife_clk_src",
645 "camnoc_axi_clk",
646 "ife_axi_clk";
647 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
648 <&clock_gcc GCC_CAMERA_AXI_CLK>,
649 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
650 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
651 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
652 <&clock_camcc CAM_CC_IFE_1_CLK>,
653 <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
654 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
655 <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
Harsh Shahff6bc352017-05-16 18:03:08 -0700656 clock-rates = <0 0 0 0 0 0 600000000 0 0>;
Jing Zhoud4020692017-02-09 15:16:49 -0800657 src-clock-name = "ife_clk_src";
658 clock-names-option = "ife_dsp_clk";
659 clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;
660 clock-rates-option = <404000000>;
661 status = "ok";
662 };
663
664 qcom,csid-lite@acc8000 {
665 cell-index = <2>;
666 compatible = "qcom,csid-lite170";
667 reg-names = "csid-lite";
668 reg = <0xacc8000 0x1000>;
669 reg-cam-base = <0xc8000>;
670 interrupt-names = "csid-lite";
671 interrupts = <0 468 0>;
672 regulator-names = "camss";
673 camss-supply = <&titan_top_gdsc>;
674 clock-names = "camera_ahb",
675 "camera_axi",
676 "soc_ahb_clk",
677 "cpas_ahb_clk",
678 "slow_ahb_clk_src",
679 "ife_csid_clk",
680 "ife_csid_clk_src",
681 "ife_cphy_rx_clk",
682 "cphy_rx_clk_src",
683 "ife_clk",
684 "ife_clk_src",
685 "camnoc_axi_clk";
686 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
687 <&clock_gcc GCC_CAMERA_AXI_CLK>,
688 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
689 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
690 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
691 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
692 <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
693 <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
694 <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
695 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
696 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
697 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
698 clock-rates = <0 0 0 0 0 0 384000000 0 0 0 40400000 0>;
699 src-clock-name = "ife_csid_clk_src";
700 status = "ok";
701 };
702
703 qcom,vfe-lite@acc4000 {
704 cell-index = <2>;
705 compatible = "qcom,vfe-lite170";
706 reg-names = "ife-lite";
707 reg = <0xacc4000 0x4000>;
708 reg-cam-base = <0xc4000>;
709 interrupt-names = "ife-lite";
710 interrupts = <0 469 0>;
711 regulator-names = "camss";
712 camss-supply = <&titan_top_gdsc>;
713 clock-names = "camera_ahb",
714 "camera_axi",
715 "soc_ahb_clk",
716 "cpas_ahb_clk",
717 "slow_ahb_clk_src",
718 "ife_clk",
719 "ife_clk_src",
720 "camnoc_axi_clk";
721 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
722 <&clock_gcc GCC_CAMERA_AXI_CLK>,
723 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
724 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
725 <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
726 <&clock_camcc CAM_CC_IFE_LITE_CLK>,
727 <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
728 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
729 qcom,clock-rates = <0 0 0 0 0 0 404000000 0>;
730 src-clock-name = "ife_clk_src";
731 status = "ok";
732 };
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700733
734 qcom,cam-icp {
735 compatible = "qcom,cam-icp";
736 compat-hw-name = "qcom,a5",
737 "qcom,ipe0",
738 "qcom,ipe1",
739 "qcom,bps";
740 num-a5 = <1>;
741 num-ipe = <2>;
742 num-bps = <1>;
743 status = "ok";
744 };
745
746 qcom,a5@ac00000 {
747 cell-index = <0>;
748 compatible = "qcom,cam_a5";
749 reg = <0xac00000 0x6000>,
750 <0xac10000 0x8000>,
751 <0xac18000 0x3000>;
752 reg-names = "a5_qgic", "a5_sierra", "a5_csr";
753 reg-cam-base = <0x00000 0x10000 0x18000>;
754 interrupts = <0 463 0>;
755 interrupt-names = "a5";
756 regulator-names = "camss-vdd";
757 camss-vdd-supply = <&titan_top_gdsc>;
758 clock-names = "gcc_cam_ahb_clk",
759 "gcc_cam_axi_clk",
760 "soc_ahb_clk",
761 "cpas_ahb_clk",
762 "camnoc_axi_clk",
763 "icp_apb_clk",
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700764 "icp_clk",
Lakshmi Narayana Kalavalae5f367a2017-05-25 11:36:18 -0700765 "icp_clk_src";
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700766 clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>,
767 <&clock_gcc GCC_CAMERA_AXI_CLK>,
768 <&clock_camcc CAM_CC_SOC_AHB_CLK>,
769 <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
770 <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>,
771 <&clock_camcc CAM_CC_ICP_APB_CLK>,
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700772 <&clock_camcc CAM_CC_ICP_CLK>,
Lakshmi Narayana Kalavalae5f367a2017-05-25 11:36:18 -0700773 <&clock_camcc CAM_CC_ICP_CLK_SRC>;
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700774
Lakshmi Narayana Kalavalae5f367a2017-05-25 11:36:18 -0700775 clock-rates = <0 0 0 80000000 0 0 0 600000000>;
Hariram Purushothaman71b8d632017-05-15 14:49:59 -0700776 fw_name = "CAMERA_ICP.elf";
777 status = "ok";
778 };
779
780 qcom,ipe0 {
781 cell-index = <0>;
782 compatible = "qcom,cam_ipe";
783 regulator-names = "ipe0-vdd";
784 ipe0-vdd-supply = <&ipe_0_gdsc>;
785 clock-names = "ipe_0_ahb_clk",
786 "ipe_0_areg_clk",
787 "ipe_0_axi_clk",
788 "ipe_0_clk",
789 "ipe_0_clk_src";
790 clocks = <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
791 <&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
792 <&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
793 <&clock_camcc CAM_CC_IPE_0_CLK>,
794 <&clock_camcc CAM_CC_IPE_0_CLK_SRC>;
795
796 clock-rates = <80000000 400000000 0 0 600000000>;
797 status = "ok";
798 };
799
800 qcom,ipe1 {
801 cell-index = <1>;
802 compatible = "qcom,cam_ipe";
803 regulator-names = "ipe1-vdd";
804 ipe1-vdd-supply = <&ipe_1_gdsc>;
805 clock-names = "ipe_1_ahb_clk",
806 "ipe_1_areg_clk",
807 "ipe_1_axi_clk",
808 "ipe_1_clk",
809 "ipe_1_clk_src";
810 clocks = <&clock_camcc CAM_CC_IPE_1_AHB_CLK>,
811 <&clock_camcc CAM_CC_IPE_1_AREG_CLK>,
812 <&clock_camcc CAM_CC_IPE_1_AXI_CLK>,
813 <&clock_camcc CAM_CC_IPE_1_CLK>,
814 <&clock_camcc CAM_CC_IPE_1_CLK_SRC>;
815
816 clock-rates = <80000000 400000000 0 0 600000000>;
817 status = "ok";
818 };
819
820 qcom,bps {
821 cell-index = <0>;
822 compatible = "qcom,cam_bps";
823 regulator-names = "bps-vdd";
824 bps-vdd-supply = <&bps_gdsc>;
825 clock-names = "bps_ahb_clk",
826 "bps_areg_clk",
827 "bps_axi_clk",
828 "bps_clk",
829 "bps_clk_src";
830 clocks = <&clock_camcc CAM_CC_BPS_AHB_CLK>,
831 <&clock_camcc CAM_CC_BPS_AREG_CLK>,
832 <&clock_camcc CAM_CC_BPS_AXI_CLK>,
833 <&clock_camcc CAM_CC_BPS_CLK>,
834 <&clock_camcc CAM_CC_BPS_CLK_SRC>;
835
836 clock-rates = <80000000 400000000 0 0 600000000>;
837 status = "ok";
838 };
Lakshmi Narayana Kalavalac0dac062016-12-01 17:20:09 -0800839};