viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-spear3xx/spear310.c |
| 3 | * |
| 4 | * SPEAr310 machine source file |
| 5 | * |
| 6 | * Copyright (C) 2009 ST Microelectronics |
| 7 | * Viresh Kumar<viresh.kumar@st.com> |
| 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public |
| 10 | * License version 2. This program is licensed "as is" without any |
| 11 | * warranty of any kind, whether express or implied. |
| 12 | */ |
| 13 | |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 14 | #define pr_fmt(fmt) "SPEAr310: " fmt |
| 15 | |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 16 | #include <linux/ptrace.h> |
| 17 | #include <asm/irq.h> |
viresh kumar | 410782b | 2011-03-07 05:57:01 +0100 | [diff] [blame] | 18 | #include <plat/shirq.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 19 | #include <mach/generic.h> |
viresh kumar | 02aa06b | 2011-03-07 05:57:02 +0100 | [diff] [blame] | 20 | #include <mach/hardware.h> |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 21 | |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 22 | /* pad multiplexing support */ |
| 23 | /* muxing registers */ |
| 24 | #define PAD_MUX_CONFIG_REG 0x08 |
| 25 | |
| 26 | /* devices */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 27 | static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 28 | { |
| 29 | .ids = 0x00, |
| 30 | .mask = PMX_TIMER_3_4_MASK, |
| 31 | }, |
| 32 | }; |
| 33 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 34 | struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 35 | .name = "emi_cs_0_1_4_5", |
| 36 | .modes = pmx_emi_cs_0_1_4_5_modes, |
| 37 | .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes), |
| 38 | .enb_on_reset = 1, |
| 39 | }; |
| 40 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 41 | static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 42 | { |
| 43 | .ids = 0x00, |
| 44 | .mask = PMX_TIMER_1_2_MASK, |
| 45 | }, |
| 46 | }; |
| 47 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 48 | struct pmx_dev spear310_pmx_emi_cs_2_3 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 49 | .name = "emi_cs_2_3", |
| 50 | .modes = pmx_emi_cs_2_3_modes, |
| 51 | .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes), |
| 52 | .enb_on_reset = 1, |
| 53 | }; |
| 54 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 55 | static struct pmx_dev_mode pmx_uart1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 56 | { |
| 57 | .ids = 0x00, |
| 58 | .mask = PMX_FIRDA_MASK, |
| 59 | }, |
| 60 | }; |
| 61 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 62 | struct pmx_dev spear310_pmx_uart1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 63 | .name = "uart1", |
| 64 | .modes = pmx_uart1_modes, |
| 65 | .mode_count = ARRAY_SIZE(pmx_uart1_modes), |
| 66 | .enb_on_reset = 1, |
| 67 | }; |
| 68 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 69 | static struct pmx_dev_mode pmx_uart2_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 70 | { |
| 71 | .ids = 0x00, |
| 72 | .mask = PMX_TIMER_1_2_MASK, |
| 73 | }, |
| 74 | }; |
| 75 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 76 | struct pmx_dev spear310_pmx_uart2 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 77 | .name = "uart2", |
| 78 | .modes = pmx_uart2_modes, |
| 79 | .mode_count = ARRAY_SIZE(pmx_uart2_modes), |
| 80 | .enb_on_reset = 1, |
| 81 | }; |
| 82 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 83 | static struct pmx_dev_mode pmx_uart3_4_5_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 84 | { |
| 85 | .ids = 0x00, |
| 86 | .mask = PMX_UART0_MODEM_MASK, |
| 87 | }, |
| 88 | }; |
| 89 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 90 | struct pmx_dev spear310_pmx_uart3_4_5 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 91 | .name = "uart3_4_5", |
| 92 | .modes = pmx_uart3_4_5_modes, |
| 93 | .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes), |
| 94 | .enb_on_reset = 1, |
| 95 | }; |
| 96 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 97 | static struct pmx_dev_mode pmx_fsmc_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 98 | { |
| 99 | .ids = 0x00, |
| 100 | .mask = PMX_SSP_CS_MASK, |
| 101 | }, |
| 102 | }; |
| 103 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 104 | struct pmx_dev spear310_pmx_fsmc = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 105 | .name = "fsmc", |
| 106 | .modes = pmx_fsmc_modes, |
| 107 | .mode_count = ARRAY_SIZE(pmx_fsmc_modes), |
| 108 | .enb_on_reset = 1, |
| 109 | }; |
| 110 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 111 | static struct pmx_dev_mode pmx_rs485_0_1_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 112 | { |
| 113 | .ids = 0x00, |
| 114 | .mask = PMX_MII_MASK, |
| 115 | }, |
| 116 | }; |
| 117 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 118 | struct pmx_dev spear310_pmx_rs485_0_1 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 119 | .name = "rs485_0_1", |
| 120 | .modes = pmx_rs485_0_1_modes, |
| 121 | .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes), |
| 122 | .enb_on_reset = 1, |
| 123 | }; |
| 124 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 125 | static struct pmx_dev_mode pmx_tdm0_modes[] = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 126 | { |
| 127 | .ids = 0x00, |
| 128 | .mask = PMX_MII_MASK, |
| 129 | }, |
| 130 | }; |
| 131 | |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 132 | struct pmx_dev spear310_pmx_tdm0 = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 133 | .name = "tdm0", |
| 134 | .modes = pmx_tdm0_modes, |
| 135 | .mode_count = ARRAY_SIZE(pmx_tdm0_modes), |
| 136 | .enb_on_reset = 1, |
| 137 | }; |
| 138 | |
| 139 | /* pmx driver structure */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 140 | static struct pmx_driver pmx_driver = { |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 141 | .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff}, |
| 142 | }; |
| 143 | |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 144 | /* spear3xx shared irq */ |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 145 | static struct shirq_dev_config shirq_ras1_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 146 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 147 | .virq = SPEAR310_VIRQ_SMII0, |
| 148 | .status_mask = SPEAR310_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 149 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 150 | .virq = SPEAR310_VIRQ_SMII1, |
| 151 | .status_mask = SPEAR310_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 152 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 153 | .virq = SPEAR310_VIRQ_SMII2, |
| 154 | .status_mask = SPEAR310_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 155 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 156 | .virq = SPEAR310_VIRQ_SMII3, |
| 157 | .status_mask = SPEAR310_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 158 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 159 | .virq = SPEAR310_VIRQ_WAKEUP_SMII0, |
| 160 | .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 161 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 162 | .virq = SPEAR310_VIRQ_WAKEUP_SMII1, |
| 163 | .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 164 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 165 | .virq = SPEAR310_VIRQ_WAKEUP_SMII2, |
| 166 | .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 167 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 168 | .virq = SPEAR310_VIRQ_WAKEUP_SMII3, |
| 169 | .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 170 | }, |
| 171 | }; |
| 172 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 173 | static struct spear_shirq shirq_ras1 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 174 | .irq = SPEAR3XX_IRQ_GEN_RAS_1, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 175 | .dev_config = shirq_ras1_config, |
| 176 | .dev_count = ARRAY_SIZE(shirq_ras1_config), |
| 177 | .regs = { |
| 178 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 179 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 180 | .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 181 | .clear_reg = -1, |
| 182 | }, |
| 183 | }; |
| 184 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 185 | static struct shirq_dev_config shirq_ras2_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 186 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 187 | .virq = SPEAR310_VIRQ_UART1, |
| 188 | .status_mask = SPEAR310_UART1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 189 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 190 | .virq = SPEAR310_VIRQ_UART2, |
| 191 | .status_mask = SPEAR310_UART2_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 192 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 193 | .virq = SPEAR310_VIRQ_UART3, |
| 194 | .status_mask = SPEAR310_UART3_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 195 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 196 | .virq = SPEAR310_VIRQ_UART4, |
| 197 | .status_mask = SPEAR310_UART4_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 198 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 199 | .virq = SPEAR310_VIRQ_UART5, |
| 200 | .status_mask = SPEAR310_UART5_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 201 | }, |
| 202 | }; |
| 203 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 204 | static struct spear_shirq shirq_ras2 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 205 | .irq = SPEAR3XX_IRQ_GEN_RAS_2, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 206 | .dev_config = shirq_ras2_config, |
| 207 | .dev_count = ARRAY_SIZE(shirq_ras2_config), |
| 208 | .regs = { |
| 209 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 210 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 211 | .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 212 | .clear_reg = -1, |
| 213 | }, |
| 214 | }; |
| 215 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 216 | static struct shirq_dev_config shirq_ras3_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 217 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 218 | .virq = SPEAR310_VIRQ_EMI, |
| 219 | .status_mask = SPEAR310_EMI_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 220 | }, |
| 221 | }; |
| 222 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 223 | static struct spear_shirq shirq_ras3 = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 224 | .irq = SPEAR3XX_IRQ_GEN_RAS_3, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 225 | .dev_config = shirq_ras3_config, |
| 226 | .dev_count = ARRAY_SIZE(shirq_ras3_config), |
| 227 | .regs = { |
| 228 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 229 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 230 | .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 231 | .clear_reg = -1, |
| 232 | }, |
| 233 | }; |
| 234 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 235 | static struct shirq_dev_config shirq_intrcomm_ras_config[] = { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 236 | { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 237 | .virq = SPEAR310_VIRQ_TDM_HDLC, |
| 238 | .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 239 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 240 | .virq = SPEAR310_VIRQ_RS485_0, |
| 241 | .status_mask = SPEAR310_RS485_0_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 242 | }, { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 243 | .virq = SPEAR310_VIRQ_RS485_1, |
| 244 | .status_mask = SPEAR310_RS485_1_IRQ_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 245 | }, |
| 246 | }; |
| 247 | |
Ryan Mallon | f6558bf | 2011-05-20 08:34:20 +0100 | [diff] [blame] | 248 | static struct spear_shirq shirq_intrcomm_ras = { |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 249 | .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 250 | .dev_config = shirq_intrcomm_ras_config, |
| 251 | .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config), |
| 252 | .regs = { |
| 253 | .enb_reg = -1, |
Ryan Mallon | 61e72bc | 2011-05-20 08:34:21 +0100 | [diff] [blame] | 254 | .status_reg = SPEAR310_INT_STS_MASK_REG, |
| 255 | .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK, |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 256 | .clear_reg = -1, |
| 257 | }, |
| 258 | }; |
| 259 | |
viresh kumar | c2c0783 | 2011-03-07 05:57:05 +0100 | [diff] [blame] | 260 | /* Add spear310 specific devices here */ |
| 261 | |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 262 | /* spear310 routines */ |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 263 | void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs, |
| 264 | u8 pmx_dev_count) |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 265 | { |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 266 | void __iomem *base; |
| 267 | int ret = 0; |
| 268 | |
viresh kumar | bc4e814 | 2010-04-01 12:30:58 +0100 | [diff] [blame] | 269 | /* call spear3xx family common init function */ |
| 270 | spear3xx_init(); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 271 | |
Uwe Kleine-König | b595076 | 2010-11-01 15:38:34 -0400 | [diff] [blame] | 272 | /* shared irq registration */ |
viresh kumar | 5382116 | 2011-03-07 05:57:06 +0100 | [diff] [blame] | 273 | base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 274 | if (base) { |
| 275 | /* shirq 1 */ |
| 276 | shirq_ras1.regs.base = base; |
| 277 | ret = spear_shirq_register(&shirq_ras1); |
| 278 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 279 | pr_err("Error registering Shared IRQ 1\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 280 | |
| 281 | /* shirq 2 */ |
| 282 | shirq_ras2.regs.base = base; |
| 283 | ret = spear_shirq_register(&shirq_ras2); |
| 284 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 285 | pr_err("Error registering Shared IRQ 2\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 286 | |
| 287 | /* shirq 3 */ |
| 288 | shirq_ras3.regs.base = base; |
| 289 | ret = spear_shirq_register(&shirq_ras3); |
| 290 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 291 | pr_err("Error registering Shared IRQ 3\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 292 | |
| 293 | /* shirq 4 */ |
| 294 | shirq_intrcomm_ras.regs.base = base; |
| 295 | ret = spear_shirq_register(&shirq_intrcomm_ras); |
| 296 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 297 | pr_err("Error registering Shared IRQ 4\n"); |
viresh kumar | 4c18e77 | 2010-05-03 09:24:30 +0100 | [diff] [blame] | 298 | } |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 299 | |
viresh kumar | 53688c5 | 2011-02-16 07:40:30 +0100 | [diff] [blame] | 300 | /* pmx initialization */ |
| 301 | pmx_driver.base = base; |
Ryan Mallon | 6618c3a | 2011-05-20 08:34:22 +0100 | [diff] [blame] | 302 | pmx_driver.mode = pmx_mode; |
| 303 | pmx_driver.devs = pmx_devs; |
| 304 | pmx_driver.devs_count = pmx_dev_count; |
| 305 | |
viresh kumar | 53688c5 | 2011-02-16 07:40:30 +0100 | [diff] [blame] | 306 | ret = pmx_register(&pmx_driver); |
| 307 | if (ret) |
Viresh Kumar | 5fb00f9 | 2012-03-26 10:39:43 +0530 | [diff] [blame^] | 308 | pr_err("padmux: registration failed. err no: %d\n", ret); |
viresh kumar | 70f4c0b | 2010-04-01 12:31:29 +0100 | [diff] [blame] | 309 | } |