blob: b7c28764df92a48ad64ae9a307950620a6c9a304 [file] [log] [blame]
viresh kumarbc4e8142010-04-01 12:30:58 +01001/*
2 * arch/arm/mach-spear3xx/spear310.c
3 *
4 * SPEAr310 machine source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
Viresh Kumar5fb00f92012-03-26 10:39:43 +053014#define pr_fmt(fmt) "SPEAr310: " fmt
15
viresh kumarbc4e8142010-04-01 12:30:58 +010016#include <linux/ptrace.h>
17#include <asm/irq.h>
viresh kumar410782b2011-03-07 05:57:01 +010018#include <plat/shirq.h>
viresh kumarbc4e8142010-04-01 12:30:58 +010019#include <mach/generic.h>
viresh kumar02aa06b2011-03-07 05:57:02 +010020#include <mach/hardware.h>
viresh kumarbc4e8142010-04-01 12:30:58 +010021
viresh kumar70f4c0b2010-04-01 12:31:29 +010022/* pad multiplexing support */
23/* muxing registers */
24#define PAD_MUX_CONFIG_REG 0x08
25
26/* devices */
Ryan Mallon6618c3a2011-05-20 08:34:22 +010027static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010028 {
29 .ids = 0x00,
30 .mask = PMX_TIMER_3_4_MASK,
31 },
32};
33
Ryan Mallon6618c3a2011-05-20 08:34:22 +010034struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010035 .name = "emi_cs_0_1_4_5",
36 .modes = pmx_emi_cs_0_1_4_5_modes,
37 .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
38 .enb_on_reset = 1,
39};
40
Ryan Mallon6618c3a2011-05-20 08:34:22 +010041static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010042 {
43 .ids = 0x00,
44 .mask = PMX_TIMER_1_2_MASK,
45 },
46};
47
Ryan Mallon6618c3a2011-05-20 08:34:22 +010048struct pmx_dev spear310_pmx_emi_cs_2_3 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010049 .name = "emi_cs_2_3",
50 .modes = pmx_emi_cs_2_3_modes,
51 .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
52 .enb_on_reset = 1,
53};
54
Ryan Mallon6618c3a2011-05-20 08:34:22 +010055static struct pmx_dev_mode pmx_uart1_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010056 {
57 .ids = 0x00,
58 .mask = PMX_FIRDA_MASK,
59 },
60};
61
Ryan Mallon6618c3a2011-05-20 08:34:22 +010062struct pmx_dev spear310_pmx_uart1 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010063 .name = "uart1",
64 .modes = pmx_uart1_modes,
65 .mode_count = ARRAY_SIZE(pmx_uart1_modes),
66 .enb_on_reset = 1,
67};
68
Ryan Mallon6618c3a2011-05-20 08:34:22 +010069static struct pmx_dev_mode pmx_uart2_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010070 {
71 .ids = 0x00,
72 .mask = PMX_TIMER_1_2_MASK,
73 },
74};
75
Ryan Mallon6618c3a2011-05-20 08:34:22 +010076struct pmx_dev spear310_pmx_uart2 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010077 .name = "uart2",
78 .modes = pmx_uart2_modes,
79 .mode_count = ARRAY_SIZE(pmx_uart2_modes),
80 .enb_on_reset = 1,
81};
82
Ryan Mallon6618c3a2011-05-20 08:34:22 +010083static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010084 {
85 .ids = 0x00,
86 .mask = PMX_UART0_MODEM_MASK,
87 },
88};
89
Ryan Mallon6618c3a2011-05-20 08:34:22 +010090struct pmx_dev spear310_pmx_uart3_4_5 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010091 .name = "uart3_4_5",
92 .modes = pmx_uart3_4_5_modes,
93 .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
94 .enb_on_reset = 1,
95};
96
Ryan Mallon6618c3a2011-05-20 08:34:22 +010097static struct pmx_dev_mode pmx_fsmc_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +010098 {
99 .ids = 0x00,
100 .mask = PMX_SSP_CS_MASK,
101 },
102};
103
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100104struct pmx_dev spear310_pmx_fsmc = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100105 .name = "fsmc",
106 .modes = pmx_fsmc_modes,
107 .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
108 .enb_on_reset = 1,
109};
110
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100111static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100112 {
113 .ids = 0x00,
114 .mask = PMX_MII_MASK,
115 },
116};
117
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100118struct pmx_dev spear310_pmx_rs485_0_1 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100119 .name = "rs485_0_1",
120 .modes = pmx_rs485_0_1_modes,
121 .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
122 .enb_on_reset = 1,
123};
124
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100125static struct pmx_dev_mode pmx_tdm0_modes[] = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100126 {
127 .ids = 0x00,
128 .mask = PMX_MII_MASK,
129 },
130};
131
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100132struct pmx_dev spear310_pmx_tdm0 = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100133 .name = "tdm0",
134 .modes = pmx_tdm0_modes,
135 .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
136 .enb_on_reset = 1,
137};
138
139/* pmx driver structure */
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100140static struct pmx_driver pmx_driver = {
viresh kumar70f4c0b2010-04-01 12:31:29 +0100141 .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
142};
143
viresh kumar4c18e772010-05-03 09:24:30 +0100144/* spear3xx shared irq */
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100145static struct shirq_dev_config shirq_ras1_config[] = {
viresh kumar4c18e772010-05-03 09:24:30 +0100146 {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100147 .virq = SPEAR310_VIRQ_SMII0,
148 .status_mask = SPEAR310_SMII0_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100149 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100150 .virq = SPEAR310_VIRQ_SMII1,
151 .status_mask = SPEAR310_SMII1_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100152 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100153 .virq = SPEAR310_VIRQ_SMII2,
154 .status_mask = SPEAR310_SMII2_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100155 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100156 .virq = SPEAR310_VIRQ_SMII3,
157 .status_mask = SPEAR310_SMII3_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100158 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100159 .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
160 .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100161 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100162 .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
163 .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100164 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100165 .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
166 .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100167 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100168 .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
169 .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100170 },
171};
172
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100173static struct spear_shirq shirq_ras1 = {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100174 .irq = SPEAR3XX_IRQ_GEN_RAS_1,
viresh kumar4c18e772010-05-03 09:24:30 +0100175 .dev_config = shirq_ras1_config,
176 .dev_count = ARRAY_SIZE(shirq_ras1_config),
177 .regs = {
178 .enb_reg = -1,
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100179 .status_reg = SPEAR310_INT_STS_MASK_REG,
180 .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100181 .clear_reg = -1,
182 },
183};
184
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100185static struct shirq_dev_config shirq_ras2_config[] = {
viresh kumar4c18e772010-05-03 09:24:30 +0100186 {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100187 .virq = SPEAR310_VIRQ_UART1,
188 .status_mask = SPEAR310_UART1_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100189 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100190 .virq = SPEAR310_VIRQ_UART2,
191 .status_mask = SPEAR310_UART2_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100192 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100193 .virq = SPEAR310_VIRQ_UART3,
194 .status_mask = SPEAR310_UART3_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100195 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100196 .virq = SPEAR310_VIRQ_UART4,
197 .status_mask = SPEAR310_UART4_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100198 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100199 .virq = SPEAR310_VIRQ_UART5,
200 .status_mask = SPEAR310_UART5_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100201 },
202};
203
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100204static struct spear_shirq shirq_ras2 = {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100205 .irq = SPEAR3XX_IRQ_GEN_RAS_2,
viresh kumar4c18e772010-05-03 09:24:30 +0100206 .dev_config = shirq_ras2_config,
207 .dev_count = ARRAY_SIZE(shirq_ras2_config),
208 .regs = {
209 .enb_reg = -1,
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100210 .status_reg = SPEAR310_INT_STS_MASK_REG,
211 .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100212 .clear_reg = -1,
213 },
214};
215
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100216static struct shirq_dev_config shirq_ras3_config[] = {
viresh kumar4c18e772010-05-03 09:24:30 +0100217 {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100218 .virq = SPEAR310_VIRQ_EMI,
219 .status_mask = SPEAR310_EMI_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100220 },
221};
222
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100223static struct spear_shirq shirq_ras3 = {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100224 .irq = SPEAR3XX_IRQ_GEN_RAS_3,
viresh kumar4c18e772010-05-03 09:24:30 +0100225 .dev_config = shirq_ras3_config,
226 .dev_count = ARRAY_SIZE(shirq_ras3_config),
227 .regs = {
228 .enb_reg = -1,
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100229 .status_reg = SPEAR310_INT_STS_MASK_REG,
230 .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100231 .clear_reg = -1,
232 },
233};
234
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100235static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
viresh kumar4c18e772010-05-03 09:24:30 +0100236 {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100237 .virq = SPEAR310_VIRQ_TDM_HDLC,
238 .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100239 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100240 .virq = SPEAR310_VIRQ_RS485_0,
241 .status_mask = SPEAR310_RS485_0_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100242 }, {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100243 .virq = SPEAR310_VIRQ_RS485_1,
244 .status_mask = SPEAR310_RS485_1_IRQ_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100245 },
246};
247
Ryan Mallonf6558bf2011-05-20 08:34:20 +0100248static struct spear_shirq shirq_intrcomm_ras = {
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100249 .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
viresh kumar4c18e772010-05-03 09:24:30 +0100250 .dev_config = shirq_intrcomm_ras_config,
251 .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
252 .regs = {
253 .enb_reg = -1,
Ryan Mallon61e72bc2011-05-20 08:34:21 +0100254 .status_reg = SPEAR310_INT_STS_MASK_REG,
255 .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
viresh kumar4c18e772010-05-03 09:24:30 +0100256 .clear_reg = -1,
257 },
258};
259
viresh kumarc2c07832011-03-07 05:57:05 +0100260/* Add spear310 specific devices here */
261
viresh kumar70f4c0b2010-04-01 12:31:29 +0100262/* spear310 routines */
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100263void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
264 u8 pmx_dev_count)
viresh kumarbc4e8142010-04-01 12:30:58 +0100265{
viresh kumar4c18e772010-05-03 09:24:30 +0100266 void __iomem *base;
267 int ret = 0;
268
viresh kumarbc4e8142010-04-01 12:30:58 +0100269 /* call spear3xx family common init function */
270 spear3xx_init();
viresh kumar4c18e772010-05-03 09:24:30 +0100271
Uwe Kleine-Königb5950762010-11-01 15:38:34 -0400272 /* shared irq registration */
viresh kumar53821162011-03-07 05:57:06 +0100273 base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
viresh kumar4c18e772010-05-03 09:24:30 +0100274 if (base) {
275 /* shirq 1 */
276 shirq_ras1.regs.base = base;
277 ret = spear_shirq_register(&shirq_ras1);
278 if (ret)
Viresh Kumar5fb00f92012-03-26 10:39:43 +0530279 pr_err("Error registering Shared IRQ 1\n");
viresh kumar4c18e772010-05-03 09:24:30 +0100280
281 /* shirq 2 */
282 shirq_ras2.regs.base = base;
283 ret = spear_shirq_register(&shirq_ras2);
284 if (ret)
Viresh Kumar5fb00f92012-03-26 10:39:43 +0530285 pr_err("Error registering Shared IRQ 2\n");
viresh kumar4c18e772010-05-03 09:24:30 +0100286
287 /* shirq 3 */
288 shirq_ras3.regs.base = base;
289 ret = spear_shirq_register(&shirq_ras3);
290 if (ret)
Viresh Kumar5fb00f92012-03-26 10:39:43 +0530291 pr_err("Error registering Shared IRQ 3\n");
viresh kumar4c18e772010-05-03 09:24:30 +0100292
293 /* shirq 4 */
294 shirq_intrcomm_ras.regs.base = base;
295 ret = spear_shirq_register(&shirq_intrcomm_ras);
296 if (ret)
Viresh Kumar5fb00f92012-03-26 10:39:43 +0530297 pr_err("Error registering Shared IRQ 4\n");
viresh kumar4c18e772010-05-03 09:24:30 +0100298 }
viresh kumar70f4c0b2010-04-01 12:31:29 +0100299
viresh kumar53688c52011-02-16 07:40:30 +0100300 /* pmx initialization */
301 pmx_driver.base = base;
Ryan Mallon6618c3a2011-05-20 08:34:22 +0100302 pmx_driver.mode = pmx_mode;
303 pmx_driver.devs = pmx_devs;
304 pmx_driver.devs_count = pmx_dev_count;
305
viresh kumar53688c52011-02-16 07:40:30 +0100306 ret = pmx_register(&pmx_driver);
307 if (ret)
Viresh Kumar5fb00f92012-03-26 10:39:43 +0530308 pr_err("padmux: registration failed. err no: %d\n", ret);
viresh kumar70f4c0b2010-04-01 12:31:29 +0100309}