Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1 | /* |
| 2 | * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. |
| 3 | * |
| 4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
| 20 | #include <linux/completion.h> |
| 21 | #include <linux/delay.h> |
| 22 | #include <linux/dmaengine.h> |
| 23 | #include <linux/dma-mapping.h> |
| 24 | #include <linux/dmapool.h> |
| 25 | #include <linux/err.h> |
| 26 | #include <linux/init.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/kernel.h> |
| 30 | #include <linux/kthread.h> |
| 31 | #include <linux/module.h> |
| 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/pm_runtime.h> |
| 34 | #include <linux/of.h> |
| 35 | #include <linux/of_device.h> |
| 36 | #include <linux/spi/spi.h> |
Prashant Gaikwad | 61fd290 | 2013-01-11 13:16:26 +0530 | [diff] [blame] | 37 | #include <linux/clk/tegra.h> |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 38 | |
| 39 | #define SLINK_COMMAND 0x000 |
| 40 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) |
| 41 | #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) |
| 42 | #define SLINK_BOTH_EN (1 << 10) |
| 43 | #define SLINK_CS_SW (1 << 11) |
| 44 | #define SLINK_CS_VALUE (1 << 12) |
| 45 | #define SLINK_CS_POLARITY (1 << 13) |
| 46 | #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) |
| 47 | #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) |
| 48 | #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) |
| 49 | #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) |
| 50 | #define SLINK_IDLE_SDA_MASK (3 << 16) |
| 51 | #define SLINK_CS_POLARITY1 (1 << 20) |
| 52 | #define SLINK_CK_SDA (1 << 21) |
| 53 | #define SLINK_CS_POLARITY2 (1 << 22) |
| 54 | #define SLINK_CS_POLARITY3 (1 << 23) |
| 55 | #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) |
| 56 | #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) |
| 57 | #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) |
| 58 | #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) |
| 59 | #define SLINK_IDLE_SCLK_MASK (3 << 24) |
| 60 | #define SLINK_M_S (1 << 28) |
| 61 | #define SLINK_WAIT (1 << 29) |
| 62 | #define SLINK_GO (1 << 30) |
| 63 | #define SLINK_ENB (1 << 31) |
| 64 | |
| 65 | #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) |
| 66 | |
| 67 | #define SLINK_COMMAND2 0x004 |
| 68 | #define SLINK_LSBFE (1 << 0) |
| 69 | #define SLINK_SSOE (1 << 1) |
| 70 | #define SLINK_SPIE (1 << 4) |
| 71 | #define SLINK_BIDIROE (1 << 6) |
| 72 | #define SLINK_MODFEN (1 << 7) |
| 73 | #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) |
| 74 | #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) |
| 75 | #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) |
| 76 | #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) |
| 77 | #define SLINK_FIFO_REFILLS_0 (0 << 22) |
| 78 | #define SLINK_FIFO_REFILLS_1 (1 << 22) |
| 79 | #define SLINK_FIFO_REFILLS_2 (2 << 22) |
| 80 | #define SLINK_FIFO_REFILLS_3 (3 << 22) |
| 81 | #define SLINK_FIFO_REFILLS_MASK (3 << 22) |
| 82 | #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) |
| 83 | #define SLINK_SPC0 (1 << 29) |
| 84 | #define SLINK_TXEN (1 << 30) |
| 85 | #define SLINK_RXEN (1 << 31) |
| 86 | |
| 87 | #define SLINK_STATUS 0x008 |
| 88 | #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) |
| 89 | #define SLINK_WORD(val) (((val) >> 5) & 0x1f) |
| 90 | #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) |
| 91 | #define SLINK_MODF (1 << 16) |
| 92 | #define SLINK_RX_UNF (1 << 18) |
| 93 | #define SLINK_TX_OVF (1 << 19) |
| 94 | #define SLINK_TX_FULL (1 << 20) |
| 95 | #define SLINK_TX_EMPTY (1 << 21) |
| 96 | #define SLINK_RX_FULL (1 << 22) |
| 97 | #define SLINK_RX_EMPTY (1 << 23) |
| 98 | #define SLINK_TX_UNF (1 << 24) |
| 99 | #define SLINK_RX_OVF (1 << 25) |
| 100 | #define SLINK_TX_FLUSH (1 << 26) |
| 101 | #define SLINK_RX_FLUSH (1 << 27) |
| 102 | #define SLINK_SCLK (1 << 28) |
| 103 | #define SLINK_ERR (1 << 29) |
| 104 | #define SLINK_RDY (1 << 30) |
| 105 | #define SLINK_BSY (1 << 31) |
| 106 | #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ |
| 107 | SLINK_TX_UNF | SLINK_RX_OVF) |
| 108 | |
| 109 | #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) |
| 110 | |
| 111 | #define SLINK_MAS_DATA 0x010 |
| 112 | #define SLINK_SLAVE_DATA 0x014 |
| 113 | |
| 114 | #define SLINK_DMA_CTL 0x018 |
| 115 | #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) |
| 116 | #define SLINK_TX_TRIG_1 (0 << 16) |
| 117 | #define SLINK_TX_TRIG_4 (1 << 16) |
| 118 | #define SLINK_TX_TRIG_8 (2 << 16) |
| 119 | #define SLINK_TX_TRIG_16 (3 << 16) |
| 120 | #define SLINK_TX_TRIG_MASK (3 << 16) |
| 121 | #define SLINK_RX_TRIG_1 (0 << 18) |
| 122 | #define SLINK_RX_TRIG_4 (1 << 18) |
| 123 | #define SLINK_RX_TRIG_8 (2 << 18) |
| 124 | #define SLINK_RX_TRIG_16 (3 << 18) |
| 125 | #define SLINK_RX_TRIG_MASK (3 << 18) |
| 126 | #define SLINK_PACKED (1 << 20) |
| 127 | #define SLINK_PACK_SIZE_4 (0 << 21) |
| 128 | #define SLINK_PACK_SIZE_8 (1 << 21) |
| 129 | #define SLINK_PACK_SIZE_16 (2 << 21) |
| 130 | #define SLINK_PACK_SIZE_32 (3 << 21) |
| 131 | #define SLINK_PACK_SIZE_MASK (3 << 21) |
| 132 | #define SLINK_IE_TXC (1 << 26) |
| 133 | #define SLINK_IE_RXC (1 << 27) |
| 134 | #define SLINK_DMA_EN (1 << 31) |
| 135 | |
| 136 | #define SLINK_STATUS2 0x01c |
| 137 | #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) |
| 138 | #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) |
| 139 | #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) |
| 140 | |
| 141 | #define SLINK_TX_FIFO 0x100 |
| 142 | #define SLINK_RX_FIFO 0x180 |
| 143 | |
| 144 | #define DATA_DIR_TX (1 << 0) |
| 145 | #define DATA_DIR_RX (1 << 1) |
| 146 | |
| 147 | #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) |
| 148 | |
| 149 | #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) |
| 150 | #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) |
| 151 | #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) |
| 152 | |
| 153 | #define SLINK_STATUS2_RESET \ |
| 154 | (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) |
| 155 | |
| 156 | #define MAX_CHIP_SELECT 4 |
| 157 | #define SLINK_FIFO_DEPTH 32 |
| 158 | |
| 159 | struct tegra_slink_chip_data { |
| 160 | bool cs_hold_time; |
| 161 | }; |
| 162 | |
| 163 | struct tegra_slink_data { |
| 164 | struct device *dev; |
| 165 | struct spi_master *master; |
| 166 | const struct tegra_slink_chip_data *chip_data; |
| 167 | spinlock_t lock; |
| 168 | |
| 169 | struct clk *clk; |
| 170 | void __iomem *base; |
| 171 | phys_addr_t phys; |
| 172 | unsigned irq; |
| 173 | int dma_req_sel; |
| 174 | u32 spi_max_frequency; |
| 175 | u32 cur_speed; |
| 176 | |
| 177 | struct spi_device *cur_spi; |
| 178 | unsigned cur_pos; |
| 179 | unsigned cur_len; |
| 180 | unsigned words_per_32bit; |
| 181 | unsigned bytes_per_word; |
| 182 | unsigned curr_dma_words; |
| 183 | unsigned cur_direction; |
| 184 | |
| 185 | unsigned cur_rx_pos; |
| 186 | unsigned cur_tx_pos; |
| 187 | |
| 188 | unsigned dma_buf_size; |
| 189 | unsigned max_buf_size; |
| 190 | bool is_curr_dma_xfer; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 191 | |
| 192 | struct completion rx_dma_complete; |
| 193 | struct completion tx_dma_complete; |
| 194 | |
| 195 | u32 tx_status; |
| 196 | u32 rx_status; |
| 197 | u32 status_reg; |
| 198 | bool is_packed; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 199 | u32 packed_size; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 200 | |
| 201 | u32 command_reg; |
| 202 | u32 command2_reg; |
| 203 | u32 dma_control_reg; |
| 204 | u32 def_command_reg; |
| 205 | u32 def_command2_reg; |
| 206 | |
| 207 | struct completion xfer_completion; |
| 208 | struct spi_transfer *curr_xfer; |
| 209 | struct dma_chan *rx_dma_chan; |
| 210 | u32 *rx_dma_buf; |
| 211 | dma_addr_t rx_dma_phys; |
| 212 | struct dma_async_tx_descriptor *rx_dma_desc; |
| 213 | |
| 214 | struct dma_chan *tx_dma_chan; |
| 215 | u32 *tx_dma_buf; |
| 216 | dma_addr_t tx_dma_phys; |
| 217 | struct dma_async_tx_descriptor *tx_dma_desc; |
| 218 | }; |
| 219 | |
| 220 | static int tegra_slink_runtime_suspend(struct device *dev); |
| 221 | static int tegra_slink_runtime_resume(struct device *dev); |
| 222 | |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 223 | static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 224 | unsigned long reg) |
| 225 | { |
| 226 | return readl(tspi->base + reg); |
| 227 | } |
| 228 | |
| 229 | static inline void tegra_slink_writel(struct tegra_slink_data *tspi, |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 230 | u32 val, unsigned long reg) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 231 | { |
| 232 | writel(val, tspi->base + reg); |
| 233 | |
| 234 | /* Read back register to make sure that register writes completed */ |
| 235 | if (reg != SLINK_TX_FIFO) |
| 236 | readl(tspi->base + SLINK_MAS_DATA); |
| 237 | } |
| 238 | |
| 239 | static void tegra_slink_clear_status(struct tegra_slink_data *tspi) |
| 240 | { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 241 | u32 val_write; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 242 | |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 243 | tegra_slink_readl(tspi, SLINK_STATUS); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 244 | |
| 245 | /* Write 1 to clear status register */ |
| 246 | val_write = SLINK_RDY | SLINK_FIFO_ERROR; |
| 247 | tegra_slink_writel(tspi, val_write, SLINK_STATUS); |
| 248 | } |
| 249 | |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 250 | static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 251 | struct spi_transfer *t) |
| 252 | { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 253 | switch (tspi->bytes_per_word) { |
| 254 | case 0: |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 255 | return SLINK_PACK_SIZE_4; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 256 | case 1: |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 257 | return SLINK_PACK_SIZE_8; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 258 | case 2: |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 259 | return SLINK_PACK_SIZE_16; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 260 | case 4: |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 261 | return SLINK_PACK_SIZE_32; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 262 | default: |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 263 | return 0; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 264 | } |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | static unsigned tegra_slink_calculate_curr_xfer_param( |
| 268 | struct spi_device *spi, struct tegra_slink_data *tspi, |
| 269 | struct spi_transfer *t) |
| 270 | { |
| 271 | unsigned remain_len = t->len - tspi->cur_pos; |
| 272 | unsigned max_word; |
Jingoo Han | 3cb7b40 | 2013-10-14 10:36:10 +0900 | [diff] [blame] | 273 | unsigned bits_per_word; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 274 | unsigned max_len; |
| 275 | unsigned total_fifo_words; |
| 276 | |
Laxman Dewangan | 766ed70 | 2012-12-18 14:25:43 +0530 | [diff] [blame] | 277 | bits_per_word = t->bits_per_word; |
Axel Lin | e91d235 | 2013-08-30 11:00:23 +0800 | [diff] [blame] | 278 | tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 279 | |
| 280 | if (bits_per_word == 8 || bits_per_word == 16) { |
| 281 | tspi->is_packed = 1; |
| 282 | tspi->words_per_32bit = 32/bits_per_word; |
| 283 | } else { |
| 284 | tspi->is_packed = 0; |
| 285 | tspi->words_per_32bit = 1; |
| 286 | } |
| 287 | tspi->packed_size = tegra_slink_get_packed_size(tspi, t); |
| 288 | |
| 289 | if (tspi->is_packed) { |
| 290 | max_len = min(remain_len, tspi->max_buf_size); |
| 291 | tspi->curr_dma_words = max_len/tspi->bytes_per_word; |
| 292 | total_fifo_words = max_len/4; |
| 293 | } else { |
| 294 | max_word = (remain_len - 1) / tspi->bytes_per_word + 1; |
| 295 | max_word = min(max_word, tspi->max_buf_size/4); |
| 296 | tspi->curr_dma_words = max_word; |
| 297 | total_fifo_words = max_word; |
| 298 | } |
| 299 | return total_fifo_words; |
| 300 | } |
| 301 | |
| 302 | static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( |
| 303 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 304 | { |
| 305 | unsigned nbytes; |
| 306 | unsigned tx_empty_count; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 307 | u32 fifo_status; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 308 | unsigned max_n_32bit; |
| 309 | unsigned i, count; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 310 | unsigned int written_words; |
| 311 | unsigned fifo_words_left; |
| 312 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; |
| 313 | |
| 314 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); |
| 315 | tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); |
| 316 | |
| 317 | if (tspi->is_packed) { |
| 318 | fifo_words_left = tx_empty_count * tspi->words_per_32bit; |
| 319 | written_words = min(fifo_words_left, tspi->curr_dma_words); |
| 320 | nbytes = written_words * tspi->bytes_per_word; |
| 321 | max_n_32bit = DIV_ROUND_UP(nbytes, 4); |
| 322 | for (count = 0; count < max_n_32bit; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 323 | u32 x = 0; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 324 | for (i = 0; (i < 4) && nbytes; i++, nbytes--) |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 325 | x |= (u32)(*tx_buf++) << (i * 8); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 326 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); |
| 327 | } |
| 328 | } else { |
| 329 | max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); |
| 330 | written_words = max_n_32bit; |
| 331 | nbytes = written_words * tspi->bytes_per_word; |
| 332 | for (count = 0; count < max_n_32bit; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 333 | u32 x = 0; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 334 | for (i = 0; nbytes && (i < tspi->bytes_per_word); |
| 335 | i++, nbytes--) |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 336 | x |= (u32)(*tx_buf++) << (i * 8); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 337 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); |
| 338 | } |
| 339 | } |
| 340 | tspi->cur_tx_pos += written_words * tspi->bytes_per_word; |
| 341 | return written_words; |
| 342 | } |
| 343 | |
| 344 | static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( |
| 345 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 346 | { |
| 347 | unsigned rx_full_count; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 348 | u32 fifo_status; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 349 | unsigned i, count; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 350 | unsigned int read_words = 0; |
| 351 | unsigned len; |
| 352 | u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; |
| 353 | |
| 354 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); |
| 355 | rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); |
| 356 | if (tspi->is_packed) { |
| 357 | len = tspi->curr_dma_words * tspi->bytes_per_word; |
| 358 | for (count = 0; count < rx_full_count; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 359 | u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 360 | for (i = 0; len && (i < 4); i++, len--) |
| 361 | *rx_buf++ = (x >> i*8) & 0xFF; |
| 362 | } |
| 363 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; |
| 364 | read_words += tspi->curr_dma_words; |
| 365 | } else { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 366 | for (count = 0; count < rx_full_count; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 367 | u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 368 | for (i = 0; (i < tspi->bytes_per_word); i++) |
| 369 | *rx_buf++ = (x >> (i*8)) & 0xFF; |
| 370 | } |
| 371 | tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; |
| 372 | read_words += rx_full_count; |
| 373 | } |
| 374 | return read_words; |
| 375 | } |
| 376 | |
| 377 | static void tegra_slink_copy_client_txbuf_to_spi_txbuf( |
| 378 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 379 | { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 380 | /* Make the dma buffer to read by cpu */ |
| 381 | dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, |
| 382 | tspi->dma_buf_size, DMA_TO_DEVICE); |
| 383 | |
| 384 | if (tspi->is_packed) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 385 | unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 386 | memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); |
| 387 | } else { |
| 388 | unsigned int i; |
| 389 | unsigned int count; |
| 390 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; |
| 391 | unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 392 | |
| 393 | for (count = 0; count < tspi->curr_dma_words; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 394 | u32 x = 0; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 395 | for (i = 0; consume && (i < tspi->bytes_per_word); |
| 396 | i++, consume--) |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 397 | x |= (u32)(*tx_buf++) << (i * 8); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 398 | tspi->tx_dma_buf[count] = x; |
| 399 | } |
| 400 | } |
| 401 | tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; |
| 402 | |
| 403 | /* Make the dma buffer to read by dma */ |
| 404 | dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, |
| 405 | tspi->dma_buf_size, DMA_TO_DEVICE); |
| 406 | } |
| 407 | |
| 408 | static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( |
| 409 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 410 | { |
| 411 | unsigned len; |
| 412 | |
| 413 | /* Make the dma buffer to read by cpu */ |
| 414 | dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, |
| 415 | tspi->dma_buf_size, DMA_FROM_DEVICE); |
| 416 | |
| 417 | if (tspi->is_packed) { |
| 418 | len = tspi->curr_dma_words * tspi->bytes_per_word; |
| 419 | memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); |
| 420 | } else { |
| 421 | unsigned int i; |
| 422 | unsigned int count; |
| 423 | unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 424 | u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 425 | |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 426 | for (count = 0; count < tspi->curr_dma_words; count++) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 427 | u32 x = tspi->rx_dma_buf[count] & rx_mask; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 428 | for (i = 0; (i < tspi->bytes_per_word); i++) |
| 429 | *rx_buf++ = (x >> (i*8)) & 0xFF; |
| 430 | } |
| 431 | } |
| 432 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; |
| 433 | |
| 434 | /* Make the dma buffer to read by dma */ |
| 435 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, |
| 436 | tspi->dma_buf_size, DMA_FROM_DEVICE); |
| 437 | } |
| 438 | |
| 439 | static void tegra_slink_dma_complete(void *args) |
| 440 | { |
| 441 | struct completion *dma_complete = args; |
| 442 | |
| 443 | complete(dma_complete); |
| 444 | } |
| 445 | |
| 446 | static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) |
| 447 | { |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 448 | reinit_completion(&tspi->tx_dma_complete); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 449 | tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, |
| 450 | tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, |
Mark Brown | 72919f3 | 2013-04-03 18:30:31 +0100 | [diff] [blame] | 451 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 452 | if (!tspi->tx_dma_desc) { |
| 453 | dev_err(tspi->dev, "Not able to get desc for Tx\n"); |
| 454 | return -EIO; |
| 455 | } |
| 456 | |
| 457 | tspi->tx_dma_desc->callback = tegra_slink_dma_complete; |
| 458 | tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; |
| 459 | |
| 460 | dmaengine_submit(tspi->tx_dma_desc); |
| 461 | dma_async_issue_pending(tspi->tx_dma_chan); |
| 462 | return 0; |
| 463 | } |
| 464 | |
| 465 | static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) |
| 466 | { |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 467 | reinit_completion(&tspi->rx_dma_complete); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 468 | tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, |
| 469 | tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, |
Mark Brown | 72919f3 | 2013-04-03 18:30:31 +0100 | [diff] [blame] | 470 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 471 | if (!tspi->rx_dma_desc) { |
| 472 | dev_err(tspi->dev, "Not able to get desc for Rx\n"); |
| 473 | return -EIO; |
| 474 | } |
| 475 | |
| 476 | tspi->rx_dma_desc->callback = tegra_slink_dma_complete; |
| 477 | tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; |
| 478 | |
| 479 | dmaengine_submit(tspi->rx_dma_desc); |
| 480 | dma_async_issue_pending(tspi->rx_dma_chan); |
| 481 | return 0; |
| 482 | } |
| 483 | |
| 484 | static int tegra_slink_start_dma_based_transfer( |
| 485 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 486 | { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 487 | u32 val; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 488 | unsigned int len; |
| 489 | int ret = 0; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 490 | u32 status; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 491 | |
| 492 | /* Make sure that Rx and Tx fifo are empty */ |
| 493 | status = tegra_slink_readl(tspi, SLINK_STATUS); |
| 494 | if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 495 | dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", |
| 496 | (unsigned)status); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 497 | return -EIO; |
| 498 | } |
| 499 | |
| 500 | val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); |
| 501 | val |= tspi->packed_size; |
| 502 | if (tspi->is_packed) |
| 503 | len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, |
| 504 | 4) * 4; |
| 505 | else |
| 506 | len = tspi->curr_dma_words * 4; |
| 507 | |
| 508 | /* Set attention level based on length of transfer */ |
| 509 | if (len & 0xF) |
| 510 | val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; |
| 511 | else if (((len) >> 4) & 0x1) |
| 512 | val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; |
| 513 | else |
| 514 | val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; |
| 515 | |
| 516 | if (tspi->cur_direction & DATA_DIR_TX) |
| 517 | val |= SLINK_IE_TXC; |
| 518 | |
| 519 | if (tspi->cur_direction & DATA_DIR_RX) |
| 520 | val |= SLINK_IE_RXC; |
| 521 | |
| 522 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 523 | tspi->dma_control_reg = val; |
| 524 | |
| 525 | if (tspi->cur_direction & DATA_DIR_TX) { |
| 526 | tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); |
| 527 | wmb(); |
| 528 | ret = tegra_slink_start_tx_dma(tspi, len); |
| 529 | if (ret < 0) { |
| 530 | dev_err(tspi->dev, |
| 531 | "Starting tx dma failed, err %d\n", ret); |
| 532 | return ret; |
| 533 | } |
| 534 | |
| 535 | /* Wait for tx fifo to be fill before starting slink */ |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 536 | status = tegra_slink_readl(tspi, SLINK_STATUS); |
| 537 | while (!(status & SLINK_TX_FULL)) |
| 538 | status = tegra_slink_readl(tspi, SLINK_STATUS); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 539 | } |
| 540 | |
| 541 | if (tspi->cur_direction & DATA_DIR_RX) { |
| 542 | /* Make the dma buffer to read by dma */ |
| 543 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, |
| 544 | tspi->dma_buf_size, DMA_FROM_DEVICE); |
| 545 | |
| 546 | ret = tegra_slink_start_rx_dma(tspi, len); |
| 547 | if (ret < 0) { |
| 548 | dev_err(tspi->dev, |
| 549 | "Starting rx dma failed, err %d\n", ret); |
| 550 | if (tspi->cur_direction & DATA_DIR_TX) |
| 551 | dmaengine_terminate_all(tspi->tx_dma_chan); |
| 552 | return ret; |
| 553 | } |
| 554 | } |
| 555 | tspi->is_curr_dma_xfer = true; |
| 556 | if (tspi->is_packed) { |
| 557 | val |= SLINK_PACKED; |
| 558 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 559 | /* HW need small delay after settign Packed mode */ |
| 560 | udelay(1); |
| 561 | } |
| 562 | tspi->dma_control_reg = val; |
| 563 | |
| 564 | val |= SLINK_DMA_EN; |
| 565 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 566 | return ret; |
| 567 | } |
| 568 | |
| 569 | static int tegra_slink_start_cpu_based_transfer( |
| 570 | struct tegra_slink_data *tspi, struct spi_transfer *t) |
| 571 | { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 572 | u32 val; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 573 | unsigned cur_words; |
| 574 | |
| 575 | val = tspi->packed_size; |
| 576 | if (tspi->cur_direction & DATA_DIR_TX) |
| 577 | val |= SLINK_IE_TXC; |
| 578 | |
| 579 | if (tspi->cur_direction & DATA_DIR_RX) |
| 580 | val |= SLINK_IE_RXC; |
| 581 | |
| 582 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 583 | tspi->dma_control_reg = val; |
| 584 | |
| 585 | if (tspi->cur_direction & DATA_DIR_TX) |
| 586 | cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); |
| 587 | else |
| 588 | cur_words = tspi->curr_dma_words; |
| 589 | val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); |
| 590 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 591 | tspi->dma_control_reg = val; |
| 592 | |
| 593 | tspi->is_curr_dma_xfer = false; |
| 594 | if (tspi->is_packed) { |
| 595 | val |= SLINK_PACKED; |
| 596 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 597 | udelay(1); |
| 598 | wmb(); |
| 599 | } |
| 600 | tspi->dma_control_reg = val; |
| 601 | val |= SLINK_DMA_EN; |
| 602 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); |
| 603 | return 0; |
| 604 | } |
| 605 | |
| 606 | static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, |
| 607 | bool dma_to_memory) |
| 608 | { |
| 609 | struct dma_chan *dma_chan; |
| 610 | u32 *dma_buf; |
| 611 | dma_addr_t dma_phys; |
| 612 | int ret; |
| 613 | struct dma_slave_config dma_sconfig; |
| 614 | dma_cap_mask_t mask; |
| 615 | |
| 616 | dma_cap_zero(mask); |
| 617 | dma_cap_set(DMA_SLAVE, mask); |
| 618 | dma_chan = dma_request_channel(mask, NULL, NULL); |
| 619 | if (!dma_chan) { |
| 620 | dev_err(tspi->dev, |
| 621 | "Dma channel is not available, will try later\n"); |
| 622 | return -EPROBE_DEFER; |
| 623 | } |
| 624 | |
| 625 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, |
| 626 | &dma_phys, GFP_KERNEL); |
| 627 | if (!dma_buf) { |
| 628 | dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); |
| 629 | dma_release_channel(dma_chan); |
| 630 | return -ENOMEM; |
| 631 | } |
| 632 | |
| 633 | dma_sconfig.slave_id = tspi->dma_req_sel; |
| 634 | if (dma_to_memory) { |
| 635 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; |
| 636 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 637 | dma_sconfig.src_maxburst = 0; |
| 638 | } else { |
| 639 | dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; |
| 640 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
| 641 | dma_sconfig.dst_maxburst = 0; |
| 642 | } |
| 643 | |
| 644 | ret = dmaengine_slave_config(dma_chan, &dma_sconfig); |
| 645 | if (ret) |
| 646 | goto scrub; |
| 647 | if (dma_to_memory) { |
| 648 | tspi->rx_dma_chan = dma_chan; |
| 649 | tspi->rx_dma_buf = dma_buf; |
| 650 | tspi->rx_dma_phys = dma_phys; |
| 651 | } else { |
| 652 | tspi->tx_dma_chan = dma_chan; |
| 653 | tspi->tx_dma_buf = dma_buf; |
| 654 | tspi->tx_dma_phys = dma_phys; |
| 655 | } |
| 656 | return 0; |
| 657 | |
| 658 | scrub: |
| 659 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); |
| 660 | dma_release_channel(dma_chan); |
| 661 | return ret; |
| 662 | } |
| 663 | |
| 664 | static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, |
| 665 | bool dma_to_memory) |
| 666 | { |
| 667 | u32 *dma_buf; |
| 668 | dma_addr_t dma_phys; |
| 669 | struct dma_chan *dma_chan; |
| 670 | |
| 671 | if (dma_to_memory) { |
| 672 | dma_buf = tspi->rx_dma_buf; |
| 673 | dma_chan = tspi->rx_dma_chan; |
| 674 | dma_phys = tspi->rx_dma_phys; |
| 675 | tspi->rx_dma_chan = NULL; |
| 676 | tspi->rx_dma_buf = NULL; |
| 677 | } else { |
| 678 | dma_buf = tspi->tx_dma_buf; |
| 679 | dma_chan = tspi->tx_dma_chan; |
| 680 | dma_phys = tspi->tx_dma_phys; |
| 681 | tspi->tx_dma_buf = NULL; |
| 682 | tspi->tx_dma_chan = NULL; |
| 683 | } |
| 684 | if (!dma_chan) |
| 685 | return; |
| 686 | |
| 687 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); |
| 688 | dma_release_channel(dma_chan); |
| 689 | } |
| 690 | |
| 691 | static int tegra_slink_start_transfer_one(struct spi_device *spi, |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 692 | struct spi_transfer *t) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 693 | { |
| 694 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); |
| 695 | u32 speed; |
| 696 | u8 bits_per_word; |
| 697 | unsigned total_fifo_words; |
| 698 | int ret; |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 699 | u32 command; |
| 700 | u32 command2; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 701 | |
Laxman Dewangan | e6811d1 | 2012-11-09 14:36:45 +0530 | [diff] [blame] | 702 | bits_per_word = t->bits_per_word; |
Laxman Dewangan | beb96c2 | 2013-01-05 00:17:15 +0530 | [diff] [blame] | 703 | speed = t->speed_hz; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 704 | if (speed != tspi->cur_speed) { |
| 705 | clk_set_rate(tspi->clk, speed * 4); |
| 706 | tspi->cur_speed = speed; |
| 707 | } |
| 708 | |
| 709 | tspi->cur_spi = spi; |
| 710 | tspi->cur_pos = 0; |
| 711 | tspi->cur_rx_pos = 0; |
| 712 | tspi->cur_tx_pos = 0; |
| 713 | tspi->curr_xfer = t; |
| 714 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); |
| 715 | |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 716 | command = tspi->command_reg; |
| 717 | command &= ~SLINK_BIT_LENGTH(~0); |
| 718 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 719 | |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 720 | command2 = tspi->command2_reg; |
| 721 | command2 &= ~(SLINK_RXEN | SLINK_TXEN); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 722 | |
| 723 | tegra_slink_writel(tspi, command, SLINK_COMMAND); |
| 724 | tspi->command_reg = command; |
| 725 | |
| 726 | tspi->cur_direction = 0; |
| 727 | if (t->rx_buf) { |
| 728 | command2 |= SLINK_RXEN; |
| 729 | tspi->cur_direction |= DATA_DIR_RX; |
| 730 | } |
| 731 | if (t->tx_buf) { |
| 732 | command2 |= SLINK_TXEN; |
| 733 | tspi->cur_direction |= DATA_DIR_TX; |
| 734 | } |
| 735 | tegra_slink_writel(tspi, command2, SLINK_COMMAND2); |
| 736 | tspi->command2_reg = command2; |
| 737 | |
| 738 | if (total_fifo_words > SLINK_FIFO_DEPTH) |
| 739 | ret = tegra_slink_start_dma_based_transfer(tspi, t); |
| 740 | else |
| 741 | ret = tegra_slink_start_cpu_based_transfer(tspi, t); |
| 742 | return ret; |
| 743 | } |
| 744 | |
| 745 | static int tegra_slink_setup(struct spi_device *spi) |
| 746 | { |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 747 | static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 748 | SLINK_CS_POLARITY, |
| 749 | SLINK_CS_POLARITY1, |
| 750 | SLINK_CS_POLARITY2, |
| 751 | SLINK_CS_POLARITY3, |
| 752 | }; |
| 753 | |
Michal Nazarewicz | 5fd3867 | 2013-12-08 16:35:10 +0100 | [diff] [blame^] | 754 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); |
| 755 | u32 val; |
| 756 | unsigned long flags; |
| 757 | int ret; |
| 758 | |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 759 | dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", |
| 760 | spi->bits_per_word, |
| 761 | spi->mode & SPI_CPOL ? "" : "~", |
| 762 | spi->mode & SPI_CPHA ? "" : "~", |
| 763 | spi->max_speed_hz); |
| 764 | |
| 765 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); |
| 766 | |
Laxman Dewangan | beb96c2 | 2013-01-05 00:17:15 +0530 | [diff] [blame] | 767 | /* Set speed to the spi max fequency if spi device has not set */ |
| 768 | spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 769 | ret = pm_runtime_get_sync(tspi->dev); |
| 770 | if (ret < 0) { |
| 771 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); |
| 772 | return ret; |
| 773 | } |
| 774 | |
| 775 | spin_lock_irqsave(&tspi->lock, flags); |
| 776 | val = tspi->def_command_reg; |
| 777 | if (spi->mode & SPI_CS_HIGH) |
| 778 | val |= cs_pol_bit[spi->chip_select]; |
| 779 | else |
| 780 | val &= ~cs_pol_bit[spi->chip_select]; |
| 781 | tspi->def_command_reg = val; |
| 782 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); |
| 783 | spin_unlock_irqrestore(&tspi->lock, flags); |
| 784 | |
| 785 | pm_runtime_put(tspi->dev); |
| 786 | return 0; |
| 787 | } |
| 788 | |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 789 | static int tegra_slink_prepare_message(struct spi_master *master, |
| 790 | struct spi_message *msg) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 791 | { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 792 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 793 | struct spi_device *spi = msg->spi; |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 794 | |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 795 | tegra_slink_clear_status(tspi); |
| 796 | |
| 797 | tspi->command_reg = tspi->def_command_reg; |
| 798 | tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; |
| 799 | |
| 800 | tspi->command2_reg = tspi->def_command2_reg; |
| 801 | tspi->command2_reg |= SLINK_SS_EN_CS(spi->chip_select); |
| 802 | |
| 803 | tspi->command_reg &= ~SLINK_MODES; |
| 804 | if (spi->mode & SPI_CPHA) |
| 805 | tspi->command_reg |= SLINK_CK_SDA; |
| 806 | |
| 807 | if (spi->mode & SPI_CPOL) |
| 808 | tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; |
| 809 | else |
| 810 | tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 811 | |
| 812 | return 0; |
| 813 | } |
| 814 | |
| 815 | static int tegra_slink_transfer_one(struct spi_master *master, |
| 816 | struct spi_device *spi, |
| 817 | struct spi_transfer *xfer) |
| 818 | { |
| 819 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 820 | int ret; |
| 821 | |
Wolfram Sang | 16735d0 | 2013-11-14 14:32:02 -0800 | [diff] [blame] | 822 | reinit_completion(&tspi->xfer_completion); |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 823 | ret = tegra_slink_start_transfer_one(spi, xfer); |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 824 | if (ret < 0) { |
| 825 | dev_err(tspi->dev, |
| 826 | "spi can not start transfer, err %d\n", ret); |
| 827 | return ret; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 828 | } |
Mark Brown | f178e3d | 2013-10-05 12:30:42 +0100 | [diff] [blame] | 829 | |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 830 | ret = wait_for_completion_timeout(&tspi->xfer_completion, |
| 831 | SLINK_DMA_TIMEOUT); |
| 832 | if (WARN_ON(ret == 0)) { |
| 833 | dev_err(tspi->dev, |
| 834 | "spi trasfer timeout, err %d\n", ret); |
| 835 | return -EIO; |
| 836 | } |
| 837 | |
| 838 | if (tspi->tx_status) |
| 839 | return tspi->tx_status; |
| 840 | if (tspi->rx_status) |
| 841 | return tspi->rx_status; |
| 842 | |
| 843 | return 0; |
| 844 | } |
| 845 | |
| 846 | static int tegra_slink_unprepare_message(struct spi_master *master, |
| 847 | struct spi_message *msg) |
| 848 | { |
| 849 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
| 850 | |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 851 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); |
| 852 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 853 | |
| 854 | return 0; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 855 | } |
| 856 | |
| 857 | static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) |
| 858 | { |
| 859 | struct spi_transfer *t = tspi->curr_xfer; |
| 860 | unsigned long flags; |
| 861 | |
| 862 | spin_lock_irqsave(&tspi->lock, flags); |
| 863 | if (tspi->tx_status || tspi->rx_status || |
| 864 | (tspi->status_reg & SLINK_BSY)) { |
| 865 | dev_err(tspi->dev, |
| 866 | "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); |
| 867 | dev_err(tspi->dev, |
| 868 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
| 869 | tspi->command2_reg, tspi->dma_control_reg); |
| 870 | tegra_periph_reset_assert(tspi->clk); |
| 871 | udelay(2); |
| 872 | tegra_periph_reset_deassert(tspi->clk); |
| 873 | complete(&tspi->xfer_completion); |
| 874 | goto exit; |
| 875 | } |
| 876 | |
| 877 | if (tspi->cur_direction & DATA_DIR_RX) |
| 878 | tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); |
| 879 | |
| 880 | if (tspi->cur_direction & DATA_DIR_TX) |
| 881 | tspi->cur_pos = tspi->cur_tx_pos; |
| 882 | else |
| 883 | tspi->cur_pos = tspi->cur_rx_pos; |
| 884 | |
| 885 | if (tspi->cur_pos == t->len) { |
| 886 | complete(&tspi->xfer_completion); |
| 887 | goto exit; |
| 888 | } |
| 889 | |
| 890 | tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); |
| 891 | tegra_slink_start_cpu_based_transfer(tspi, t); |
| 892 | exit: |
| 893 | spin_unlock_irqrestore(&tspi->lock, flags); |
| 894 | return IRQ_HANDLED; |
| 895 | } |
| 896 | |
| 897 | static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) |
| 898 | { |
| 899 | struct spi_transfer *t = tspi->curr_xfer; |
| 900 | long wait_status; |
| 901 | int err = 0; |
| 902 | unsigned total_fifo_words; |
| 903 | unsigned long flags; |
| 904 | |
| 905 | /* Abort dmas if any error */ |
| 906 | if (tspi->cur_direction & DATA_DIR_TX) { |
| 907 | if (tspi->tx_status) { |
| 908 | dmaengine_terminate_all(tspi->tx_dma_chan); |
| 909 | err += 1; |
| 910 | } else { |
| 911 | wait_status = wait_for_completion_interruptible_timeout( |
| 912 | &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); |
| 913 | if (wait_status <= 0) { |
| 914 | dmaengine_terminate_all(tspi->tx_dma_chan); |
| 915 | dev_err(tspi->dev, "TxDma Xfer failed\n"); |
| 916 | err += 1; |
| 917 | } |
| 918 | } |
| 919 | } |
| 920 | |
| 921 | if (tspi->cur_direction & DATA_DIR_RX) { |
| 922 | if (tspi->rx_status) { |
| 923 | dmaengine_terminate_all(tspi->rx_dma_chan); |
| 924 | err += 2; |
| 925 | } else { |
| 926 | wait_status = wait_for_completion_interruptible_timeout( |
| 927 | &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); |
| 928 | if (wait_status <= 0) { |
| 929 | dmaengine_terminate_all(tspi->rx_dma_chan); |
| 930 | dev_err(tspi->dev, "RxDma Xfer failed\n"); |
| 931 | err += 2; |
| 932 | } |
| 933 | } |
| 934 | } |
| 935 | |
| 936 | spin_lock_irqsave(&tspi->lock, flags); |
| 937 | if (err) { |
| 938 | dev_err(tspi->dev, |
| 939 | "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); |
| 940 | dev_err(tspi->dev, |
| 941 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, |
| 942 | tspi->command2_reg, tspi->dma_control_reg); |
| 943 | tegra_periph_reset_assert(tspi->clk); |
| 944 | udelay(2); |
| 945 | tegra_periph_reset_deassert(tspi->clk); |
| 946 | complete(&tspi->xfer_completion); |
| 947 | spin_unlock_irqrestore(&tspi->lock, flags); |
| 948 | return IRQ_HANDLED; |
| 949 | } |
| 950 | |
| 951 | if (tspi->cur_direction & DATA_DIR_RX) |
| 952 | tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); |
| 953 | |
| 954 | if (tspi->cur_direction & DATA_DIR_TX) |
| 955 | tspi->cur_pos = tspi->cur_tx_pos; |
| 956 | else |
| 957 | tspi->cur_pos = tspi->cur_rx_pos; |
| 958 | |
| 959 | if (tspi->cur_pos == t->len) { |
| 960 | complete(&tspi->xfer_completion); |
| 961 | goto exit; |
| 962 | } |
| 963 | |
| 964 | /* Continue transfer in current message */ |
| 965 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, |
| 966 | tspi, t); |
| 967 | if (total_fifo_words > SLINK_FIFO_DEPTH) |
| 968 | err = tegra_slink_start_dma_based_transfer(tspi, t); |
| 969 | else |
| 970 | err = tegra_slink_start_cpu_based_transfer(tspi, t); |
| 971 | |
| 972 | exit: |
| 973 | spin_unlock_irqrestore(&tspi->lock, flags); |
| 974 | return IRQ_HANDLED; |
| 975 | } |
| 976 | |
| 977 | static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) |
| 978 | { |
| 979 | struct tegra_slink_data *tspi = context_data; |
| 980 | |
| 981 | if (!tspi->is_curr_dma_xfer) |
| 982 | return handle_cpu_based_xfer(tspi); |
| 983 | return handle_dma_based_xfer(tspi); |
| 984 | } |
| 985 | |
| 986 | static irqreturn_t tegra_slink_isr(int irq, void *context_data) |
| 987 | { |
| 988 | struct tegra_slink_data *tspi = context_data; |
| 989 | |
| 990 | tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); |
| 991 | if (tspi->cur_direction & DATA_DIR_TX) |
| 992 | tspi->tx_status = tspi->status_reg & |
| 993 | (SLINK_TX_OVF | SLINK_TX_UNF); |
| 994 | |
| 995 | if (tspi->cur_direction & DATA_DIR_RX) |
| 996 | tspi->rx_status = tspi->status_reg & |
| 997 | (SLINK_RX_OVF | SLINK_RX_UNF); |
| 998 | tegra_slink_clear_status(tspi); |
| 999 | |
| 1000 | return IRQ_WAKE_THREAD; |
| 1001 | } |
| 1002 | |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1003 | static void tegra_slink_parse_dt(struct tegra_slink_data *tspi) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1004 | { |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1005 | struct device_node *np = tspi->dev->of_node; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1006 | u32 of_dma[2]; |
| 1007 | |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1008 | if (of_property_read_u32_array(np, "nvidia,dma-request-selector", |
| 1009 | of_dma, 2) >= 0) |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1010 | tspi->dma_req_sel = of_dma[1]; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1011 | |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1012 | if (of_property_read_u32(np, "spi-max-frequency", |
| 1013 | &tspi->spi_max_frequency)) |
| 1014 | tspi->spi_max_frequency = 25000000; /* 25MHz */ |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1015 | } |
| 1016 | |
Wei Yongjun | 8b0bebe | 2013-04-05 21:45:36 +0800 | [diff] [blame] | 1017 | static const struct tegra_slink_chip_data tegra30_spi_cdata = { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1018 | .cs_hold_time = true, |
| 1019 | }; |
| 1020 | |
Wei Yongjun | 8b0bebe | 2013-04-05 21:45:36 +0800 | [diff] [blame] | 1021 | static const struct tegra_slink_chip_data tegra20_spi_cdata = { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1022 | .cs_hold_time = false, |
| 1023 | }; |
| 1024 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1025 | static struct of_device_id tegra_slink_of_match[] = { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1026 | { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, |
Laxman Dewangan | 24bc897 | 2012-11-09 14:37:32 +0530 | [diff] [blame] | 1027 | { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1028 | {} |
| 1029 | }; |
| 1030 | MODULE_DEVICE_TABLE(of, tegra_slink_of_match); |
| 1031 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1032 | static int tegra_slink_probe(struct platform_device *pdev) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1033 | { |
| 1034 | struct spi_master *master; |
| 1035 | struct tegra_slink_data *tspi; |
| 1036 | struct resource *r; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1037 | int ret, spi_irq; |
| 1038 | const struct tegra_slink_chip_data *cdata = NULL; |
| 1039 | const struct of_device_id *match; |
| 1040 | |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1041 | match = of_match_device(tegra_slink_of_match, &pdev->dev); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1042 | if (!match) { |
| 1043 | dev_err(&pdev->dev, "Error: No device match found\n"); |
| 1044 | return -ENODEV; |
| 1045 | } |
| 1046 | cdata = match->data; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1047 | |
| 1048 | master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); |
| 1049 | if (!master) { |
| 1050 | dev_err(&pdev->dev, "master allocation failed\n"); |
| 1051 | return -ENOMEM; |
| 1052 | } |
| 1053 | |
| 1054 | /* the spi->mode bits understood by this driver: */ |
| 1055 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
| 1056 | master->setup = tegra_slink_setup; |
Mark Brown | 63fc184 | 2013-10-05 12:23:38 +0100 | [diff] [blame] | 1057 | master->prepare_message = tegra_slink_prepare_message; |
| 1058 | master->transfer_one = tegra_slink_transfer_one; |
| 1059 | master->unprepare_message = tegra_slink_unprepare_message; |
Mark Brown | ce74ac8 | 2013-07-28 15:37:59 +0100 | [diff] [blame] | 1060 | master->auto_runtime_pm = true; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1061 | master->num_chipselect = MAX_CHIP_SELECT; |
| 1062 | master->bus_num = -1; |
| 1063 | |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 1064 | platform_set_drvdata(pdev, master); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1065 | tspi = spi_master_get_devdata(master); |
| 1066 | tspi->master = master; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1067 | tspi->dev = &pdev->dev; |
| 1068 | tspi->chip_data = cdata; |
| 1069 | spin_lock_init(&tspi->lock); |
| 1070 | |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1071 | tegra_slink_parse_dt(tspi); |
| 1072 | |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1073 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1074 | if (!r) { |
| 1075 | dev_err(&pdev->dev, "No IO memory resource\n"); |
| 1076 | ret = -ENODEV; |
| 1077 | goto exit_free_master; |
| 1078 | } |
| 1079 | tspi->phys = r->start; |
Thierry Reding | b0ee560 | 2013-01-21 11:09:18 +0100 | [diff] [blame] | 1080 | tspi->base = devm_ioremap_resource(&pdev->dev, r); |
| 1081 | if (IS_ERR(tspi->base)) { |
| 1082 | ret = PTR_ERR(tspi->base); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1083 | goto exit_free_master; |
| 1084 | } |
| 1085 | |
| 1086 | spi_irq = platform_get_irq(pdev, 0); |
| 1087 | tspi->irq = spi_irq; |
| 1088 | ret = request_threaded_irq(tspi->irq, tegra_slink_isr, |
| 1089 | tegra_slink_isr_thread, IRQF_ONESHOT, |
| 1090 | dev_name(&pdev->dev), tspi); |
| 1091 | if (ret < 0) { |
| 1092 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", |
| 1093 | tspi->irq); |
| 1094 | goto exit_free_master; |
| 1095 | } |
| 1096 | |
Prashant Gaikwad | 3cb9190 | 2013-01-11 13:31:20 +0530 | [diff] [blame] | 1097 | tspi->clk = devm_clk_get(&pdev->dev, NULL); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1098 | if (IS_ERR(tspi->clk)) { |
| 1099 | dev_err(&pdev->dev, "can not get clock\n"); |
| 1100 | ret = PTR_ERR(tspi->clk); |
| 1101 | goto exit_free_irq; |
| 1102 | } |
| 1103 | |
| 1104 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; |
| 1105 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1106 | |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1107 | if (tspi->dma_req_sel) { |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1108 | ret = tegra_slink_init_dma_param(tspi, true); |
| 1109 | if (ret < 0) { |
| 1110 | dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); |
| 1111 | goto exit_free_irq; |
| 1112 | } |
| 1113 | |
| 1114 | ret = tegra_slink_init_dma_param(tspi, false); |
| 1115 | if (ret < 0) { |
| 1116 | dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret); |
| 1117 | goto exit_rx_dma_free; |
| 1118 | } |
| 1119 | tspi->max_buf_size = tspi->dma_buf_size; |
| 1120 | init_completion(&tspi->tx_dma_complete); |
| 1121 | init_completion(&tspi->rx_dma_complete); |
| 1122 | } |
| 1123 | |
| 1124 | init_completion(&tspi->xfer_completion); |
| 1125 | |
| 1126 | pm_runtime_enable(&pdev->dev); |
| 1127 | if (!pm_runtime_enabled(&pdev->dev)) { |
| 1128 | ret = tegra_slink_runtime_resume(&pdev->dev); |
| 1129 | if (ret) |
| 1130 | goto exit_pm_disable; |
| 1131 | } |
| 1132 | |
| 1133 | ret = pm_runtime_get_sync(&pdev->dev); |
| 1134 | if (ret < 0) { |
| 1135 | dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); |
| 1136 | goto exit_pm_disable; |
| 1137 | } |
| 1138 | tspi->def_command_reg = SLINK_M_S; |
| 1139 | tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; |
| 1140 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); |
| 1141 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); |
| 1142 | pm_runtime_put(&pdev->dev); |
| 1143 | |
| 1144 | master->dev.of_node = pdev->dev.of_node; |
Jingoo Han | 716db5d | 2013-09-24 13:51:32 +0900 | [diff] [blame] | 1145 | ret = devm_spi_register_master(&pdev->dev, master); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1146 | if (ret < 0) { |
| 1147 | dev_err(&pdev->dev, "can not register to master err %d\n", ret); |
| 1148 | goto exit_pm_disable; |
| 1149 | } |
| 1150 | return ret; |
| 1151 | |
| 1152 | exit_pm_disable: |
| 1153 | pm_runtime_disable(&pdev->dev); |
| 1154 | if (!pm_runtime_status_suspended(&pdev->dev)) |
| 1155 | tegra_slink_runtime_suspend(&pdev->dev); |
| 1156 | tegra_slink_deinit_dma_param(tspi, false); |
| 1157 | exit_rx_dma_free: |
| 1158 | tegra_slink_deinit_dma_param(tspi, true); |
| 1159 | exit_free_irq: |
| 1160 | free_irq(spi_irq, tspi); |
| 1161 | exit_free_master: |
| 1162 | spi_master_put(master); |
| 1163 | return ret; |
| 1164 | } |
| 1165 | |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1166 | static int tegra_slink_remove(struct platform_device *pdev) |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1167 | { |
Jingoo Han | 24b5a82 | 2013-05-23 19:20:40 +0900 | [diff] [blame] | 1168 | struct spi_master *master = platform_get_drvdata(pdev); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1169 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
| 1170 | |
| 1171 | free_irq(tspi->irq, tspi); |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1172 | |
| 1173 | if (tspi->tx_dma_chan) |
| 1174 | tegra_slink_deinit_dma_param(tspi, false); |
| 1175 | |
| 1176 | if (tspi->rx_dma_chan) |
| 1177 | tegra_slink_deinit_dma_param(tspi, true); |
| 1178 | |
| 1179 | pm_runtime_disable(&pdev->dev); |
| 1180 | if (!pm_runtime_status_suspended(&pdev->dev)) |
| 1181 | tegra_slink_runtime_suspend(&pdev->dev); |
| 1182 | |
| 1183 | return 0; |
| 1184 | } |
| 1185 | |
| 1186 | #ifdef CONFIG_PM_SLEEP |
| 1187 | static int tegra_slink_suspend(struct device *dev) |
| 1188 | { |
| 1189 | struct spi_master *master = dev_get_drvdata(dev); |
| 1190 | |
| 1191 | return spi_master_suspend(master); |
| 1192 | } |
| 1193 | |
| 1194 | static int tegra_slink_resume(struct device *dev) |
| 1195 | { |
| 1196 | struct spi_master *master = dev_get_drvdata(dev); |
| 1197 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
| 1198 | int ret; |
| 1199 | |
| 1200 | ret = pm_runtime_get_sync(dev); |
| 1201 | if (ret < 0) { |
| 1202 | dev_err(dev, "pm runtime failed, e = %d\n", ret); |
| 1203 | return ret; |
| 1204 | } |
| 1205 | tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); |
| 1206 | tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); |
| 1207 | pm_runtime_put(dev); |
| 1208 | |
| 1209 | return spi_master_resume(master); |
| 1210 | } |
| 1211 | #endif |
| 1212 | |
| 1213 | static int tegra_slink_runtime_suspend(struct device *dev) |
| 1214 | { |
| 1215 | struct spi_master *master = dev_get_drvdata(dev); |
| 1216 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
| 1217 | |
| 1218 | /* Flush all write which are in PPSB queue by reading back */ |
| 1219 | tegra_slink_readl(tspi, SLINK_MAS_DATA); |
| 1220 | |
| 1221 | clk_disable_unprepare(tspi->clk); |
| 1222 | return 0; |
| 1223 | } |
| 1224 | |
| 1225 | static int tegra_slink_runtime_resume(struct device *dev) |
| 1226 | { |
| 1227 | struct spi_master *master = dev_get_drvdata(dev); |
| 1228 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); |
| 1229 | int ret; |
| 1230 | |
| 1231 | ret = clk_prepare_enable(tspi->clk); |
| 1232 | if (ret < 0) { |
| 1233 | dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); |
| 1234 | return ret; |
| 1235 | } |
| 1236 | return 0; |
| 1237 | } |
| 1238 | |
| 1239 | static const struct dev_pm_ops slink_pm_ops = { |
| 1240 | SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, |
| 1241 | tegra_slink_runtime_resume, NULL) |
| 1242 | SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) |
| 1243 | }; |
| 1244 | static struct platform_driver tegra_slink_driver = { |
| 1245 | .driver = { |
| 1246 | .name = "spi-tegra-slink", |
| 1247 | .owner = THIS_MODULE, |
| 1248 | .pm = &slink_pm_ops, |
Stephen Warren | c60fea0 | 2013-02-15 15:03:49 -0700 | [diff] [blame] | 1249 | .of_match_table = tegra_slink_of_match, |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1250 | }, |
| 1251 | .probe = tegra_slink_probe, |
Grant Likely | fd4a319 | 2012-12-07 16:57:14 +0000 | [diff] [blame] | 1252 | .remove = tegra_slink_remove, |
Laxman Dewangan | dc4dc36 | 2012-10-30 12:34:05 +0530 | [diff] [blame] | 1253 | }; |
| 1254 | module_platform_driver(tegra_slink_driver); |
| 1255 | |
| 1256 | MODULE_ALIAS("platform:spi-tegra-slink"); |
| 1257 | MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); |
| 1258 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); |
| 1259 | MODULE_LICENSE("GPL v2"); |