blob: 5e579552aa5444fb7189b8df54e09758fd912b56 [file] [log] [blame]
Anton Vorontsovd94f9442010-03-25 17:12:41 +03001/*
2 * Copyright 2008 Cavium Networks
3 *
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
7 */
8
Mac Lin38e64ba2010-11-23 00:32:43 +08009#include <linux/init.h>
10#include <linux/module.h>
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040011#include <linux/io.h>
Anton Vorontsovd94f9442010-03-25 17:12:41 +030012#include <linux/delay.h>
Mac Lincf367972010-11-23 00:32:44 +080013#include <asm/atomic.h>
Anton Vorontsovd94f9442010-03-25 17:12:41 +030014#include <mach/system.h>
15#include <mach/cns3xxx.h>
Mac Lin38e64ba2010-11-23 00:32:43 +080016#include <mach/pm.h>
Anton Vorontsovd94f9442010-03-25 17:12:41 +030017
18void cns3xxx_pwr_clk_en(unsigned int block)
19{
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040020 u32 reg = __raw_readl(PM_CLK_GATE_REG);
21
22 reg |= (block & PM_CLK_GATE_REG_MASK);
23 __raw_writel(reg, PM_CLK_GATE_REG);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030024}
Mac Lin38e64ba2010-11-23 00:32:43 +080025EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
26
27void cns3xxx_pwr_clk_dis(unsigned int block)
28{
29 u32 reg = __raw_readl(PM_CLK_GATE_REG);
30
31 reg &= ~(block & PM_CLK_GATE_REG_MASK);
32 __raw_writel(reg, PM_CLK_GATE_REG);
33}
34EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030035
36void cns3xxx_pwr_power_up(unsigned int block)
37{
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040038 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
39
40 reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030042
43 /* Wait for 300us for the PLL output clock locked. */
44 udelay(300);
45};
Mac Lin38e64ba2010-11-23 00:32:43 +080046EXPORT_SYMBOL(cns3xxx_pwr_power_up);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030047
48void cns3xxx_pwr_power_down(unsigned int block)
49{
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040050 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
51
Anton Vorontsovd94f9442010-03-25 17:12:41 +030052 /* write '1' to power down */
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040053 reg |= (block & CNS3XXX_PWR_PLL_ALL);
54 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030055};
Mac Lin38e64ba2010-11-23 00:32:43 +080056EXPORT_SYMBOL(cns3xxx_pwr_power_down);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030057
58static void cns3xxx_pwr_soft_rst_force(unsigned int block)
59{
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040060 u32 reg = __raw_readl(PM_SOFT_RST_REG);
61
Anton Vorontsovd94f9442010-03-25 17:12:41 +030062 /*
63 * bit 0, 28, 29 => program low to reset,
64 * the other else program low and then high
65 */
66 if (block & 0x30000001) {
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040067 reg &= ~(block & PM_SOFT_RST_REG_MASK);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030068 } else {
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040069 reg &= ~(block & PM_SOFT_RST_REG_MASK);
Anton Vorontsovdf8f4d22010-11-26 20:48:35 +030070 __raw_writel(reg, PM_SOFT_RST_REG);
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040071 reg |= (block & PM_SOFT_RST_REG_MASK);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030072 }
Anton Vorontsov6eb5d142010-06-02 14:12:08 +040073
74 __raw_writel(reg, PM_SOFT_RST_REG);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030075}
Mac Lin38e64ba2010-11-23 00:32:43 +080076EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030077
78void cns3xxx_pwr_soft_rst(unsigned int block)
79{
80 static unsigned int soft_reset;
81
82 if (soft_reset & block) {
83 /* SPI/I2C/GPIO use the same block, reset once. */
84 return;
85 } else {
86 soft_reset |= block;
87 }
88 cns3xxx_pwr_soft_rst_force(block);
89}
Mac Lin38e64ba2010-11-23 00:32:43 +080090EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
Anton Vorontsovd94f9442010-03-25 17:12:41 +030091
92void arch_reset(char mode, const char *cmd)
93{
94 /*
95 * To reset, we hit the on-board reset register
96 * in the system FPGA.
97 */
98 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
99}
100
101/*
102 * cns3xxx_cpu_clock - return CPU/L2 clock
103 * aclk: cpu clock/2
104 * hclk: cpu clock/4
105 * pclk: cpu clock/8
106 */
107int cns3xxx_cpu_clock(void)
108{
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400109 u32 reg = __raw_readl(PM_CLK_CTRL_REG);
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300110 int cpu;
111 int cpu_sel;
112 int div_sel;
113
Anton Vorontsov6eb5d142010-06-02 14:12:08 +0400114 cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
115 div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
Anton Vorontsovd94f9442010-03-25 17:12:41 +0300116
117 cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
118
119 return cpu;
120}
Mac Lin38e64ba2010-11-23 00:32:43 +0800121EXPORT_SYMBOL(cns3xxx_cpu_clock);
Mac Lincf367972010-11-23 00:32:44 +0800122
123atomic_t usb_pwr_ref = ATOMIC_INIT(0);
124EXPORT_SYMBOL(usb_pwr_ref);