John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 1 | /* This program is free software; you can redistribute it and/or modify |
| 2 | * it under the terms of the GNU General Public License as published by |
| 3 | * the Free Software Foundation; version 2 of the License |
| 4 | * |
| 5 | * This program is distributed in the hope that it will be useful, |
| 6 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 7 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 8 | * GNU General Public License for more details. |
| 9 | * |
| 10 | * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org> |
| 11 | * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org> |
| 12 | * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com> |
| 13 | */ |
| 14 | |
| 15 | #ifndef MTK_ETH_H |
| 16 | #define MTK_ETH_H |
| 17 | |
| 18 | #define MTK_QDMA_PAGE_SIZE 2048 |
| 19 | #define MTK_MAX_RX_LENGTH 1536 |
| 20 | #define MTK_TX_DMA_BUF_LEN 0x3fff |
| 21 | #define MTK_DMA_SIZE 256 |
| 22 | #define MTK_NAPI_WEIGHT 64 |
| 23 | #define MTK_MAC_COUNT 2 |
| 24 | #define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN) |
| 25 | #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) |
| 26 | #define MTK_DMA_DUMMY_DESC 0xffffffff |
| 27 | #define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \ |
| 28 | NETIF_MSG_PROBE | \ |
| 29 | NETIF_MSG_LINK | \ |
| 30 | NETIF_MSG_TIMER | \ |
| 31 | NETIF_MSG_IFDOWN | \ |
| 32 | NETIF_MSG_IFUP | \ |
| 33 | NETIF_MSG_RX_ERR | \ |
| 34 | NETIF_MSG_TX_ERR) |
| 35 | #define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \ |
| 36 | NETIF_F_RXCSUM | \ |
| 37 | NETIF_F_HW_VLAN_CTAG_TX | \ |
| 38 | NETIF_F_HW_VLAN_CTAG_RX | \ |
| 39 | NETIF_F_SG | NETIF_F_TSO | \ |
| 40 | NETIF_F_TSO6 | \ |
| 41 | NETIF_F_IPV6_CSUM) |
| 42 | #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1)) |
| 43 | |
| 44 | /* Frame Engine Global Reset Register */ |
| 45 | #define MTK_RST_GL 0x04 |
| 46 | #define RST_GL_PSE BIT(0) |
| 47 | |
| 48 | /* Frame Engine Interrupt Status Register */ |
| 49 | #define MTK_INT_STATUS2 0x08 |
| 50 | #define MTK_GDM1_AF BIT(28) |
| 51 | #define MTK_GDM2_AF BIT(29) |
| 52 | |
| 53 | /* Frame Engine Interrupt Grouping Register */ |
| 54 | #define MTK_FE_INT_GRP 0x20 |
| 55 | |
| 56 | /* CDMP Exgress Control Register */ |
| 57 | #define MTK_CDMP_EG_CTRL 0x404 |
| 58 | |
| 59 | /* GDM Exgress Control Register */ |
| 60 | #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) |
| 61 | #define MTK_GDMA_ICS_EN BIT(22) |
| 62 | #define MTK_GDMA_TCS_EN BIT(21) |
| 63 | #define MTK_GDMA_UCS_EN BIT(20) |
| 64 | |
| 65 | /* Unicast Filter MAC Address Register - Low */ |
| 66 | #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) |
| 67 | |
| 68 | /* Unicast Filter MAC Address Register - High */ |
| 69 | #define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000)) |
| 70 | |
| 71 | /* QDMA TX Queue Configuration Registers */ |
| 72 | #define MTK_QTX_CFG(x) (0x1800 + (x * 0x10)) |
| 73 | #define QDMA_RES_THRES 4 |
| 74 | |
| 75 | /* QDMA TX Queue Scheduler Registers */ |
| 76 | #define MTK_QTX_SCH(x) (0x1804 + (x * 0x10)) |
| 77 | |
| 78 | /* QDMA RX Base Pointer Register */ |
| 79 | #define MTK_QRX_BASE_PTR0 0x1900 |
| 80 | |
| 81 | /* QDMA RX Maximum Count Register */ |
| 82 | #define MTK_QRX_MAX_CNT0 0x1904 |
| 83 | |
| 84 | /* QDMA RX CPU Pointer Register */ |
| 85 | #define MTK_QRX_CRX_IDX0 0x1908 |
| 86 | |
| 87 | /* QDMA RX DMA Pointer Register */ |
| 88 | #define MTK_QRX_DRX_IDX0 0x190C |
| 89 | |
| 90 | /* QDMA Global Configuration Register */ |
| 91 | #define MTK_QDMA_GLO_CFG 0x1A04 |
| 92 | #define MTK_RX_2B_OFFSET BIT(31) |
| 93 | #define MTK_RX_BT_32DWORDS (3 << 11) |
| 94 | #define MTK_TX_WB_DDONE BIT(6) |
| 95 | #define MTK_DMA_SIZE_16DWORDS (2 << 4) |
| 96 | #define MTK_RX_DMA_BUSY BIT(3) |
| 97 | #define MTK_TX_DMA_BUSY BIT(1) |
| 98 | #define MTK_RX_DMA_EN BIT(2) |
| 99 | #define MTK_TX_DMA_EN BIT(0) |
| 100 | #define MTK_DMA_BUSY_TIMEOUT HZ |
| 101 | |
| 102 | /* QDMA Reset Index Register */ |
| 103 | #define MTK_QDMA_RST_IDX 0x1A08 |
| 104 | #define MTK_PST_DRX_IDX0 BIT(16) |
| 105 | |
| 106 | /* QDMA Delay Interrupt Register */ |
| 107 | #define MTK_QDMA_DELAY_INT 0x1A0C |
| 108 | |
| 109 | /* QDMA Flow Control Register */ |
| 110 | #define MTK_QDMA_FC_THRES 0x1A10 |
| 111 | #define FC_THRES_DROP_MODE BIT(20) |
| 112 | #define FC_THRES_DROP_EN (7 << 16) |
| 113 | #define FC_THRES_MIN 0x4444 |
| 114 | |
| 115 | /* QDMA Interrupt Status Register */ |
| 116 | #define MTK_QMTK_INT_STATUS 0x1A18 |
| 117 | #define MTK_RX_DONE_INT1 BIT(17) |
| 118 | #define MTK_RX_DONE_INT0 BIT(16) |
| 119 | #define MTK_TX_DONE_INT3 BIT(3) |
| 120 | #define MTK_TX_DONE_INT2 BIT(2) |
| 121 | #define MTK_TX_DONE_INT1 BIT(1) |
| 122 | #define MTK_TX_DONE_INT0 BIT(0) |
| 123 | #define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1) |
| 124 | #define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \ |
| 125 | MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3) |
| 126 | |
| 127 | /* QDMA Interrupt Status Register */ |
| 128 | #define MTK_QDMA_INT_MASK 0x1A1C |
| 129 | |
| 130 | /* QDMA Interrupt Mask Register */ |
| 131 | #define MTK_QDMA_HRED2 0x1A44 |
| 132 | |
| 133 | /* QDMA TX Forward CPU Pointer Register */ |
| 134 | #define MTK_QTX_CTX_PTR 0x1B00 |
| 135 | |
| 136 | /* QDMA TX Forward DMA Pointer Register */ |
| 137 | #define MTK_QTX_DTX_PTR 0x1B04 |
| 138 | |
| 139 | /* QDMA TX Release CPU Pointer Register */ |
| 140 | #define MTK_QTX_CRX_PTR 0x1B10 |
| 141 | |
| 142 | /* QDMA TX Release DMA Pointer Register */ |
| 143 | #define MTK_QTX_DRX_PTR 0x1B14 |
| 144 | |
| 145 | /* QDMA FQ Head Pointer Register */ |
| 146 | #define MTK_QDMA_FQ_HEAD 0x1B20 |
| 147 | |
| 148 | /* QDMA FQ Head Pointer Register */ |
| 149 | #define MTK_QDMA_FQ_TAIL 0x1B24 |
| 150 | |
| 151 | /* QDMA FQ Free Page Counter Register */ |
| 152 | #define MTK_QDMA_FQ_CNT 0x1B28 |
| 153 | |
| 154 | /* QDMA FQ Free Page Buffer Length Register */ |
| 155 | #define MTK_QDMA_FQ_BLEN 0x1B2C |
| 156 | |
| 157 | /* GMA1 Received Good Byte Count Register */ |
| 158 | #define MTK_GDM1_TX_GBCNT 0x2400 |
| 159 | #define MTK_STAT_OFFSET 0x40 |
| 160 | |
| 161 | /* QDMA descriptor txd4 */ |
| 162 | #define TX_DMA_CHKSUM (0x7 << 29) |
| 163 | #define TX_DMA_TSO BIT(28) |
| 164 | #define TX_DMA_FPORT_SHIFT 25 |
| 165 | #define TX_DMA_FPORT_MASK 0x7 |
| 166 | #define TX_DMA_INS_VLAN BIT(16) |
| 167 | |
| 168 | /* QDMA descriptor txd3 */ |
| 169 | #define TX_DMA_OWNER_CPU BIT(31) |
| 170 | #define TX_DMA_LS0 BIT(30) |
| 171 | #define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16) |
| 172 | #define TX_DMA_SWC BIT(14) |
| 173 | #define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16) |
| 174 | |
| 175 | /* QDMA descriptor rxd2 */ |
| 176 | #define RX_DMA_DONE BIT(31) |
| 177 | #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16) |
| 178 | #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff) |
| 179 | |
| 180 | /* QDMA descriptor rxd3 */ |
| 181 | #define RX_DMA_VID(_x) ((_x) & 0xfff) |
| 182 | |
| 183 | /* QDMA descriptor rxd4 */ |
| 184 | #define RX_DMA_L4_VALID BIT(24) |
| 185 | #define RX_DMA_FPORT_SHIFT 19 |
| 186 | #define RX_DMA_FPORT_MASK 0x7 |
| 187 | |
| 188 | /* PHY Indirect Access Control registers */ |
| 189 | #define MTK_PHY_IAC 0x10004 |
| 190 | #define PHY_IAC_ACCESS BIT(31) |
| 191 | #define PHY_IAC_READ BIT(19) |
| 192 | #define PHY_IAC_WRITE BIT(18) |
| 193 | #define PHY_IAC_START BIT(16) |
| 194 | #define PHY_IAC_ADDR_SHIFT 20 |
| 195 | #define PHY_IAC_REG_SHIFT 25 |
| 196 | #define PHY_IAC_TIMEOUT HZ |
| 197 | |
| 198 | /* Mac control registers */ |
| 199 | #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) |
| 200 | #define MAC_MCR_MAX_RX_1536 BIT(24) |
| 201 | #define MAC_MCR_IPG_CFG (BIT(18) | BIT(16)) |
| 202 | #define MAC_MCR_FORCE_MODE BIT(15) |
| 203 | #define MAC_MCR_TX_EN BIT(14) |
| 204 | #define MAC_MCR_RX_EN BIT(13) |
| 205 | #define MAC_MCR_BACKOFF_EN BIT(9) |
| 206 | #define MAC_MCR_BACKPR_EN BIT(8) |
| 207 | #define MAC_MCR_FORCE_RX_FC BIT(5) |
| 208 | #define MAC_MCR_FORCE_TX_FC BIT(4) |
| 209 | #define MAC_MCR_SPEED_1000 BIT(3) |
| 210 | #define MAC_MCR_SPEED_100 BIT(2) |
| 211 | #define MAC_MCR_FORCE_DPX BIT(1) |
| 212 | #define MAC_MCR_FORCE_LINK BIT(0) |
| 213 | #define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \ |
| 214 | MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \ |
| 215 | MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \ |
| 216 | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \ |
| 217 | MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \ |
| 218 | MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK) |
| 219 | |
| 220 | /* GPIO port control registers for GMAC 2*/ |
| 221 | #define GPIO_OD33_CTRL8 0x4c0 |
| 222 | #define GPIO_BIAS_CTRL 0xed0 |
| 223 | #define GPIO_DRV_SEL10 0xf00 |
| 224 | |
| 225 | /* ethernet subsystem config register */ |
| 226 | #define ETHSYS_SYSCFG0 0x14 |
| 227 | #define SYSCFG0_GE_MASK 0x3 |
| 228 | #define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2))) |
| 229 | |
| 230 | struct mtk_rx_dma { |
| 231 | unsigned int rxd1; |
| 232 | unsigned int rxd2; |
| 233 | unsigned int rxd3; |
| 234 | unsigned int rxd4; |
| 235 | } __packed __aligned(4); |
| 236 | |
| 237 | struct mtk_tx_dma { |
| 238 | unsigned int txd1; |
| 239 | unsigned int txd2; |
| 240 | unsigned int txd3; |
| 241 | unsigned int txd4; |
| 242 | } __packed __aligned(4); |
| 243 | |
| 244 | struct mtk_eth; |
| 245 | struct mtk_mac; |
| 246 | |
| 247 | /* struct mtk_hw_stats - the structure that holds the traffic statistics. |
| 248 | * @stats_lock: make sure that stats operations are atomic |
| 249 | * @reg_offset: the status register offset of the SoC |
| 250 | * @syncp: the refcount |
| 251 | * |
| 252 | * All of the supported SoCs have hardware counters for traffic statistics. |
| 253 | * Whenever the status IRQ triggers we can read the latest stats from these |
| 254 | * counters and store them in this struct. |
| 255 | */ |
| 256 | struct mtk_hw_stats { |
| 257 | u64 tx_bytes; |
| 258 | u64 tx_packets; |
| 259 | u64 tx_skip; |
| 260 | u64 tx_collisions; |
| 261 | u64 rx_bytes; |
| 262 | u64 rx_packets; |
| 263 | u64 rx_overflow; |
| 264 | u64 rx_fcs_errors; |
| 265 | u64 rx_short_errors; |
| 266 | u64 rx_long_errors; |
| 267 | u64 rx_checksum_errors; |
| 268 | u64 rx_flow_control_packets; |
| 269 | |
| 270 | spinlock_t stats_lock; |
| 271 | u32 reg_offset; |
| 272 | struct u64_stats_sync syncp; |
| 273 | }; |
| 274 | |
| 275 | /* PDMA descriptor can point at 1-2 segments. This enum allows us to track how |
| 276 | * memory was allocated so that it can be freed properly |
| 277 | */ |
| 278 | enum mtk_tx_flags { |
| 279 | MTK_TX_FLAGS_SINGLE0 = 0x01, |
| 280 | MTK_TX_FLAGS_PAGE0 = 0x02, |
| 281 | }; |
| 282 | |
| 283 | /* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at |
| 284 | * by the TX descriptor s |
| 285 | * @skb: The SKB pointer of the packet being sent |
| 286 | * @dma_addr0: The base addr of the first segment |
| 287 | * @dma_len0: The length of the first segment |
| 288 | * @dma_addr1: The base addr of the second segment |
| 289 | * @dma_len1: The length of the second segment |
| 290 | */ |
| 291 | struct mtk_tx_buf { |
| 292 | struct sk_buff *skb; |
| 293 | u32 flags; |
| 294 | DEFINE_DMA_UNMAP_ADDR(dma_addr0); |
| 295 | DEFINE_DMA_UNMAP_LEN(dma_len0); |
| 296 | DEFINE_DMA_UNMAP_ADDR(dma_addr1); |
| 297 | DEFINE_DMA_UNMAP_LEN(dma_len1); |
| 298 | }; |
| 299 | |
| 300 | /* struct mtk_tx_ring - This struct holds info describing a TX ring |
| 301 | * @dma: The descriptor ring |
| 302 | * @buf: The memory pointed at by the ring |
| 303 | * @phys: The physical addr of tx_buf |
| 304 | * @next_free: Pointer to the next free descriptor |
| 305 | * @last_free: Pointer to the last free descriptor |
| 306 | * @thresh: The threshold of minimum amount of free descriptors |
| 307 | * @free_count: QDMA uses a linked list. Track how many free descriptors |
| 308 | * are present |
| 309 | */ |
| 310 | struct mtk_tx_ring { |
| 311 | struct mtk_tx_dma *dma; |
| 312 | struct mtk_tx_buf *buf; |
| 313 | dma_addr_t phys; |
| 314 | struct mtk_tx_dma *next_free; |
| 315 | struct mtk_tx_dma *last_free; |
| 316 | u16 thresh; |
| 317 | atomic_t free_count; |
| 318 | }; |
| 319 | |
| 320 | /* struct mtk_rx_ring - This struct holds info describing a RX ring |
| 321 | * @dma: The descriptor ring |
| 322 | * @data: The memory pointed at by the ring |
| 323 | * @phys: The physical addr of rx_buf |
| 324 | * @frag_size: How big can each fragment be |
| 325 | * @buf_size: The size of each packet buffer |
| 326 | * @calc_idx: The current head of ring |
| 327 | */ |
| 328 | struct mtk_rx_ring { |
| 329 | struct mtk_rx_dma *dma; |
| 330 | u8 **data; |
| 331 | dma_addr_t phys; |
| 332 | u16 frag_size; |
| 333 | u16 buf_size; |
| 334 | u16 calc_idx; |
| 335 | }; |
| 336 | |
| 337 | /* currently no SoC has more than 2 macs */ |
| 338 | #define MTK_MAX_DEVS 2 |
| 339 | |
| 340 | /* struct mtk_eth - This is the main datasructure for holding the state |
| 341 | * of the driver |
| 342 | * @dev: The device pointer |
| 343 | * @base: The mapped register i/o base |
| 344 | * @page_lock: Make sure that register operations are atomic |
| 345 | * @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a |
| 346 | * dummy for NAPI to work |
| 347 | * @netdev: The netdev instances |
| 348 | * @mac: Each netdev is linked to a physical MAC |
| 349 | * @irq: The IRQ that we are using |
| 350 | * @msg_enable: Ethtool msg level |
| 351 | * @ethsys: The register map pointing at the range used to setup |
| 352 | * MII modes |
| 353 | * @pctl: The register map pointing at the range used to setup |
| 354 | * GMAC port drive/slew values |
| 355 | * @dma_refcnt: track how many netdevs are using the DMA engine |
| 356 | * @tx_ring: Pointer to the memore holding info about the TX ring |
| 357 | * @rx_ring: Pointer to the memore holding info about the RX ring |
| 358 | * @rx_napi: The NAPI struct |
| 359 | * @scratch_ring: Newer SoCs need memory for a second HW managed TX ring |
John Crispin | 605e4fe | 2016-06-10 13:27:59 +0200 | [diff] [blame^] | 360 | * @phy_scratch_ring: physical address of scratch_ring |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 361 | * @scratch_head: The scratch memory that scratch_ring points to. |
| 362 | * @clk_ethif: The ethif clock |
| 363 | * @clk_esw: The switch clock |
| 364 | * @clk_gp1: The gmac1 clock |
| 365 | * @clk_gp2: The gmac2 clock |
| 366 | * @mii_bus: If there is a bus we need to create an instance for it |
John Crispin | 7c78b4a | 2016-04-08 00:54:10 +0200 | [diff] [blame] | 367 | * @pending_work: The workqueue used to reset the dma ring |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 368 | */ |
| 369 | |
| 370 | struct mtk_eth { |
| 371 | struct device *dev; |
| 372 | void __iomem *base; |
| 373 | struct reset_control *rstc; |
| 374 | spinlock_t page_lock; |
| 375 | struct net_device dummy_dev; |
| 376 | struct net_device *netdev[MTK_MAX_DEVS]; |
| 377 | struct mtk_mac *mac[MTK_MAX_DEVS]; |
| 378 | int irq; |
| 379 | u32 msg_enable; |
| 380 | unsigned long sysclk; |
| 381 | struct regmap *ethsys; |
| 382 | struct regmap *pctl; |
| 383 | atomic_t dma_refcnt; |
| 384 | struct mtk_tx_ring tx_ring; |
| 385 | struct mtk_rx_ring rx_ring; |
| 386 | struct napi_struct rx_napi; |
| 387 | struct mtk_tx_dma *scratch_ring; |
John Crispin | 605e4fe | 2016-06-10 13:27:59 +0200 | [diff] [blame^] | 388 | dma_addr_t phy_scratch_ring; |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 389 | void *scratch_head; |
| 390 | struct clk *clk_ethif; |
| 391 | struct clk *clk_esw; |
| 392 | struct clk *clk_gp1; |
| 393 | struct clk *clk_gp2; |
| 394 | struct mii_bus *mii_bus; |
John Crispin | 7c78b4a | 2016-04-08 00:54:10 +0200 | [diff] [blame] | 395 | struct work_struct pending_work; |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | /* struct mtk_mac - the structure that holds the info about the MACs of the |
| 399 | * SoC |
| 400 | * @id: The number of the MAC |
| 401 | * @of_node: Our devicetree node |
| 402 | * @hw: Backpointer to our main datastruture |
| 403 | * @hw_stats: Packet statistics counter |
| 404 | * @phy_dev: The attached PHY if available |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 405 | */ |
| 406 | struct mtk_mac { |
| 407 | int id; |
| 408 | struct device_node *of_node; |
| 409 | struct mtk_eth *hw; |
| 410 | struct mtk_hw_stats *hw_stats; |
| 411 | struct phy_device *phy_dev; |
John Crispin | 656e705 | 2016-03-08 11:29:55 +0100 | [diff] [blame] | 412 | }; |
| 413 | |
| 414 | /* the struct describing the SoC. these are declared in the soc_xyz.c files */ |
| 415 | extern const struct of_device_id of_mtk_match[]; |
| 416 | |
| 417 | /* read the hardware status register */ |
| 418 | void mtk_stats_update_mac(struct mtk_mac *mac); |
| 419 | |
| 420 | void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); |
| 421 | u32 mtk_r32(struct mtk_eth *eth, unsigned reg); |
| 422 | |
| 423 | #endif /* MTK_ETH_H */ |