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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 Waldorf GMBH
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
8 * Copyright (C) 1996 Paul M. Antoine
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
Ralf Baechle41943182005-05-05 16:45:59 +000010 * Copyright (C) 2004 Maciej W. Rozycki
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 */
12#ifndef __ASM_CPU_INFO_H
13#define __ASM_CPU_INFO_H
14
Linus Torvalds1da177e2005-04-16 15:20:36 -070015#include <asm/cache.h>
16
Linus Torvalds1da177e2005-04-16 15:20:36 -070017/*
18 * Descriptor for a cache
19 */
20struct cache_desc {
Linus Torvalds1da177e2005-04-16 15:20:36 -070021 unsigned int waysize; /* Bytes per way */
Ralf Baechle6f2c3fa2006-11-30 01:14:45 +000022 unsigned short sets; /* Number of lines per set */
23 unsigned char ways; /* Number of ways */
24 unsigned char linesz; /* Size of line in bytes */
25 unsigned char waybit; /* Bits to select in a cache set */
26 unsigned char flags; /* Flags describing cache properties */
Linus Torvalds1da177e2005-04-16 15:20:36 -070027};
28
29/*
30 * Flag definitions
31 */
32#define MIPS_CACHE_NOT_PRESENT 0x00000001
33#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
34#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
35#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
36#define MIPS_IC_SNOOPS_REMOTE 0x00000010 /* Ic snoops remote stores */
Atsushi Nemotode628932006-03-13 18:23:03 +090037#define MIPS_CACHE_PINDEX 0x00000020 /* Physically indexed cache */
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39struct cpuinfo_mips {
40 unsigned long udelay_val;
41 unsigned long asid_cache;
Linus Torvalds1da177e2005-04-16 15:20:36 -070042
43 /*
44 * Capability and feature descriptor structure for MIPS CPU
45 */
46 unsigned long options;
Ralf Baechle41943182005-05-05 16:45:59 +000047 unsigned long ases;
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 unsigned int processor_id;
49 unsigned int fpu_id;
50 unsigned int cputype;
51 int isa_level;
52 int tlbsize;
53 struct cache_desc icache; /* Primary I-cache */
54 struct cache_desc dcache; /* Primary D or combined I/D cache */
55 struct cache_desc scache; /* Secondary cache */
56 struct cache_desc tcache; /* Tertiary/split secondary cache */
Ralf Baechlef6771db2007-11-08 18:02:29 +000057 int srsets; /* Shadow register sets */
Ralf Baechle0ab7aef2007-03-02 20:42:04 +000058 int core; /* physical core number */
Chris Dearmand6c30482008-05-16 17:29:54 -070059#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
Ralf Baechle41c594a2006-04-05 09:45:45 +010060 /*
61 * In the MIPS MT "SMTC" model, each TC is considered
62 * to be a "CPU" for the purposes of scheduling, but
63 * exception resources, ASID spaces, etc, are common
64 * to all TCs within the same VPE.
65 */
66 int vpe_id; /* Virtual Processor number */
Chris Dearmand6c30482008-05-16 17:29:54 -070067#endif
Ralf Baechle0ab7aef2007-03-02 20:42:04 +000068#ifdef CONFIG_MIPS_MT_SMTC
69 int tc_id; /* Thread Context number */
70#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 void *data; /* Additional data */
72} __attribute__((aligned(SMP_CACHE_BYTES)));
73
74extern struct cpuinfo_mips cpu_data[];
75#define current_cpu_data cpu_data[smp_processor_id()]
Atsushi Nemoto53dc8022007-03-10 01:07:45 +090076#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
Linus Torvalds1da177e2005-04-16 15:20:36 -070077
78extern void cpu_probe(void);
79extern void cpu_report(void);
80
Ralf Baechle9966db252007-10-11 23:46:17 +010081extern const char *__cpu_name[];
82#define cpu_name_string() __cpu_name[smp_processor_id()]
83
Linus Torvalds1da177e2005-04-16 15:20:36 -070084#endif /* __ASM_CPU_INFO_H */