blob: a4d99685a7c4015c95baad86a8e07646489e4770 [file] [log] [blame]
Andy Shevchenko667dfed2015-07-27 18:04:02 +03001/*
2 * Driver for the Intel integrated DMA 64-bit
3 *
4 * Copyright (C) 2015 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __DMA_IDMA64_H__
12#define __DMA_IDMA64_H__
13
14#include <linux/device.h>
15#include <linux/io.h>
16#include <linux/spinlock.h>
17#include <linux/types.h>
18
19#include "virt-dma.h"
20
21/* Channel registers */
22
23#define IDMA64_CH_SAR 0x00 /* Source Address Register */
24#define IDMA64_CH_DAR 0x08 /* Destination Address Register */
25#define IDMA64_CH_LLP 0x10 /* Linked List Pointer */
26#define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */
27#define IDMA64_CH_CTL_HI 0x1c /* Control Register High */
28#define IDMA64_CH_SSTAT 0x20
29#define IDMA64_CH_DSTAT 0x28
30#define IDMA64_CH_SSTATAR 0x30
31#define IDMA64_CH_DSTATAR 0x38
32#define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */
33#define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */
34#define IDMA64_CH_SGR 0x48
35#define IDMA64_CH_DSR 0x50
36
37#define IDMA64_CH_LENGTH 0x58
38
39/* Bitfields in CTL_LO */
40#define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */
41#define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */
42#define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4)
43#define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */
44#define IDMA64C_CTLL_DST_FIX (1 << 8)
45#define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */
46#define IDMA64C_CTLL_SRC_FIX (1 << 10)
47#define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */
48#define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14)
49#define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
50#define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
51#define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
52#define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */
53
54/* Bitfields in CTL_HI */
55#define IDMA64C_CTLH_BLOCK_TS(x) ((x) & ((1 << 17) - 1))
56#define IDMA64C_CTLH_DONE (1 << 17)
57
58/* Bitfields in CFG_LO */
59#define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */
60#define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */
61#define IDMA64C_CFGL_CH_SUSP (1 << 8)
62#define IDMA64C_CFGL_FIFO_EMPTY (1 << 9)
63#define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */
64#define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */
65#define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */
66
67/* Bitfields in CFG_HI */
68#define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */
69#define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */
70#define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8)
71#define IDMA64C_CFGH_RW_ISSUE_THD(x) ((x) << 18)
72
73/* Interrupt registers */
74
75#define IDMA64_INT_XFER 0x00
76#define IDMA64_INT_BLOCK 0x08
77#define IDMA64_INT_SRC_TRAN 0x10
78#define IDMA64_INT_DST_TRAN 0x18
79#define IDMA64_INT_ERROR 0x20
80
81#define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */
82#define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */
83#define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */
84#define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */
85
86/* Common registers */
87
88#define IDMA64_STATUS_INT 0x360 /* r */
89#define IDMA64_CFG 0x398
90#define IDMA64_CH_EN 0x3a0
91
92/* Bitfields in CFG */
93#define IDMA64_CFG_DMA_EN (1 << 0)
94
95/* Hardware descriptor for Linked LIst transfers */
96struct idma64_lli {
97 u64 sar;
98 u64 dar;
99 u64 llp;
100 u32 ctllo;
101 u32 ctlhi;
102 u32 sstat;
103 u32 dstat;
104};
105
106struct idma64_hw_desc {
107 struct idma64_lli *lli;
108 dma_addr_t llp;
109 dma_addr_t phys;
110 unsigned int len;
111};
112
113struct idma64_desc {
114 struct virt_dma_desc vdesc;
115 enum dma_transfer_direction direction;
116 struct idma64_hw_desc *hw;
117 unsigned int ndesc;
118 size_t length;
119 enum dma_status status;
120};
121
122static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
123{
124 return container_of(vdesc, struct idma64_desc, vdesc);
125}
126
127struct idma64_chan {
128 struct virt_dma_chan vchan;
129
130 void __iomem *regs;
131
132 /* hardware configuration */
133 enum dma_transfer_direction direction;
134 unsigned int mask;
135 struct dma_slave_config config;
136
137 void *pool;
138 struct idma64_desc *desc;
139};
140
141static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
142{
143 return container_of(chan, struct idma64_chan, vchan.chan);
144}
145
146#define channel_set_bit(idma64, reg, mask) \
147 dma_writel(idma64, reg, ((mask) << 8) | (mask))
148#define channel_clear_bit(idma64, reg, mask) \
149 dma_writel(idma64, reg, ((mask) << 8) | 0)
150
151static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
152{
153 return readl(idma64c->regs + offset);
154}
155
156static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
157 u32 value)
158{
159 writel(value, idma64c->regs + offset);
160}
161
162#define channel_readl(idma64c, reg) \
163 idma64c_readl(idma64c, IDMA64_CH_##reg)
164#define channel_writel(idma64c, reg, value) \
165 idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
166
167static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
168{
169 u64 l, h;
170
171 l = idma64c_readl(idma64c, offset);
172 h = idma64c_readl(idma64c, offset + 4);
173
174 return l | (h << 32);
175}
176
177static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
178 u64 value)
179{
180 idma64c_writel(idma64c, offset, value);
181 idma64c_writel(idma64c, offset + 4, value >> 32);
182}
183
184#define channel_readq(idma64c, reg) \
185 idma64c_readq(idma64c, IDMA64_CH_##reg)
186#define channel_writeq(idma64c, reg, value) \
187 idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
188
189struct idma64 {
190 struct dma_device dma;
191
192 void __iomem *regs;
193
194 /* channels */
195 unsigned short all_chan_mask;
196 struct idma64_chan *chan;
197};
198
199static inline struct idma64 *to_idma64(struct dma_device *ddev)
200{
201 return container_of(ddev, struct idma64, dma);
202}
203
204static inline u32 idma64_readl(struct idma64 *idma64, int offset)
205{
206 return readl(idma64->regs + offset);
207}
208
209static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
210{
211 writel(value, idma64->regs + offset);
212}
213
214#define dma_readl(idma64, reg) \
215 idma64_readl(idma64, IDMA64_##reg)
216#define dma_writel(idma64, reg, value) \
217 idma64_writel(idma64, IDMA64_##reg, (value))
218
219/**
220 * struct idma64_chip - representation of DesignWare DMA controller hardware
221 * @dev: struct device of the DMA controller
222 * @irq: irq line
223 * @regs: memory mapped I/O space
224 * @idma64: struct idma64 that is filed by idma64_probe()
225 */
226struct idma64_chip {
227 struct device *dev;
228 int irq;
229 void __iomem *regs;
230 struct idma64 *idma64;
231};
232
233#endif /* __DMA_IDMA64_H__ */