blob: 5f4d31ef3933ac9a3caa7aa0003773f960351411 [file] [log] [blame]
Michel Dänzerecc0b322009-07-21 11:23:57 +02001/*
2 * Copyright 2009 VMware, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Michel Dänzer
23 */
24#include <drm/drmP.h>
25#include <drm/radeon_drm.h>
26#include "radeon_reg.h"
27#include "radeon.h"
28
29
30/* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
31void radeon_test_moves(struct radeon_device *rdev)
32{
Jerome Glisse4c788672009-11-20 14:29:23 +010033 struct radeon_bo *vram_obj = NULL;
34 struct radeon_bo **gtt_obj = NULL;
Michel Dänzerecc0b322009-07-21 11:23:57 +020035 struct radeon_fence *fence = NULL;
36 uint64_t gtt_addr, vram_addr;
37 unsigned i, n, size;
38 int r;
39
40 size = 1024 * 1024;
41
42 /* Number of tests =
Michel Dänzer24cae9e2011-08-19 15:24:16 +000043 * (Total GTT - IB pool - writeback page - ring buffers) / test size
Michel Dänzerecc0b322009-07-21 11:23:57 +020044 */
Christian König7b1f2482011-09-23 15:11:23 +020045 n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
Christian Königbf852792011-10-13 13:19:22 +020046 for (i = 0; i < RADEON_NUM_RINGS; ++i)
47 n -= rdev->cp[i].ring_size;
Michel Dänzer24cae9e2011-08-19 15:24:16 +000048 if (rdev->wb.wb_obj)
49 n -= RADEON_GPU_PAGE_SIZE;
50 if (rdev->ih.ring_obj)
51 n -= rdev->ih.ring_size;
52 n /= size;
Michel Dänzerecc0b322009-07-21 11:23:57 +020053
54 gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
55 if (!gtt_obj) {
56 DRM_ERROR("Failed to allocate %d pointers\n", n);
57 r = 1;
58 goto out_cleanup;
59 }
60
Daniel Vetter441921d2011-02-18 17:59:16 +010061 r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
Jerome Glisse4c788672009-11-20 14:29:23 +010062 &vram_obj);
Michel Dänzerecc0b322009-07-21 11:23:57 +020063 if (r) {
64 DRM_ERROR("Failed to create VRAM object\n");
65 goto out_cleanup;
66 }
Jerome Glisse4c788672009-11-20 14:29:23 +010067 r = radeon_bo_reserve(vram_obj, false);
68 if (unlikely(r != 0))
69 goto out_cleanup;
70 r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
Michel Dänzerecc0b322009-07-21 11:23:57 +020071 if (r) {
72 DRM_ERROR("Failed to pin VRAM object\n");
73 goto out_cleanup;
74 }
Michel Dänzerecc0b322009-07-21 11:23:57 +020075 for (i = 0; i < n; i++) {
76 void *gtt_map, *vram_map;
77 void **gtt_start, **gtt_end;
78 void **vram_start, **vram_end;
79
Daniel Vetter441921d2011-02-18 17:59:16 +010080 r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
Jerome Glisse4c788672009-11-20 14:29:23 +010081 RADEON_GEM_DOMAIN_GTT, gtt_obj + i);
Michel Dänzerecc0b322009-07-21 11:23:57 +020082 if (r) {
83 DRM_ERROR("Failed to create GTT object %d\n", i);
84 goto out_cleanup;
85 }
86
Jerome Glisse4c788672009-11-20 14:29:23 +010087 r = radeon_bo_reserve(gtt_obj[i], false);
88 if (unlikely(r != 0))
89 goto out_cleanup;
90 r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
Michel Dänzerecc0b322009-07-21 11:23:57 +020091 if (r) {
92 DRM_ERROR("Failed to pin GTT object %d\n", i);
93 goto out_cleanup;
94 }
95
Jerome Glisse4c788672009-11-20 14:29:23 +010096 r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
Michel Dänzerecc0b322009-07-21 11:23:57 +020097 if (r) {
98 DRM_ERROR("Failed to map GTT object %d\n", i);
99 goto out_cleanup;
100 }
101
102 for (gtt_start = gtt_map, gtt_end = gtt_map + size;
103 gtt_start < gtt_end;
104 gtt_start++)
105 *gtt_start = gtt_start;
106
Jerome Glisse4c788672009-11-20 14:29:23 +0100107 radeon_bo_kunmap(gtt_obj[i]);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200108
Alex Deucher74652802011-08-25 13:39:48 -0400109 r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200110 if (r) {
111 DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i);
112 goto out_cleanup;
113 }
114
Matt Turnera77f1712009-10-14 00:34:41 -0400115 r = radeon_copy(rdev, gtt_addr, vram_addr, size / RADEON_GPU_PAGE_SIZE, fence);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200116 if (r) {
117 DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
118 goto out_cleanup;
119 }
120
121 r = radeon_fence_wait(fence, false);
122 if (r) {
123 DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
124 goto out_cleanup;
125 }
126
127 radeon_fence_unref(&fence);
128
Jerome Glisse4c788672009-11-20 14:29:23 +0100129 r = radeon_bo_kmap(vram_obj, &vram_map);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200130 if (r) {
131 DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
132 goto out_cleanup;
133 }
134
135 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
136 vram_start = vram_map, vram_end = vram_map + size;
137 vram_start < vram_end;
138 gtt_start++, vram_start++) {
139 if (*vram_start != gtt_start) {
140 DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
Michel Dänzer4fb1a352011-08-19 15:24:17 +0000141 "expected 0x%p (GTT/VRAM offset "
142 "0x%16llx/0x%16llx)\n",
143 i, *vram_start, gtt_start,
144 (unsigned long long)
145 (gtt_addr - rdev->mc.gtt_start +
146 (void*)gtt_start - gtt_map),
147 (unsigned long long)
148 (vram_addr - rdev->mc.vram_start +
149 (void*)gtt_start - gtt_map));
Jerome Glisse4c788672009-11-20 14:29:23 +0100150 radeon_bo_kunmap(vram_obj);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200151 goto out_cleanup;
152 }
153 *vram_start = vram_start;
154 }
155
Jerome Glisse4c788672009-11-20 14:29:23 +0100156 radeon_bo_kunmap(vram_obj);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200157
Alex Deucher74652802011-08-25 13:39:48 -0400158 r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200159 if (r) {
160 DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i);
161 goto out_cleanup;
162 }
163
Matt Turnera77f1712009-10-14 00:34:41 -0400164 r = radeon_copy(rdev, vram_addr, gtt_addr, size / RADEON_GPU_PAGE_SIZE, fence);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200165 if (r) {
166 DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
167 goto out_cleanup;
168 }
169
170 r = radeon_fence_wait(fence, false);
171 if (r) {
172 DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
173 goto out_cleanup;
174 }
175
176 radeon_fence_unref(&fence);
177
Jerome Glisse4c788672009-11-20 14:29:23 +0100178 r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200179 if (r) {
180 DRM_ERROR("Failed to map GTT object after copy %d\n", i);
181 goto out_cleanup;
182 }
183
184 for (gtt_start = gtt_map, gtt_end = gtt_map + size,
185 vram_start = vram_map, vram_end = vram_map + size;
186 gtt_start < gtt_end;
187 gtt_start++, vram_start++) {
188 if (*gtt_start != vram_start) {
189 DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
Michel Dänzer4fb1a352011-08-19 15:24:17 +0000190 "expected 0x%p (VRAM/GTT offset "
191 "0x%16llx/0x%16llx)\n",
192 i, *gtt_start, vram_start,
193 (unsigned long long)
194 (vram_addr - rdev->mc.vram_start +
195 (void*)vram_start - vram_map),
196 (unsigned long long)
197 (gtt_addr - rdev->mc.gtt_start +
198 (void*)vram_start - vram_map));
Jerome Glisse4c788672009-11-20 14:29:23 +0100199 radeon_bo_kunmap(gtt_obj[i]);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200200 goto out_cleanup;
201 }
202 }
203
Jerome Glisse4c788672009-11-20 14:29:23 +0100204 radeon_bo_kunmap(gtt_obj[i]);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200205
206 DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
Jerome Glissed594e462010-02-17 21:54:29 +0000207 gtt_addr - rdev->mc.gtt_start);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200208 }
209
210out_cleanup:
211 if (vram_obj) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100212 if (radeon_bo_is_reserved(vram_obj)) {
213 radeon_bo_unpin(vram_obj);
214 radeon_bo_unreserve(vram_obj);
215 }
216 radeon_bo_unref(&vram_obj);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200217 }
218 if (gtt_obj) {
219 for (i = 0; i < n; i++) {
220 if (gtt_obj[i]) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100221 if (radeon_bo_is_reserved(gtt_obj[i])) {
222 radeon_bo_unpin(gtt_obj[i]);
223 radeon_bo_unreserve(gtt_obj[i]);
224 }
225 radeon_bo_unref(&gtt_obj[i]);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200226 }
227 }
228 kfree(gtt_obj);
229 }
230 if (fence) {
231 radeon_fence_unref(&fence);
232 }
233 if (r) {
234 printk(KERN_WARNING "Error while testing BO move.\n");
235 }
236}
Christian König60a7e392011-09-27 12:31:00 +0200237
238void radeon_test_ring_sync(struct radeon_device *rdev,
239 struct radeon_cp *cpA,
240 struct radeon_cp *cpB)
241{
242 struct radeon_fence *fence = NULL;
243 struct radeon_semaphore *semaphore = NULL;
244 int ringA = radeon_ring_index(rdev, cpA);
245 int ringB = radeon_ring_index(rdev, cpB);
246 int r;
247
248 r = radeon_fence_create(rdev, &fence, ringA);
249 if (r) {
250 DRM_ERROR("Failed to create sync fence\n");
251 goto out_cleanup;
252 }
253
254 r = radeon_semaphore_create(rdev, &semaphore);
255 if (r) {
256 DRM_ERROR("Failed to create semaphore\n");
257 goto out_cleanup;
258 }
259
260 r = radeon_ring_lock(rdev, cpA, 64);
261 if (r) {
262 DRM_ERROR("Failed to lock ring %d\n", ringA);
263 goto out_cleanup;
264 }
265 radeon_semaphore_emit_wait(rdev, ringA, semaphore);
266 radeon_fence_emit(rdev, fence);
267 radeon_ring_unlock_commit(rdev, cpA);
268
269 mdelay(1000);
270
271 if (radeon_fence_signaled(fence)) {
272 DRM_ERROR("Fence signaled without waiting for semaphore.\n");
273 goto out_cleanup;
274 }
275
276 r = radeon_ring_lock(rdev, cpB, 64);
277 if (r) {
278 DRM_ERROR("Failed to lock ring %d\n", ringB);
279 goto out_cleanup;
280 }
281 radeon_semaphore_emit_signal(rdev, ringB, semaphore);
282 radeon_ring_unlock_commit(rdev, cpB);
283
284 r = radeon_fence_wait(fence, false);
285 if (r) {
286 DRM_ERROR("Failed to wait for sync fence\n");
287 goto out_cleanup;
288 }
289
290 DRM_INFO("Syncing between rings %d and %d seems to work.\n", ringA, ringB);
291
292out_cleanup:
293 if (semaphore)
294 radeon_semaphore_free(rdev, semaphore);
295
296 if (fence)
297 radeon_fence_unref(&fence);
298
299 if (r)
300 printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
301}
302
303void radeon_test_syncing(struct radeon_device *rdev)
304{
305 int i, j;
306
307 for (i = 1; i < RADEON_NUM_RINGS; ++i) {
308 struct radeon_cp *cpA = &rdev->cp[i];
309 if (!cpA->ready)
310 continue;
311
312 for (j = 0; j < i; ++j) {
313 struct radeon_cp *cpB = &rdev->cp[j];
314 if (!cpB->ready)
315 continue;
316
317 DRM_INFO("Testing syncing between rings %d and %d\n", i, j);
318 radeon_test_ring_sync(rdev, cpA, cpB);
319
320 DRM_INFO("Testing syncing between rings %d and %d\n", j, i);
321 radeon_test_ring_sync(rdev, cpB, cpA);
322 }
323 }
324}