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gerrit-public.fairphone.software / kernel / msm-4.9 / 60b3b9af35aad66345e395be911e46fb8443f0c5 / . / include / asm-blackfin / mach-bf548 / cdefBF54x_base.h
blob: 19ddcd83c71f130c658ea593495660faa1f6cb2a [file] [log] [blame]
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H
33
Mike Frysinger36a15482007-07-25 12:01:19 +0800[diff] [blame]34#include <asm/blackfin.h>
35
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]36#include "defBF54x_base.h"
Michael Hennerich1c5d2262007-06-21 11:34:16 +0800[diff] [blame]37#include <asm/system.h>
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]38
39/* ************************************************************** */
40/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
41/* ************************************************************** */
42
43/* PLL Registers */
44
45#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
46#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
47#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
48#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
49#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
Michael Hennerich1c5d2262007-06-21 11:34:16 +0800[diff] [blame]50/* Writing to VR_CTL initiates a PLL relock sequence. */
51static __inline__ void bfin_write_VR_CTL(unsigned int val)
52{
53 unsigned long flags, iwr0, iwr1, iwr2;
54
55 /* Enable the PLL Wakeup bit in SIC IWR */
56 iwr0 = bfin_read32(SIC_IWR0);
57 iwr1 = bfin_read32(SIC_IWR1);
58 iwr2 = bfin_read32(SIC_IWR2);
59 /* Only allow PPL Wakeup) */
60 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
61 bfin_write32(SIC_IWR1, 0);
62 bfin_write32(SIC_IWR2, 0);
63
64 bfin_write16(VR_CTL, val);
Mike Frysingerd5148ff2007-07-25 11:57:42 +0800[diff] [blame]65 SSYNC();
Michael Hennerich1c5d2262007-06-21 11:34:16 +0800[diff] [blame]66
67 local_irq_save(flags);
68 asm("IDLE;");
69 local_irq_restore(flags);
70 bfin_write32(SIC_IWR0, iwr0);
71 bfin_write32(SIC_IWR1, iwr1);
72 bfin_write32(SIC_IWR2, iwr2);
Michael Hennerich1c5d2262007-06-21 11:34:16 +0800[diff] [blame]73}
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]74#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
75#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
76#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
77#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
78
79/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
80
81#define bfin_read_CHIPID() bfin_read32(CHIPID)
82#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
83
84/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
85
86#define bfin_read_SWRST() bfin_read16(SWRST)
87#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
88#define bfin_read_SYSCR() bfin_read16(SYSCR)
89#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
90
91/* SIC Registers */
92
93#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
94#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
95#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
96#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
97#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
98#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]99#define bfin_read_SIC_IMASK(x) bfin_read32(SIC_IMASK0 + (x << 2))
100#define bfin_write_SIC_IMASK(x, val) bfin_write32((SIC_IMASK0 + (x << 2)), val)
101
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]102#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
103#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
104#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
105#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
106#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
107#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]108#define bfin_read_SIC_ISR(x) bfin_read32(SIC_ISR0 + (x << 2))
109#define bfin_write_SIC_ISR(x, val) bfin_write32((SIC_ISR0 + (x << 2)), val)
110
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]111#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
112#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
113#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
114#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
115#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
116#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
117#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
118#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
119#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
120#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
121#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
122#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
123#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
124#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
125#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
126#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
127#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
128#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
129#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
130#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
131#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
132#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
133#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
134#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
135#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
136#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
137#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
138#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
139#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
140#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
141
142/* Watchdog Timer Registers */
143
144#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
145#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
146#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
147#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
148#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
149#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
150
151/* RTC Registers */
152
153#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
154#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
155#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
156#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
157#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
158#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
159#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
160#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
161#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
162#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
163#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
164#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
165
166/* UART0 Registers */
167
168#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
169#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
170#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
171#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
172#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
173#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
174#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
175#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
176#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
177#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
178#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
179#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
180#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
181#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
182#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
183#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
184#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
185#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
186#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
187#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
188#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
189#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
190#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
191#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
192
193/* SPI0 Registers */
194
195#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
196#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
197#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
198#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
199#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
200#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
201#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
202#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
203#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
204#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
205#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
206#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
207#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
208#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
209
210/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
211
212/* Two Wire Interface Registers (TWI0) */
213
214#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
215#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
216#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
217#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
218#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
219#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
220#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
221#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
222#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
223#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
224#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
225#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
226#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
227#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
228#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
229#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
230#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
231#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
232#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
233#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
234#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
235#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
236#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
237#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
238#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
239#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
240#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
241#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
242#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
243#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
244#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
245#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
246
247/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
248
249/* SPORT1 Registers */
250
251#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
252#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
253#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
254#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
255#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
256#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
257#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
258#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
259#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
260#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
261#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
262#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
263#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
264#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
265#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
266#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
267#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
268#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
269#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
270#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
271#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
272#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
273#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
274#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
275#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
276#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
277#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
278#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
279#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
280#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
281#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
282#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
283#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
284#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
285#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
286#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
287#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
288#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
289#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
290#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
291#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
292#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
293#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
294#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
295
296/* Asynchronous Memory Control Registers */
297
298#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
299#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
300#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
301#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
302#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
303#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
304#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
305#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
306#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
307#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
308#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
309#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
310#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
311#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
312
313/* DDR Memory Control Registers */
314
315#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
316#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
317#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
318#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
319#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
320#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
321#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
322#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
323#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
324#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
325#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
326#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD)
327#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
328#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
329#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
330#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
331
332/* DDR BankRead and Write Count Registers */
333
334#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
335#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
336#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
337#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
338#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
339#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
340#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
341#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
342#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
343#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
344#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
345#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
346#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
347#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
348#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
349#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
350#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
351#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
352#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
353#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
354#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
355#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
356#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
357#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
358#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
359#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
360#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
361#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
362#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
363#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
364#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
365#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
366#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
367#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
368#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
369#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
370#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
371#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
372#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
373#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
374#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
375#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
376#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
377#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
378#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
379#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
380#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
381#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
382#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
383#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
384
385/* DMAC0 Registers */
386
387#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
388#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
389#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
390#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
391
392/* DMA Channel 0 Registers */
393
394#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
395#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR)
396#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
397#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR)
398#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
399#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
400#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
401#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
402#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
403#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY)
404#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
405#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
406#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
407#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY)
408#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
409#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR)
410#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
411#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR)
412#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
413#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
414#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
415#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
416#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
417#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
418#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
419#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
420
421/* DMA Channel 1 Registers */
422
423#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
424#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR)
425#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
426#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR)
427#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
428#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
429#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
430#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
431#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
432#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY)
433#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
434#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
435#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
436#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY)
437#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
438#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR)
439#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
440#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR)
441#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
442#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
443#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
444#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
445#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
446#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
447#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
448#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
449
450/* DMA Channel 2 Registers */
451
452#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
453#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR)
454#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
455#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR)
456#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
457#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
458#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
459#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
460#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
461#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY)
462#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
463#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
464#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
465#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY)
466#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
467#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR)
468#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
469#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR)
470#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
471#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
472#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
473#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
474#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
475#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
476#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
477#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
478
479/* DMA Channel 3 Registers */
480
481#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
482#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR)
483#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
484#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR)
485#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
486#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
487#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
488#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
489#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
490#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY)
491#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
492#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
493#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
494#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY)
495#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
496#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR)
497#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
498#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR)
499#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
500#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
501#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
502#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
503#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
504#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
505#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
506#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
507
508/* DMA Channel 4 Registers */
509
510#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
511#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR)
512#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
513#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR)
514#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
515#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
516#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
517#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
518#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
519#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY)
520#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
521#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
522#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
523#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY)
524#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
525#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR)
526#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
527#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR)
528#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
529#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
530#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
531#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
532#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
533#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
534#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
535#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
536
537/* DMA Channel 5 Registers */
538
539#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
540#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR)
541#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
542#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR)
543#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
544#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
545#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
546#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
547#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
548#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY)
549#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
550#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
551#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
552#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY)
553#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
554#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR)
555#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
556#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR)
557#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
558#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
559#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
560#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
561#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
562#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
563#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
564#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
565
566/* DMA Channel 6 Registers */
567
568#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
569#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR)
570#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
571#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR)
572#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
573#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
574#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
575#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
576#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
577#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY)
578#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
579#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
580#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
581#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY)
582#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
583#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR)
584#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
585#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR)
586#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
587#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
588#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
589#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
590#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
591#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
592#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
593#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
594
595/* DMA Channel 7 Registers */
596
597#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
598#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR)
599#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
600#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR)
601#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
602#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
603#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
604#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
605#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
606#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY)
607#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
608#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
609#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
610#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY)
611#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
612#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR)
613#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
614#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR)
615#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
616#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
617#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
618#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
619#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
620#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
621#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
622#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
623
624/* DMA Channel 8 Registers */
625
626#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
627#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR)
628#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
629#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR)
630#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
631#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
632#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
633#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
634#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
635#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY)
636#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
637#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
638#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
639#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY)
640#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
641#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR)
642#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
643#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR)
644#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
645#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
646#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
647#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
648#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
649#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
650#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
651#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
652
653/* DMA Channel 9 Registers */
654
655#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
656#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR)
657#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
658#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR)
659#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
660#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
661#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
662#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
663#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
664#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY)
665#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
666#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
667#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
668#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY)
669#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
670#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR)
671#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
672#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR)
673#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
674#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
675#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
676#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
677#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
678#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
679#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
680#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
681
682/* DMA Channel 10 Registers */
683
684#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
685#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR)
686#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
687#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR)
688#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
689#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
690#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
691#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
692#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
693#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY)
694#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
695#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
696#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
697#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY)
698#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
699#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR)
700#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
701#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR)
702#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
703#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
704#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
705#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
706#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
707#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
708#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
709#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
710
711/* DMA Channel 11 Registers */
712
713#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
714#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR)
715#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
716#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR)
717#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
718#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
719#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
720#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
721#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
722#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY)
723#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
724#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
725#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
726#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY)
727#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
728#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR)
729#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
730#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR)
731#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
732#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
733#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
734#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
735#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
736#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
737#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
738#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
739
740/* MDMA Stream 0 Registers */
741
742#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
743#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
744#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]745#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]746#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
747#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
748#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
749#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
750#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]751#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]752#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
753#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
754#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]755#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]756#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]757#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]758#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]759#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]760#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
761#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
762#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
763#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
764#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
765#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
766#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
767#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
768#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]769#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]770#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]771#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]772#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
773#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
774#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
775#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
776#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]777#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]778#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
779#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
780#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]781#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]782#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]783#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]784#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]785#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]786#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
787#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
788#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
789#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
790#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
791#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
792#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
793#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
794
795/* MDMA Stream 1 Registers */
796
797#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]798#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]799#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]800#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]801#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
802#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
803#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
804#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
805#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
806#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY)
807#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
808#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
809#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
810#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
811#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]812#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]813#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]814#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]815#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
816#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
817#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
818#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
819#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
820#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
821#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
822#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
823#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]824#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]825#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]826#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]827#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
828#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
829#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
830#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
831#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
832#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY)
833#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
834#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
835#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
836#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
837#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]838#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]839#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
Roy Huang24a07a12007-07-12 22:41:45 +0800[diff] [blame]840#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
Bryan Wu19381f02007-05-21 18:09:31 +0800[diff] [blame]841#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
842#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
843#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
844#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
845#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
846#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
847#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
848#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
849
850/* EPPI1 Registers */
851
852#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
853#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
854#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
855#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
856#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
857#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
858#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
859#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
860#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
861#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
862#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
863#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
864#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
865#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
866#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
867#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
868#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
869#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
870#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
871#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
872#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
873#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
874#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
875#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
876#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
877#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
878#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
879#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
880
881/* Port Interrubfin_read_()t 0 Registers (32-bit) */
882
883#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
884#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
885#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
886#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
887#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
888#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
889#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
890#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
891#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
892#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
893#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
894#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
895#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
896#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
897#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
898#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
899#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
900#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
901#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
902#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
903
904/* Port Interrubfin_read_()t 1 Registers (32-bit) */
905
906#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
907#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
908#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
909#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
910#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
911#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
912#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
913#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
914#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
915#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
916#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
917#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
918#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
919#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
920#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
921#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
922#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
923#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
924#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
925#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
926
927/* Port Interrubfin_read_()t 2 Registers (32-bit) */
928
929#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
930#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
931#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
932#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
933#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
934#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
935#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
936#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
937#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
938#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
939#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
940#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
941#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
942#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
943#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
944#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
945#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
946#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
947#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
948#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
949
950/* Port Interrubfin_read_()t 3 Registers (32-bit) */
951
952#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
953#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
954#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
955#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
956#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
957#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
958#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
959#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
960#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
961#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
962#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
963#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
964#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
965#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
966#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
967#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
968#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
969#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
970#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
971#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
972
973/* Port A Registers */
974
975#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
976#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
977#define bfin_read_PORTA() bfin_read16(PORTA)
978#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
979#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
980#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
981#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
982#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
983#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
984#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
985#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
986#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
987#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
988#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
989#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
990#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
991
992/* Port B Registers */
993
994#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
995#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
996#define bfin_read_PORTB() bfin_read16(PORTB)
997#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
998#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
999#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
1000#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
1001#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
1002#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
1003#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
1004#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
1005#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
1006#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
1007#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
1008#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
1009#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
1010
1011/* Port C Registers */
1012
1013#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
1014#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
1015#define bfin_read_PORTC() bfin_read16(PORTC)
1016#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
1017#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
1018#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
1019#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
1020#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
1021#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
1022#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
1023#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
1024#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
1025#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
1026#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
1027#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
1028#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
1029
1030/* Port D Registers */
1031
1032#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
1033#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
1034#define bfin_read_PORTD() bfin_read16(PORTD)
1035#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
1036#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
1037#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
1038#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
1039#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
1040#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
1041#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
1042#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
1043#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
1044#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
1045#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
1046#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
1047#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
1048
1049/* Port E Registers */
1050
1051#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
1052#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
1053#define bfin_read_PORTE() bfin_read16(PORTE)
1054#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
1055#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
1056#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
1057#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
1058#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
1059#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
1060#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
1061#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
1062#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
1063#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
1064#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
1065#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
1066#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
1067
1068/* Port F Registers */
1069
1070#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1071#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1072#define bfin_read_PORTF() bfin_read16(PORTF)
1073#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
1074#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
1075#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
1076#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
1077#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
1078#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
1079#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
1080#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
1081#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
1082#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
1083#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
1084#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
1085#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1086
1087/* Port G Registers */
1088
1089#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1090#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1091#define bfin_read_PORTG() bfin_read16(PORTG)
1092#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
1093#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
1094#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
1095#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
1096#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
1097#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
1098#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
1099#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
1100#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1101#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
1102#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
1103#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
1104#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1105
1106/* Port H Registers */
1107
1108#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1109#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1110#define bfin_read_PORTH() bfin_read16(PORTH)
1111#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
1112#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
1113#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
1114#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
1115#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
1116#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
1117#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
1118#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
1119#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1120#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
1121#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
1122#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
1123#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1124
1125/* Port I Registers */
1126
1127#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
1128#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
1129#define bfin_read_PORTI() bfin_read16(PORTI)
1130#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
1131#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
1132#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
1133#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
1134#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
1135#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
1136#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
1137#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
1138#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1139#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
1140#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
1141#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
1142#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1143
1144/* Port J Registers */
1145
1146#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
1147#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
1148#define bfin_read_PORTJ() bfin_read16(PORTJ)
1149#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
1150#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
1151#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
1152#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
1153#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
1154#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
1155#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
1156#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
1157#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1158#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
1159#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
1160#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
1161#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1162
1163/* PWM Timer Registers */
1164
1165#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
1166#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
1167#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
1168#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1169#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
1170#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1171#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
1172#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1173#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
1174#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
1175#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
1176#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1177#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
1178#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1179#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
1180#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1181#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
1182#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
1183#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
1184#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1185#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
1186#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1187#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
1188#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1189#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
1190#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
1191#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
1192#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1193#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
1194#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1195#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
1196#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1197#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
1198#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
1199#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
1200#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1201#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
1202#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1203#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
1204#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1205#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
1206#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
1207#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
1208#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1209#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
1210#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1211#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
1212#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1213#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
1214#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
1215#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
1216#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1217#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
1218#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1219#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
1220#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1221#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
1222#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
1223#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
1224#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1225#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
1226#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1227#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
1228#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1229
1230/* Timer Groubfin_read_() of 8 */
1231
1232#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
1233#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
1234#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
1235#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
1236#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
1237#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1238
1239/* DMAC1 Registers */
1240
1241#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
1242#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
1243#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
1244#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
1245
1246/* DMA Channel 12 Registers */
1247
1248#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1249#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR)
1250#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1251#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR)
1252#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1253#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1254#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1255#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1256#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1257#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY)
1258#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1259#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1260#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1261#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY)
1262#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1263#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR)
1264#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1265#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR)
1266#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1267#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1268#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
1269#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
1270#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
1271#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
1272#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
1273#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
1274
1275/* DMA Channel 13 Registers */
1276
1277#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1278#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR)
1279#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1280#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR)
1281#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1282#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1283#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1284#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1285#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1286#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY)
1287#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1288#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1289#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1290#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY)
1291#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1292#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR)
1293#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1294#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR)
1295#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1296#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1297#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
1298#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
1299#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
1300#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
1301#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
1302#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
1303
1304/* DMA Channel 14 Registers */
1305
1306#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1307#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR)
1308#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1309#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR)
1310#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1311#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1312#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1313#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1314#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1315#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY)
1316#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1317#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1318#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1319#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY)
1320#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1321#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR)
1322#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1323#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR)
1324#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1325#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1326#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
1327#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
1328#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
1329#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
1330#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
1331#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
1332
1333/* DMA Channel 15 Registers */
1334
1335#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1336#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR)
1337#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1338#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR)
1339#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1340#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1341#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1342#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1343#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1344#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY)
1345#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1346#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1347#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1348#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY)
1349#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1350#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR)
1351#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1352#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR)
1353#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1354#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1355#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
1356#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
1357#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
1358#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
1359#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
1360#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
1361
1362/* DMA Channel 16 Registers */
1363
1364#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1365#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR)
1366#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1367#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR)
1368#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1369#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1370#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1371#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1372#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1373#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY)
1374#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1375#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1376#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1377#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY)
1378#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1379#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR)
1380#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1381#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR)
1382#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1383#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1384#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
1385#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
1386#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
1387#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
1388#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
1389#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
1390
1391/* DMA Channel 17 Registers */
1392
1393#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1394#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR)
1395#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1396#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR)
1397#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1398#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1399#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1400#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1401#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1402#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY)
1403#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1404#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1405#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1406#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY)
1407#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1408#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR)
1409#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1410#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR)
1411#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1412#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1413#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
1414#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
1415#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
1416#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
1417#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
1418#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
1419
1420/* DMA Channel 18 Registers */
1421
1422#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1423#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR)
1424#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1425#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR)
1426#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1427#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1428#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1429#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1430#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1431#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY)
1432#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1433#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1434#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1435#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY)
1436#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1437#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR)
1438#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1439#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR)
1440#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1441#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1442#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
1443#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
1444#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
1445#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
1446#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
1447#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
1448
1449/* DMA Channel 19 Registers */
1450
1451#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1452#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR)
1453#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1454#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR)
1455#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1456#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1457#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1458#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1459#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1460#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY)
1461#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1462#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1463#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1464#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY)
1465#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1466#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR)
1467#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1468#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR)
1469#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1470#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1471#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
1472#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1473#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
1474#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1475#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
1476#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1477
1478/* DMA Channel 20 Registers */
1479
1480#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1481#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR)
1482#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1483#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR)
1484#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1485#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1486#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1487#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1488#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1489#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY)
1490#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1491#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1492#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1493#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY)
1494#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1495#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR)
1496#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1497#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR)
1498#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1499#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1500#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
1501#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
1502#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
1503#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
1504#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
1505#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
1506
1507/* DMA Channel 21 Registers */
1508
1509#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1510#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR)
1511#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1512#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR)
1513#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1514#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1515#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1516#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1517#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1518#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY)
1519#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1520#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1521#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1522#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY)
1523#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1524#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR)
1525#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1526#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR)
1527#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1528#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1529#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
1530#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
1531#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
1532#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
1533#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
1534#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
1535
1536/* DMA Channel 22 Registers */
1537
1538#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1539#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR)
1540#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1541#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR)
1542#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1543#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1544#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1545#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1546#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1547#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY)
1548#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1549#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1550#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1551#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY)
1552#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1553#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR)
1554#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1555#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR)
1556#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1557#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1558#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
1559#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
1560#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
1561#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
1562#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
1563#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
1564
1565/* DMA Channel 23 Registers */
1566
1567#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1568#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR)
1569#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1570#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR)
1571#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1572#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1573#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1574#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1575#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1576#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY)
1577#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1578#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1579#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1580#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY)
1581#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1582#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR)
1583#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1584#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR)
1585#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1586#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1587#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
1588#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1589#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
1590#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1591#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
1592#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1593
1594/* MDMA Stream 2 Registers */
1595
1596#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1597#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR)
1598#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1599#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR)
1600#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1601#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1602#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1603#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1604#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1605#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY)
1606#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1607#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1608#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1609#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY)
1610#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1611#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR)
1612#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1613#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR)
1614#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1615#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1616#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1617#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1618#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1619#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1620#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1621#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1622#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1623#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR)
1624#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1625#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR)
1626#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1627#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1628#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1629#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1630#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1631#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY)
1632#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1633#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1634#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1635#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY)
1636#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1637#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR)
1638#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1639#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR)
1640#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1641#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1642#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1643#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1644#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1645#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1646#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1647#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1648
1649/* MDMA Stream 3 Registers */
1650
1651#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1652#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR)
1653#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1654#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR)
1655#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1656#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1657#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1658#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1659#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1660#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY)
1661#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1662#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1663#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1664#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY)
1665#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1666#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR)
1667#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1668#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR)
1669#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1670#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1671#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1672#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1673#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1674#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1675#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1676#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1677#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1678#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR)
1679#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1680#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR)
1681#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1682#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1683#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1684#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1685#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1686#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY)
1687#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1688#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1689#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1690#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY)
1691#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1692#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR)
1693#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1694#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR)
1695#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1696#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1697#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1698#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1699#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1700#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1701#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1702#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1703
1704/* UART1 Registers */
1705
1706#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1707#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1708#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1709#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1710#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1711#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1712#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1713#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1714#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1715#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1716#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1717#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1718#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1719#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1720#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1721#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1722#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
1723#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
1724#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
1725#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
1726#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1727#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1728#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1729#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1730
1731/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
1732
1733/* SPI1 Registers */
1734
1735#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
1736#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
1737#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
1738#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
1739#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
1740#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
1741#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
1742#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
1743#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
1744#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
1745#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
1746#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
1747#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
1748#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
1749
1750/* SPORT2 Registers */
1751
1752#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
1753#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
1754#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
1755#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
1756#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
1757#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
1758#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
1759#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
1760#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
1761#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1762#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
1763#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1764#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
1765#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
1766#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
1767#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
1768#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1769#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
1770#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
1771#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
1772#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
1773#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
1774#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
1775#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
1776#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
1777#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
1778#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
1779#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
1780#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
1781#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1782#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
1783#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1784#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
1785#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1786#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
1787#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1788#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
1789#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1790#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
1791#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1792#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
1793#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1794#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
1795#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1796
1797/* SPORT3 Registers */
1798
1799#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
1800#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
1801#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
1802#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
1803#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
1804#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
1805#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
1806#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
1807#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
1808#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1809#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
1810#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1811#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
1812#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
1813#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
1814#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
1815#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
1816#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
1817#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
1818#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
1819#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
1820#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
1821#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
1822#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
1823#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
1824#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
1825#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
1826#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
1827#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
1828#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1829#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
1830#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1831#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
1832#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1833#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
1834#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1835#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
1836#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1837#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
1838#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1839#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
1840#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1841#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
1842#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1843
1844/* EPPI2 Registers */
1845
1846#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
1847#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
1848#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
1849#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
1850#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
1851#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
1852#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
1853#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
1854#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
1855#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
1856#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
1857#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
1858#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
1859#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
1860#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
1861#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
1862#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
1863#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1864#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
1865#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1866#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
1867#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1868#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
1869#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1870#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
1871#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1872#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
1873#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
1874
1875/* CAN Controller 0 Config 1 Registers */
1876
1877#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
1878#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
1879#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
1880#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
1881#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
1882#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
1883#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
1884#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
1885#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
1886#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
1887#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
1888#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
1889#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
1890#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
1891#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
1892#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
1893#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
1894#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
1895#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
1896#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
1897#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
1898#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
1899#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
1900#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
1901#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
1902#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
1903
1904/* CAN Controller 0 Config 2 Registers */
1905
1906#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
1907#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
1908#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
1909#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
1910#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
1911#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
1912#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
1913#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
1914#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
1915#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
1916#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
1917#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
1918#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
1919#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
1920#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
1921#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
1922#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
1923#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
1924#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
1925#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
1926#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
1927#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
1928#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
1929#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
1930#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
1931#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
1932
1933/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
1934
1935#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
1936#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
1937#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
1938#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
1939#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
1940#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
1941#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
1942#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
1943#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
1944#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
1945#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
1946#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
1947#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
1948#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
1949#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
1950#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
1951#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
1952#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
1953#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
1954#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
1955#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
1956#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
1957#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
1958#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
1959#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
1960#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
1961#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
1962#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
1963#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
1964#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
1965#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
1966#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
1967
1968/* CAN Controller 0 Accebfin_read_()tance Registers */
1969
1970#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
1971#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
1972#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
1973#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
1974#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
1975#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
1976#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
1977#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
1978#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
1979#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
1980#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
1981#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
1982#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
1983#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
1984#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
1985#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
1986#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
1987#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
1988#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
1989#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
1990#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
1991#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
1992#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
1993#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
1994#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
1995#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
1996#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
1997#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
1998#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
1999#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
2000#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
2001#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
2002#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
2003#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
2004#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
2005#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
2006#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
2007#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
2008#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
2009#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
2010#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
2011#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
2012#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
2013#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
2014#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
2015#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
2016#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
2017#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
2018#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
2019#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
2020#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
2021#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
2022#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
2023#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
2024#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
2025#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
2026#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
2027#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
2028#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
2029#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
2030#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
2031#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2032#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2033#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2034
2035/* CAN Controller 0 Accebfin_read_()tance Registers */
2036
2037#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2038#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2039#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2040#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2041#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2042#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2043#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2044#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2045#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2046#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2047#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2048#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2049#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2050#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2051#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2052#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2053#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2054#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2055#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2056#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2057#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2058#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2059#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2060#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2061#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2062#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2063#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2064#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2065#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2066#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2067#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2068#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2069#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2070#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2071#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2072#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2073#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2074#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2075#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2076#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2077#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2078#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2079#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2080#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2081#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2082#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2083#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2084#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2085#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2086#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2087#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2088#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2089#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2090#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2091#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2092#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2093#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2094#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2095#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2096#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2097#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2098#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2099#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2100#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2101
2102/* CAN Controller 0 Mailbox Data Registers */
2103
2104#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2105#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2106#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2107#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2108#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2109#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2110#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2111#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2112#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2113#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2114#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2115#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2116#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2117#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2118#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2119#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2120#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2121#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2122#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2123#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2124#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2125#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2126#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2127#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2128#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2129#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2130#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2131#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2132#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2133#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2134#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2135#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2136#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2137#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2138#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2139#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2140#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2141#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2142#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2143#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2144#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2145#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2146#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2147#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2148#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2149#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2150#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2151#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2152#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2153#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2154#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2155#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2156#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2157#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2158#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2159#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2160#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2161#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2162#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2163#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2164#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2165#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2166#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2167#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2168#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2169#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2170#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2171#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2172#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2173#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2174#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2175#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2176#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2177#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2178#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2179#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2180#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2181#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2182#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2183#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2184#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2185#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2186#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2187#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2188#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2189#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2190#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2191#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2192#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2193#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2194#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2195#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2196#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2197#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2198#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2199#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2200#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2201#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2202#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2203#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2204#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2205#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2206#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2207#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2208#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2209#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2210#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2211#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2212#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2213#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2214#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2215#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2216#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2217#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2218#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2219#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2220#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2221#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2222#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2223#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2224#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2225#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2226#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2227#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2228#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2229#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2230#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2231#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2232#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2233#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2234#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2235#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2236#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2237#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2238#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2239#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2240#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2241#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2242#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2243#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2244#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2245#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2246#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2247#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2248#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2249#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2250#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2251#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2252#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2253#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2254#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2255#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2256#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2257#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2258#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2259#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2260#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2261#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2262#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2263#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2264#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2265#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2266#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2267#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2268#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2269#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2270#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2271#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2272#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2273#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2274#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2275#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2276#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2277#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2278#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2279#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2280#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2281#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2282#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2283#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2284#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2285#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2286#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2287#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2288#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2289#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2290#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2291#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2292#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2293#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2294#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2295#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2296#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2297#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2298#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2299#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2300#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2301#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2302#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2303#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2304#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2305#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2306#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2307#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2308#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2309#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2310#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2311#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2312#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2313#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2314#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2315#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2316#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2317#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2318#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2319#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2320#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2321#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2322#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2323#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2324#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2325#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2326#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2327#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2328#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2329#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2330#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2331#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2332#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2333#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2334#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2335#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2336#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2337#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2338#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2339#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2340#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2341#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2342#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2343#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2344#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2345#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2346#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2347#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2348#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2349#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2350#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2351#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2352#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2353#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2354#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2355#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2356#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2357#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2358#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2359#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2360
2361/* CAN Controller 0 Mailbox Data Registers */
2362
2363#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2364#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2365#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2366#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2367#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2368#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2369#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2370#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2371#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2372#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2373#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2374#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2375#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2376#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2377#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2378#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2379#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2380#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2381#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2382#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2383#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2384#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2385#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2386#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2387#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2388#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2389#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2390#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2391#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2392#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2393#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2394#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2395#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2396#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2397#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2398#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2399#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2400#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2401#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2402#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2403#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2404#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2405#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2406#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2407#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2408#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2409#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2410#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2411#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2412#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2413#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2414#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2415#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2416#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2417#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2418#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2419#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2420#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2421#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2422#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2423#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2424#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2425#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2426#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2427#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2428#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2429#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2430#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2431#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2432#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2433#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2434#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2435#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2436#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2437#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2438#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2439#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2440#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2441#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2442#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2443#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2444#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2445#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2446#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2447#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2448#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2449#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2450#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2451#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2452#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
2453#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
2454#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
2455#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
2456#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
2457#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
2458#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
2459#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
2460#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
2461#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
2462#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
2463#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
2464#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
2465#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
2466#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
2467#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
2468#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
2469#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
2470#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
2471#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
2472#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
2473#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
2474#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
2475#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
2476#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
2477#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
2478#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
2479#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
2480#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
2481#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
2482#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
2483#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
2484#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
2485#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
2486#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
2487#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
2488#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
2489#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
2490#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
2491#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
2492#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
2493#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
2494#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
2495#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
2496#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
2497#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
2498#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
2499#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
2500#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
2501#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
2502#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
2503#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
2504#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
2505#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
2506#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
2507#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
2508#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
2509#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
2510#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
2511#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
2512#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
2513#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
2514#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
2515#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
2516#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
2517#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
2518#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
2519#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
2520#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
2521#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
2522#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
2523#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
2524#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
2525#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
2526#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
2527#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
2528#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
2529#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
2530#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
2531#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
2532#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
2533#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
2534#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
2535#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
2536#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
2537#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
2538#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
2539#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
2540#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
2541#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
2542#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
2543#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
2544#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
2545#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
2546#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
2547#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
2548#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
2549#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
2550#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
2551#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
2552#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
2553#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
2554#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
2555#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
2556#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
2557#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
2558#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
2559#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
2560#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
2561#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
2562#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
2563#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
2564#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
2565#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
2566#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
2567#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
2568#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
2569#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
2570#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
2571#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
2572#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
2573#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
2574#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
2575#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
2576#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
2577#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
2578#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
2579#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
2580#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
2581#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
2582#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
2583#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
2584#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
2585#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
2586#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
2587#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
2588#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
2589#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
2590#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
2591#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
2592#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
2593#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
2594#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
2595#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
2596#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
2597#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
2598#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
2599#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
2600#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
2601#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
2602#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
2603#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
2604#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
2605#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
2606#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
2607#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
2608#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
2609#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
2610#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
2611#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
2612#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
2613#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
2614#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
2615#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
2616#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
2617#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
2618#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
2619
2620/* UART3 Registers */
2621
2622#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
2623#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
2624#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
2625#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
2626#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
2627#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
2628#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
2629#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
2630#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
2631#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
2632#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
2633#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
2634#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
2635#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
2636#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
2637#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
2638#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
2639#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
2640#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
2641#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
2642#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
2643#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
2644#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
2645#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
2646
2647/* NFC Registers */
2648
2649#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
2650#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
2651#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
2652#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
2653#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
2654#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
2655#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
2656#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
2657#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
2658#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
2659#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
2660#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
2661#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
2662#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
2663#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
2664#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
2665#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
2666#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
2667#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
2668#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
2669#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
2670#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
2671#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
2672#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
2673#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
2674#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
2675#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
2676#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
2677#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
2678#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
2679#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
2680#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
2681
2682/* Counter Registers */
2683
2684#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
2685#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
2686#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
2687#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
2688#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
2689#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
2690#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
2691#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
2692#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
2693#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
2694#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
2695#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2696#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
2697#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2698#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2699#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2700
2701/* OTP/FUSE Registers */
2702
2703#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2704#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2705#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2706#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2707#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2708#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2709#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2710#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2711
2712/* Security Registers */
2713
2714#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
2715#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2716#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
2717#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2718#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
2719#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
2720
2721/* DMA Peribfin_read_()heral Mux Register */
2722
2723#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2724#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2725
2726/* OTP Read/Write Data Buffer Registers */
2727
2728#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2729#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2730#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2731#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2732#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2733#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2734#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2735#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2736
2737/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2738
2739/* legacy definitions */
2740#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2741#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2742#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2743#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2744#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2745#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2746#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2747#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2748#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2749#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2750#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2751#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2752
2753#endif /* _CDEF_BF54X_H */
2754