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Dhaval Patel14d46ce2017-01-17 16:28:12 -08001/*
2 * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07005 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -08006 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07009 *
Dhaval Patel14d46ce2017-01-17 16:28:12 -080010 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070017 */
18
Clarence Ipd9f9fa62016-09-09 13:42:32 -040019#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040020#include <linux/sort.h>
Clarence Ip8f7366c2016-07-05 12:15:26 -040021#include <linux/debugfs.h>
Clarence Ipcae1bb62016-07-07 12:07:13 -040022#include <linux/ktime.h>
Clarence Ip4c1d9772016-06-26 09:35:38 -040023#include <uapi/drm/sde_drm.h>
Narendra Muppalla1b0b3352015-09-29 10:16:51 -070024#include <drm/drm_mode.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_flip_work.h>
28
29#include "sde_kms.h"
30#include "sde_hw_lm.h"
Clarence Ipc475b082016-06-26 09:27:23 -040031#include "sde_hw_ctl.h"
Abhijit Kulkarni40e38162016-06-26 22:12:09 -040032#include "sde_crtc.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040033#include "sde_plane.h"
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -070034#include "sde_color_processing.h"
Alan Kwong83285fb2016-10-21 20:51:17 -040035#include "sde_encoder.h"
36#include "sde_connector.h"
Alan Kwong67a3f792016-11-01 23:16:53 -040037#include "sde_power_handle.h"
Alan Kwong9aa061c2016-11-06 21:17:12 -050038#include "sde_core_perf.h"
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040039
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -070040struct sde_crtc_irq_info {
41 struct sde_irq_callback irq;
42 u32 event;
43 int (*func)(struct drm_crtc *crtc, bool en,
44 struct sde_irq_callback *irq);
45 struct list_head list;
46};
47
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -070048struct sde_crtc_custom_events {
49 u32 event;
50 int (*func)(struct drm_crtc *crtc, bool en,
51 struct sde_irq_callback *irq);
52};
53
54static struct sde_crtc_custom_events custom_events[] = {
55 {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt}
56};
57
Clarence Ipcae1bb62016-07-07 12:07:13 -040058/* default input fence timeout, in ms */
59#define SDE_CRTC_INPUT_FENCE_TIMEOUT 2000
60
Dhaval Patel4e574842016-08-23 15:11:37 -070061/*
62 * The default input fence timeout is 2 seconds while max allowed
63 * range is 10 seconds. Any value above 10 seconds adds glitches beyond
64 * tolerance limit.
65 */
66#define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000
67
Dhaval Patel48c76022016-09-01 17:51:23 -070068/* layer mixer index on sde_crtc */
69#define LEFT_MIXER 0
70#define RIGHT_MIXER 1
71
Dhaval Patelf9245d62017-03-28 16:24:00 -070072#define MISR_BUFF_SIZE 256
73
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -040074static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040075{
Clarence Ip7f70ce42017-03-20 06:53:46 -070076 struct msm_drm_private *priv;
77
78 if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
79 SDE_ERROR("invalid crtc\n");
80 return NULL;
81 }
82 priv = crtc->dev->dev_private;
83 if (!priv || !priv->kms) {
84 SDE_ERROR("invalid kms\n");
85 return NULL;
86 }
Abhijit Kulkarni40e38162016-06-26 22:12:09 -040087
Ben Chan78647cd2016-06-26 22:02:47 -040088 return to_sde_kms(priv->kms);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -040089}
90
Dhaval Patelf9245d62017-03-28 16:24:00 -070091static inline int _sde_crtc_power_enable(struct sde_crtc *sde_crtc, bool enable)
92{
93 struct drm_crtc *crtc;
94 struct msm_drm_private *priv;
95 struct sde_kms *sde_kms;
96
97 if (!sde_crtc) {
98 SDE_ERROR("invalid sde crtc\n");
99 return -EINVAL;
100 }
101
102 crtc = &sde_crtc->base;
103 if (!crtc->dev || !crtc->dev->dev_private) {
104 SDE_ERROR("invalid drm device\n");
105 return -EINVAL;
106 }
107
108 priv = crtc->dev->dev_private;
109 if (!priv->kms) {
110 SDE_ERROR("invalid kms\n");
111 return -EINVAL;
112 }
113
114 sde_kms = to_sde_kms(priv->kms);
115
116 return sde_power_resource_enable(&priv->phandle, sde_kms->core_client,
117 enable);
118}
119
Alan Kwongcdb2f282017-03-18 13:42:06 -0700120/**
121 * _sde_crtc_rp_to_crtc - get crtc from resource pool object
122 * @rp: Pointer to resource pool
123 * return: Pointer to drm crtc if success; null otherwise
124 */
125static struct drm_crtc *_sde_crtc_rp_to_crtc(struct sde_crtc_respool *rp)
126{
127 if (!rp)
128 return NULL;
129
130 return container_of(rp, struct sde_crtc_state, rp)->base.crtc;
131}
132
133/**
134 * _sde_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool
135 * @rp: Pointer to resource pool
136 * @force: True to reclaim all resources; otherwise, reclaim only unused ones
137 * return: None
138 */
139static void _sde_crtc_rp_reclaim(struct sde_crtc_respool *rp, bool force)
140{
141 struct sde_crtc_res *res, *next;
142 struct drm_crtc *crtc;
143
144 crtc = _sde_crtc_rp_to_crtc(rp);
145 if (!crtc) {
146 SDE_ERROR("invalid crtc\n");
147 return;
148 }
149
150 SDE_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id,
151 force ? "destroy" : "free_unused");
152
153 list_for_each_entry_safe(res, next, &rp->res_list, list) {
154 if (!force && !(res->flags & SDE_CRTC_RES_FLAG_FREE))
155 continue;
156 SDE_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n",
157 crtc->base.id, rp->sequence_id,
158 res->type, res->tag, res->val,
159 atomic_read(&res->refcount));
160 list_del(&res->list);
161 if (res->ops.put)
162 res->ops.put(res->val);
163 kfree(res);
164 }
165}
166
167/**
168 * _sde_crtc_rp_free_unused - free unused resource in pool
169 * @rp: Pointer to resource pool
170 * return: none
171 */
172static void _sde_crtc_rp_free_unused(struct sde_crtc_respool *rp)
173{
174 _sde_crtc_rp_reclaim(rp, false);
175}
176
177/**
178 * _sde_crtc_rp_destroy - destroy resource pool
179 * @rp: Pointer to resource pool
180 * return: None
181 */
182static void _sde_crtc_rp_destroy(struct sde_crtc_respool *rp)
183{
184 _sde_crtc_rp_reclaim(rp, true);
185}
186
187/**
188 * _sde_crtc_hw_blk_get - get callback for hardware block
189 * @val: Resource handle
190 * @type: Resource type
191 * @tag: Search tag for given resource
192 * return: Resource handle
193 */
194static void *_sde_crtc_hw_blk_get(void *val, u32 type, u64 tag)
195{
196 SDE_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val);
197 return sde_hw_blk_get(val, type, tag);
198}
199
200/**
201 * _sde_crtc_hw_blk_put - put callback for hardware block
202 * @val: Resource handle
203 * return: None
204 */
205static void _sde_crtc_hw_blk_put(void *val)
206{
207 SDE_DEBUG("res://%pK\n", val);
208 sde_hw_blk_put(val);
209}
210
211/**
212 * _sde_crtc_rp_duplicate - duplicate resource pool and reset reference count
213 * @rp: Pointer to original resource pool
214 * @dup_rp: Pointer to duplicated resource pool
215 * return: None
216 */
217static void _sde_crtc_rp_duplicate(struct sde_crtc_respool *rp,
218 struct sde_crtc_respool *dup_rp)
219{
220 struct sde_crtc_res *res, *dup_res;
221 struct drm_crtc *crtc;
222
223 if (!rp || !dup_rp) {
224 SDE_ERROR("invalid resource pool\n");
225 return;
226 }
227
228 crtc = _sde_crtc_rp_to_crtc(rp);
229 if (!crtc) {
230 SDE_ERROR("invalid crtc\n");
231 return;
232 }
233
234 SDE_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id);
235
236 dup_rp->sequence_id = rp->sequence_id + 1;
237 INIT_LIST_HEAD(&dup_rp->res_list);
238 dup_rp->ops = rp->ops;
239 list_for_each_entry(res, &rp->res_list, list) {
240 dup_res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL);
241 if (!dup_res)
242 return;
243 INIT_LIST_HEAD(&dup_res->list);
244 atomic_set(&dup_res->refcount, 0);
245 dup_res->type = res->type;
246 dup_res->tag = res->tag;
247 dup_res->val = res->val;
248 dup_res->ops = res->ops;
249 dup_res->flags = SDE_CRTC_RES_FLAG_FREE;
250 SDE_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n",
251 crtc->base.id, dup_rp->sequence_id,
252 dup_res->type, dup_res->tag, dup_res->val,
253 atomic_read(&dup_res->refcount));
254 list_add_tail(&dup_res->list, &dup_rp->res_list);
255 if (dup_res->ops.get)
256 dup_res->ops.get(dup_res->val, 0, -1);
257 }
258}
259
260/**
261 * _sde_crtc_rp_reset - reset resource pool after allocation
262 * @rp: Pointer to original resource pool
263 * return: None
264 */
265static void _sde_crtc_rp_reset(struct sde_crtc_respool *rp)
266{
267 if (!rp) {
268 SDE_ERROR("invalid resource pool\n");
269 return;
270 }
271
272 rp->sequence_id = 0;
273 INIT_LIST_HEAD(&rp->res_list);
274 rp->ops.get = _sde_crtc_hw_blk_get;
275 rp->ops.put = _sde_crtc_hw_blk_put;
276}
277
278/**
279 * _sde_crtc_rp_add - add given resource to resource pool
280 * @rp: Pointer to original resource pool
281 * @type: Resource type
282 * @tag: Search tag for given resource
283 * @val: Resource handle
284 * @ops: Resource callback operations
285 * return: 0 if success; error code otherwise
286 */
287static int _sde_crtc_rp_add(struct sde_crtc_respool *rp, u32 type, u64 tag,
288 void *val, struct sde_crtc_res_ops *ops)
289{
290 struct sde_crtc_res *res;
291 struct drm_crtc *crtc;
292
293 if (!rp || !ops) {
294 SDE_ERROR("invalid resource pool/ops\n");
295 return -EINVAL;
296 }
297
298 crtc = _sde_crtc_rp_to_crtc(rp);
299 if (!crtc) {
300 SDE_ERROR("invalid crtc\n");
301 return -EINVAL;
302 }
303
304 list_for_each_entry(res, &rp->res_list, list) {
305 if (res->type != type || res->tag != tag)
306 continue;
307 SDE_ERROR("crtc%d.%u already exist res:0x%x/0x%llx/%pK/%d\n",
308 crtc->base.id, rp->sequence_id,
309 res->type, res->tag, res->val,
310 atomic_read(&res->refcount));
311 return -EEXIST;
312 }
313 res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL);
314 if (!res)
315 return -ENOMEM;
316 INIT_LIST_HEAD(&res->list);
317 atomic_set(&res->refcount, 1);
318 res->type = type;
319 res->tag = tag;
320 res->val = val;
321 res->ops = *ops;
322 list_add_tail(&res->list, &rp->res_list);
323 SDE_DEBUG("crtc%d.%u added res:0x%x/0x%llx\n",
324 crtc->base.id, rp->sequence_id, type, tag);
325 return 0;
326}
327
328/**
329 * _sde_crtc_rp_get - lookup the resource from given resource pool and obtain
330 * if available; otherwise, obtain resource from global pool
331 * @rp: Pointer to original resource pool
332 * @type: Resource type
333 * @tag: Search tag for given resource
334 * return: Resource handle if success; pointer error or null otherwise
335 */
336static void *_sde_crtc_rp_get(struct sde_crtc_respool *rp, u32 type, u64 tag)
337{
338 struct sde_crtc_res *res;
339 void *val = NULL;
340 int rc;
341 struct drm_crtc *crtc;
342
343 if (!rp) {
344 SDE_ERROR("invalid resource pool\n");
345 return NULL;
346 }
347
348 crtc = _sde_crtc_rp_to_crtc(rp);
349 if (!crtc) {
350 SDE_ERROR("invalid crtc\n");
351 return NULL;
352 }
353
354 list_for_each_entry(res, &rp->res_list, list) {
355 if (res->type != type || res->tag != tag)
356 continue;
357 SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n",
358 crtc->base.id, rp->sequence_id,
359 res->type, res->tag, res->val,
360 atomic_read(&res->refcount));
361 atomic_inc(&res->refcount);
362 res->flags &= ~SDE_CRTC_RES_FLAG_FREE;
363 return res->val;
364 }
365 list_for_each_entry(res, &rp->res_list, list) {
366 if (res->type != type || !(res->flags & SDE_CRTC_RES_FLAG_FREE))
367 continue;
368 SDE_DEBUG("crtc%d.%u retag res:0x%x/0x%llx/%pK/%d\n",
369 crtc->base.id, rp->sequence_id,
370 res->type, res->tag, res->val,
371 atomic_read(&res->refcount));
372 atomic_inc(&res->refcount);
373 res->tag = tag;
374 res->flags &= ~SDE_CRTC_RES_FLAG_FREE;
375 return res->val;
376 }
377 if (rp->ops.get)
378 val = rp->ops.get(NULL, type, -1);
379 if (IS_ERR_OR_NULL(val)) {
380 SDE_ERROR("crtc%d.%u failed to get res:0x%x//\n",
381 crtc->base.id, rp->sequence_id, type);
382 return NULL;
383 }
384 rc = _sde_crtc_rp_add(rp, type, tag, val, &rp->ops);
385 if (rc) {
386 SDE_ERROR("crtc%d.%u failed to add res:0x%x/0x%llx\n",
387 crtc->base.id, rp->sequence_id, type, tag);
388 if (rp->ops.put)
389 rp->ops.put(val);
390 val = NULL;
391 }
392 return val;
393}
394
395/**
396 * _sde_crtc_rp_put - return given resource to resource pool
397 * @rp: Pointer to original resource pool
398 * @type: Resource type
399 * @tag: Search tag for given resource
400 * return: None
401 */
402static void _sde_crtc_rp_put(struct sde_crtc_respool *rp, u32 type, u64 tag)
403{
404 struct sde_crtc_res *res, *next;
405 struct drm_crtc *crtc;
406
407 if (!rp) {
408 SDE_ERROR("invalid resource pool\n");
409 return;
410 }
411
412 crtc = _sde_crtc_rp_to_crtc(rp);
413 if (!crtc) {
414 SDE_ERROR("invalid crtc\n");
415 return;
416 }
417
418 list_for_each_entry_safe(res, next, &rp->res_list, list) {
419 if (res->type != type || res->tag != tag)
420 continue;
421 SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n",
422 crtc->base.id, rp->sequence_id,
423 res->type, res->tag, res->val,
424 atomic_read(&res->refcount));
425 if (res->flags & SDE_CRTC_RES_FLAG_FREE)
426 SDE_ERROR(
427 "crtc%d.%u already free res:0x%x/0x%llx/%pK/%d\n",
428 crtc->base.id, rp->sequence_id,
429 res->type, res->tag, res->val,
430 atomic_read(&res->refcount));
431 else if (atomic_dec_return(&res->refcount) == 0)
432 res->flags |= SDE_CRTC_RES_FLAG_FREE;
433
434 return;
435 }
436 SDE_ERROR("crtc%d.%u not found res:0x%x/0x%llx\n",
437 crtc->base.id, rp->sequence_id, type, tag);
438}
439
440int sde_crtc_res_add(struct drm_crtc_state *state, u32 type, u64 tag,
441 void *val, struct sde_crtc_res_ops *ops)
442{
443 struct sde_crtc_respool *rp;
444
445 if (!state) {
446 SDE_ERROR("invalid parameters\n");
447 return -EINVAL;
448 }
449
450 rp = &to_sde_crtc_state(state)->rp;
451 return _sde_crtc_rp_add(rp, type, tag, val, ops);
452}
453
454void *sde_crtc_res_get(struct drm_crtc_state *state, u32 type, u64 tag)
455{
456 struct sde_crtc_respool *rp;
457 void *val;
458
459 if (!state) {
460 SDE_ERROR("invalid parameters\n");
461 return NULL;
462 }
463
464 rp = &to_sde_crtc_state(state)->rp;
465 val = _sde_crtc_rp_get(rp, type, tag);
466 if (IS_ERR(val)) {
467 SDE_ERROR("failed to get res type:0x%x:0x%llx\n",
468 type, tag);
469 return NULL;
470 }
471
472 return val;
473}
474
475void sde_crtc_res_put(struct drm_crtc_state *state, u32 type, u64 tag)
476{
477 struct sde_crtc_respool *rp;
478
479 if (!state) {
480 SDE_ERROR("invalid parameters\n");
481 return;
482 }
483
484 rp = &to_sde_crtc_state(state)->rp;
485 _sde_crtc_rp_put(rp, type, tag);
486}
487
Clarence Ipa18d4832017-03-13 12:35:44 -0700488static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc)
489{
490 if (!sde_crtc)
491 return;
492
493 if (sde_crtc->event_thread) {
494 kthread_flush_worker(&sde_crtc->event_worker);
495 kthread_stop(sde_crtc->event_thread);
496 sde_crtc->event_thread = NULL;
497 }
498}
499
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700500static void sde_crtc_destroy(struct drm_crtc *crtc)
501{
502 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
503
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -0400504 SDE_DEBUG("\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -0400505
506 if (!crtc)
507 return;
508
Dhaval Patele4a5dda2016-10-13 19:29:30 -0700509 if (sde_crtc->blob_info)
510 drm_property_unreference_blob(sde_crtc->blob_info);
Clarence Ip7a753bb2016-07-07 11:47:44 -0400511 msm_property_destroy(&sde_crtc->property_info);
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -0700512 sde_cp_crtc_destroy_properties(crtc);
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -0700513
Clarence Ip24f80662016-06-13 19:05:32 -0400514 sde_fence_deinit(&sde_crtc->output_fence);
Clarence Ipa18d4832017-03-13 12:35:44 -0700515 _sde_crtc_deinit_events(sde_crtc);
Clarence Ip7a753bb2016-07-07 11:47:44 -0400516
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700517 drm_crtc_cleanup(crtc);
Clarence Ip7f70ce42017-03-20 06:53:46 -0700518 mutex_destroy(&sde_crtc->crtc_lock);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700519 kfree(sde_crtc);
520}
521
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700522static bool sde_crtc_mode_fixup(struct drm_crtc *crtc,
523 const struct drm_display_mode *mode,
524 struct drm_display_mode *adjusted_mode)
525{
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -0400526 SDE_DEBUG("\n");
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -0400527
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -0400528 if (msm_is_mode_seamless(adjusted_mode) &&
529 (!crtc->enabled || crtc->state->active_changed)) {
530 SDE_ERROR("crtc state prevents seamless transition\n");
531 return false;
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -0400532 }
533
Narendra Muppalla1b0b3352015-09-29 10:16:51 -0700534 return true;
535}
536
Dhaval Patel48c76022016-09-01 17:51:23 -0700537static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer,
538 struct sde_plane_state *pstate, struct sde_format *format)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400539{
Dhaval Patel48c76022016-09-01 17:51:23 -0700540 uint32_t blend_op, fg_alpha, bg_alpha;
541 uint32_t blend_type;
Dhaval Patel44f12472016-08-29 12:19:47 -0700542 struct sde_hw_mixer *lm = mixer->hw_lm;
543
Dhaval Patel48c76022016-09-01 17:51:23 -0700544 /* default to opaque blending */
545 fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA);
546 bg_alpha = 0xFF - fg_alpha;
547 blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST;
548 blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP);
Dhaval Patel44f12472016-08-29 12:19:47 -0700549
Dhaval Patel48c76022016-09-01 17:51:23 -0700550 SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha);
551
552 switch (blend_type) {
553
554 case SDE_DRM_BLEND_OP_OPAQUE:
555 blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
556 SDE_BLEND_BG_ALPHA_BG_CONST;
557 break;
558
559 case SDE_DRM_BLEND_OP_PREMULTIPLIED:
560 if (format->alpha_enable) {
561 blend_op = SDE_BLEND_FG_ALPHA_FG_CONST |
562 SDE_BLEND_BG_ALPHA_FG_PIXEL;
563 if (fg_alpha != 0xff) {
564 bg_alpha = fg_alpha;
565 blend_op |= SDE_BLEND_BG_MOD_ALPHA |
566 SDE_BLEND_BG_INV_MOD_ALPHA;
567 } else {
568 blend_op |= SDE_BLEND_BG_INV_ALPHA;
569 }
570 }
571 break;
572
573 case SDE_DRM_BLEND_OP_COVERAGE:
574 if (format->alpha_enable) {
575 blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL |
576 SDE_BLEND_BG_ALPHA_FG_PIXEL;
577 if (fg_alpha != 0xff) {
578 bg_alpha = fg_alpha;
579 blend_op |= SDE_BLEND_FG_MOD_ALPHA |
580 SDE_BLEND_FG_INV_MOD_ALPHA |
581 SDE_BLEND_BG_MOD_ALPHA |
582 SDE_BLEND_BG_INV_MOD_ALPHA;
583 } else {
584 blend_op |= SDE_BLEND_BG_INV_ALPHA;
585 }
586 }
587 break;
588 default:
589 /* do nothing */
590 break;
Clarence Ipd9f9fa62016-09-09 13:42:32 -0400591 }
Dhaval Patel48c76022016-09-01 17:51:23 -0700592
593 lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha,
594 bg_alpha, blend_op);
Dhaval Patel6c666622017-03-21 23:02:59 -0700595 SDE_DEBUG(
596 "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n",
597 (char *) &format->base.pixel_format,
Dhaval Patel48c76022016-09-01 17:51:23 -0700598 format->alpha_enable, fg_alpha, bg_alpha, blend_op);
599}
600
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800601static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc,
602 struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer,
603 struct sde_hw_dim_layer *dim_layer)
604{
605 struct sde_hw_mixer *lm;
606 struct sde_rect mixer_rect;
607 struct sde_hw_dim_layer split_dim_layer;
608 u32 mixer_width, mixer_height;
609 int i;
610
611 if (!dim_layer->rect.w || !dim_layer->rect.h) {
612 SDE_DEBUG("empty dim layer\n");
613 return;
614 }
615
616 mixer_width = get_crtc_split_width(crtc);
617 mixer_height = get_crtc_mixer_height(crtc);
618 mixer_rect = (struct sde_rect) {0, 0, mixer_width, mixer_height};
619
620 split_dim_layer.stage = dim_layer->stage;
621 split_dim_layer.color_fill = dim_layer->color_fill;
622
623 /*
624 * traverse through the layer mixers attached to crtc and find the
625 * intersecting dim layer rect in each LM and program accordingly.
626 */
627 for (i = 0; i < sde_crtc->num_mixers; i++) {
628 split_dim_layer.flags = dim_layer->flags;
629 mixer_rect.x = i * mixer_width;
630
631 sde_kms_rect_intersect(&split_dim_layer.rect, &mixer_rect,
632 &dim_layer->rect);
633 if (!split_dim_layer.rect.w && !split_dim_layer.rect.h) {
634 /*
635 * no extra programming required for non-intersecting
636 * layer mixers with INCLUSIVE dim layer
637 */
638 if (split_dim_layer.flags
639 & SDE_DRM_DIM_LAYER_INCLUSIVE)
640 continue;
641
642 /*
643 * program the other non-intersecting layer mixers with
644 * INCLUSIVE dim layer of full size for uniformity
645 * with EXCLUSIVE dim layer config.
646 */
647 split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE;
648 split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE;
649 split_dim_layer.rect = (struct sde_rect) {0, 0,
650 mixer_width, mixer_height};
651
652 } else {
653 split_dim_layer.rect.x = split_dim_layer.rect.x
654 - (i * mixer_width);
655 }
656
657 lm = mixer[i].hw_lm;
658 mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage;
659 lm->ops.setup_dim_layer(lm, &split_dim_layer);
660 }
661}
662
Dhaval Patel48c76022016-09-01 17:51:23 -0700663static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc,
664 struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer)
665{
666 struct drm_plane *plane;
Dhaval Patel6c666622017-03-21 23:02:59 -0700667 struct drm_framebuffer *fb;
668 struct drm_plane_state *state;
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800669 struct sde_crtc_state *cstate;
Dhaval Patel48c76022016-09-01 17:51:23 -0700670 struct sde_plane_state *pstate = NULL;
671 struct sde_format *format;
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800672 struct sde_hw_ctl *ctl;
673 struct sde_hw_mixer *lm;
674 struct sde_hw_stage_cfg *stage_cfg;
Dhaval Patel48c76022016-09-01 17:51:23 -0700675
676 u32 flush_mask = 0, crtc_split_width;
677 uint32_t lm_idx = LEFT_MIXER, idx;
678 bool bg_alpha_enable[CRTC_DUAL_MIXERS] = {false};
679 bool lm_right = false;
680 int left_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0};
681 int right_crtc_zpos_cnt[SDE_STAGE_MAX + 1] = {0};
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800682 int i;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800683 bool sbuf_mode = false;
684 u32 prefill = 0;
Dhaval Patel48c76022016-09-01 17:51:23 -0700685
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800686 if (!sde_crtc || !mixer) {
687 SDE_ERROR("invalid sde_crtc or mixer\n");
688 return;
689 }
690
691 ctl = mixer->hw_ctl;
692 lm = mixer->hw_lm;
693 stage_cfg = &sde_crtc->stage_cfg;
Dhaval Patel48c76022016-09-01 17:51:23 -0700694 crtc_split_width = get_crtc_split_width(crtc);
Dhaval Patel44f12472016-08-29 12:19:47 -0700695
696 drm_atomic_crtc_for_each_plane(plane, crtc) {
Dhaval Patel6c666622017-03-21 23:02:59 -0700697 state = plane->state;
698 if (!state)
699 continue;
Dhaval Patel48c76022016-09-01 17:51:23 -0700700
Dhaval Patel6c666622017-03-21 23:02:59 -0700701 pstate = to_sde_plane_state(state);
702 fb = state->fb;
Dhaval Patel44f12472016-08-29 12:19:47 -0700703
Alan Kwong4dd64c82017-02-04 18:41:51 -0800704 if (sde_plane_is_sbuf_mode(plane, &prefill))
705 sbuf_mode = true;
706
707 sde_plane_get_ctl_flush(plane, ctl, &flush_mask);
Dhaval Patel44f12472016-08-29 12:19:47 -0700708
Dhaval Patel48c76022016-09-01 17:51:23 -0700709 /* always stage plane on either left or right lm */
Dhaval Patel6c666622017-03-21 23:02:59 -0700710 if (state->crtc_x >= crtc_split_width) {
Dhaval Patel48c76022016-09-01 17:51:23 -0700711 lm_idx = RIGHT_MIXER;
712 idx = right_crtc_zpos_cnt[pstate->stage]++;
713 } else {
714 lm_idx = LEFT_MIXER;
715 idx = left_crtc_zpos_cnt[pstate->stage]++;
716 }
717
718 /* stage plane on right LM if it crosses the boundary */
719 lm_right = (lm_idx == LEFT_MIXER) &&
Dhaval Patel6c666622017-03-21 23:02:59 -0700720 (state->crtc_x + state->crtc_w > crtc_split_width);
Dhaval Patel48c76022016-09-01 17:51:23 -0700721
722 stage_cfg->stage[lm_idx][pstate->stage][idx] =
723 sde_plane_pipe(plane);
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800724 stage_cfg->multirect_index
725 [lm_idx][pstate->stage][idx] =
726 pstate->multirect_index;
Dhaval Patel48c76022016-09-01 17:51:23 -0700727 mixer[lm_idx].flush_mask |= flush_mask;
728
729 SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
Clarence Ipd9f9fa62016-09-09 13:42:32 -0400730 crtc->base.id,
Clarence Ipd9f9fa62016-09-09 13:42:32 -0400731 pstate->stage,
732 plane->base.id,
733 sde_plane_pipe(plane) - SSPP_VIG0,
Dhaval Patel6c666622017-03-21 23:02:59 -0700734 state->fb ? state->fb->base.id : -1);
Dhaval Patel44f12472016-08-29 12:19:47 -0700735
Dhaval Patel48c76022016-09-01 17:51:23 -0700736 format = to_sde_format(msm_framebuffer_format(pstate->base.fb));
Dhaval Patel44f12472016-08-29 12:19:47 -0700737
Dhaval Patel6c666622017-03-21 23:02:59 -0700738 SDE_EVT32(DRMID(plane), state->src_x, state->src_y,
739 state->src_w >> 16, state->src_h >> 16, state->crtc_x,
740 state->crtc_y, state->crtc_w, state->crtc_h);
741 SDE_EVT32(DRMID(plane), DRMID(crtc), lm_idx, lm_right,
742 pstate->stage, pstate->multirect_index,
743 pstate->multirect_mode, format->base.pixel_format,
744 fb ? fb->modifier[0] : 0);
745
Dhaval Patel48c76022016-09-01 17:51:23 -0700746 /* blend config update */
747 if (pstate->stage != SDE_STAGE_BASE) {
748 _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate,
749 format);
750
751 if (bg_alpha_enable[lm_idx] && !format->alpha_enable)
752 mixer[lm_idx].mixer_op_mode = 0;
753 else
754 mixer[lm_idx].mixer_op_mode |=
755 1 << pstate->stage;
756 } else if (format->alpha_enable) {
757 bg_alpha_enable[lm_idx] = true;
758 }
759
760 if (lm_right) {
761 idx = right_crtc_zpos_cnt[pstate->stage]++;
762 stage_cfg->stage[RIGHT_MIXER][pstate->stage][idx] =
763 sde_plane_pipe(plane);
Jeykumar Sankaran2e655032017-02-04 14:05:45 -0800764 stage_cfg->multirect_index
765 [RIGHT_MIXER][pstate->stage][idx] =
766 pstate->multirect_index;
Dhaval Patel48c76022016-09-01 17:51:23 -0700767 mixer[RIGHT_MIXER].flush_mask |= flush_mask;
768
769 /* blend config update */
770 if (pstate->stage != SDE_STAGE_BASE) {
771 _sde_crtc_setup_blend_cfg(mixer + RIGHT_MIXER,
772 pstate, format);
773
774 if (bg_alpha_enable[RIGHT_MIXER] &&
775 !format->alpha_enable)
776 mixer[RIGHT_MIXER].mixer_op_mode = 0;
777 else
778 mixer[RIGHT_MIXER].mixer_op_mode |=
779 1 << pstate->stage;
780 } else if (format->alpha_enable) {
781 bg_alpha_enable[RIGHT_MIXER] = true;
782 }
783 }
Dhaval Patel44f12472016-08-29 12:19:47 -0700784 }
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800785
786 if (lm && lm->ops.setup_dim_layer) {
787 cstate = to_sde_crtc_state(crtc->state);
788 for (i = 0; i < cstate->num_dim_layers; i++)
789 _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc,
790 mixer, &cstate->dim_layer[i]);
791 }
Alan Kwong4dd64c82017-02-04 18:41:51 -0800792
793 if (ctl->ops.setup_sbuf_cfg) {
794 cstate = to_sde_crtc_state(crtc->state);
795 if (!sbuf_mode) {
796 cstate->sbuf_cfg.rot_op_mode =
797 SDE_CTL_ROT_OP_MODE_OFFLINE;
Alan Kwong4aacd532017-02-04 18:51:33 -0800798 cstate->sbuf_prefill_line = 0;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800799 } else {
800 cstate->sbuf_cfg.rot_op_mode =
801 SDE_CTL_ROT_OP_MODE_INLINE_SYNC;
Alan Kwong4aacd532017-02-04 18:51:33 -0800802 cstate->sbuf_prefill_line = prefill;
Alan Kwong4dd64c82017-02-04 18:41:51 -0800803 }
804
805 ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg);
806 }
Dhaval Patel44f12472016-08-29 12:19:47 -0700807}
808
Clarence Ipd9f9fa62016-09-09 13:42:32 -0400809/**
810 * _sde_crtc_blend_setup - configure crtc mixers
811 * @crtc: Pointer to drm crtc structure
812 */
813static void _sde_crtc_blend_setup(struct drm_crtc *crtc)
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400814{
815 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -0400816 struct sde_crtc_mixer *mixer = sde_crtc->mixers;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400817 struct sde_hw_ctl *ctl;
818 struct sde_hw_mixer *lm;
Dhaval Patel44f12472016-08-29 12:19:47 -0700819
820 int i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400821
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -0400822 SDE_DEBUG("%s\n", sde_crtc->name);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400823
Dhaval Patel48c76022016-09-01 17:51:23 -0700824 if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) {
825 SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers);
826 return;
827 }
828
829 for (i = 0; i < sde_crtc->num_mixers; i++) {
830 if (!mixer[i].hw_lm || !mixer[i].hw_ctl) {
831 SDE_ERROR("invalid lm or ctl assigned to mixer\n");
832 return;
833 }
834 mixer[i].mixer_op_mode = 0;
835 mixer[i].flush_mask = 0;
Lloyd Atkinsone5ec30d2016-08-23 14:32:32 -0400836 if (mixer[i].hw_ctl->ops.clear_all_blendstages)
837 mixer[i].hw_ctl->ops.clear_all_blendstages(
838 mixer[i].hw_ctl);
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -0800839
840 /* clear dim_layer settings */
841 lm = mixer[i].hw_lm;
842 if (lm->ops.clear_dim_layer)
843 lm->ops.clear_dim_layer(lm);
Dhaval Patel48c76022016-09-01 17:51:23 -0700844 }
845
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400846 /* initialize stage cfg */
Clarence Ip8f7366c2016-07-05 12:15:26 -0400847 memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg));
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400848
Dhaval Patel48c76022016-09-01 17:51:23 -0700849 _sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer);
850
Abhijit Kulkarni71002ba2016-06-24 18:36:28 -0400851 for (i = 0; i < sde_crtc->num_mixers; i++) {
Abhijit Kulkarni71002ba2016-06-24 18:36:28 -0400852 ctl = mixer[i].hw_ctl;
853 lm = mixer[i].hw_lm;
Abhijit Kulkarni71002ba2016-06-24 18:36:28 -0400854
Dhaval Patel48c76022016-09-01 17:51:23 -0700855 lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400856
Dhaval Patel48c76022016-09-01 17:51:23 -0700857 mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl,
Abhijit Kulkarni71002ba2016-06-24 18:36:28 -0400858 mixer[i].hw_lm->idx);
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -0400859
860 /* stage config flush mask */
Dhaval Patel48c76022016-09-01 17:51:23 -0700861 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
862
Clarence Ip8e69ad02016-12-09 09:43:57 -0500863 SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
864 mixer[i].hw_lm->idx - LM_0,
865 mixer[i].mixer_op_mode,
866 ctl->idx - CTL_0,
867 mixer[i].flush_mask);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400868
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400869 ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
Dhaval Patel44f12472016-08-29 12:19:47 -0700870 &sde_crtc->stage_cfg, i);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400871 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -0400872}
873
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400874void sde_crtc_prepare_commit(struct drm_crtc *crtc,
875 struct drm_crtc_state *old_state)
Clarence Ip24f80662016-06-13 19:05:32 -0400876{
877 struct sde_crtc *sde_crtc;
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400878 struct sde_crtc_state *cstate;
879 struct drm_connector *conn;
Clarence Ip24f80662016-06-13 19:05:32 -0400880
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400881 if (!crtc || !crtc->state) {
Clarence Ip24f80662016-06-13 19:05:32 -0400882 SDE_ERROR("invalid crtc\n");
883 return;
884 }
885
886 sde_crtc = to_sde_crtc(crtc);
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400887 cstate = to_sde_crtc_state(crtc->state);
Dhaval Patel6c666622017-03-21 23:02:59 -0700888 SDE_EVT32_VERBOSE(DRMID(crtc));
Clarence Ip24f80662016-06-13 19:05:32 -0400889
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400890 /* identify connectors attached to this crtc */
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400891 cstate->num_connectors = 0;
892
893 drm_for_each_connector(conn, crtc->dev)
894 if (conn->state && conn->state->crtc == crtc &&
895 cstate->num_connectors < MAX_CONNECTORS) {
896 cstate->connectors[cstate->num_connectors++] = conn;
897 sde_connector_prepare_fence(conn);
Clarence Ip0d0e96d2016-10-24 18:13:13 -0400898 }
899
900 /* prepare main output fence */
Clarence Ip24f80662016-06-13 19:05:32 -0400901 sde_fence_prepare(&sde_crtc->output_fence);
902}
903
Abhinav Kumarf2e94b52017-02-09 20:27:24 -0800904/**
905 * _sde_crtc_complete_flip - signal pending page_flip events
906 * Any pending vblank events are added to the vblank_event_list
907 * so that the next vblank interrupt shall signal them.
908 * However PAGE_FLIP events are not handled through the vblank_event_list.
909 * This API signals any pending PAGE_FLIP events requested through
910 * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event.
911 * if file!=NULL, this is preclose potential cancel-flip path
912 * @crtc: Pointer to drm crtc structure
913 * @file: Pointer to drm file
914 */
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -0400915static void _sde_crtc_complete_flip(struct drm_crtc *crtc,
916 struct drm_file *file)
Abhijit Kulkarni40e38162016-06-26 22:12:09 -0400917{
918 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
919 struct drm_device *dev = crtc->dev;
920 struct drm_pending_vblank_event *event;
921 unsigned long flags;
922
923 spin_lock_irqsave(&dev->event_lock, flags);
924 event = sde_crtc->event;
925 if (event) {
926 /* if regular vblank case (!file) or if cancel-flip from
927 * preclose on file that requested flip, then send the
928 * event:
929 */
930 if (!file || (event->base.file_priv == file)) {
931 sde_crtc->event = NULL;
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -0400932 DRM_DEBUG_VBL("%s: send event: %pK\n",
Dhaval Patelec10fad2016-08-22 14:40:48 -0700933 sde_crtc->name, event);
Lloyd Atkinson5d40d312016-09-06 08:34:13 -0400934 SDE_EVT32(DRMID(crtc));
Lloyd Atkinsonac933642016-09-14 11:52:00 -0400935 drm_crtc_send_vblank_event(crtc, event);
Abhijit Kulkarni40e38162016-06-26 22:12:09 -0400936 }
937 }
938 spin_unlock_irqrestore(&dev->event_lock, flags);
939}
940
Alan Kwong3e985f02017-02-12 15:08:44 -0800941enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc)
942{
943 struct drm_encoder *encoder;
944
945 if (!crtc || !crtc->dev) {
946 SDE_ERROR("invalid crtc\n");
947 return INTF_MODE_NONE;
948 }
949
950 drm_for_each_encoder(encoder, crtc->dev)
951 if (encoder->crtc == crtc)
952 return sde_encoder_get_intf_mode(encoder);
953
954 return INTF_MODE_NONE;
955}
956
Abhijit Kulkarni40e38162016-06-26 22:12:09 -0400957static void sde_crtc_vblank_cb(void *data)
958{
959 struct drm_crtc *crtc = (struct drm_crtc *)data;
Alan Kwong07da0982016-11-04 12:57:45 -0400960 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
961
962 /* keep statistics on vblank callback - with auto reset via debugfs */
963 if (ktime_equal(sde_crtc->vblank_cb_time, ktime_set(0, 0)))
964 sde_crtc->vblank_cb_time = ktime_get();
965 else
966 sde_crtc->vblank_cb_count++;
Abhinav Kumarf2e94b52017-02-09 20:27:24 -0800967 _sde_crtc_complete_flip(crtc, NULL);
Lloyd Atkinsonac933642016-09-14 11:52:00 -0400968 drm_crtc_handle_vblank(crtc);
Lloyd Atkinson9eabe7a2016-09-14 13:39:15 -0400969 DRM_DEBUG_VBL("crtc%d\n", crtc->base.id);
Dhaval Patel6c666622017-03-21 23:02:59 -0700970 SDE_EVT32_VERBOSE(DRMID(crtc));
Abhijit Kulkarni40e38162016-06-26 22:12:09 -0400971}
972
Alan Kwong628d19e2016-10-31 13:50:13 -0400973static void sde_crtc_frame_event_work(struct kthread_work *work)
974{
Alan Kwong67a3f792016-11-01 23:16:53 -0400975 struct msm_drm_private *priv;
Alan Kwong628d19e2016-10-31 13:50:13 -0400976 struct sde_crtc_frame_event *fevent;
977 struct drm_crtc *crtc;
978 struct sde_crtc *sde_crtc;
979 struct sde_kms *sde_kms;
980 unsigned long flags;
981
982 if (!work) {
983 SDE_ERROR("invalid work handle\n");
984 return;
985 }
986
987 fevent = container_of(work, struct sde_crtc_frame_event, work);
988 if (!fevent->crtc) {
989 SDE_ERROR("invalid crtc\n");
990 return;
991 }
992
993 crtc = fevent->crtc;
994 sde_crtc = to_sde_crtc(crtc);
995
996 sde_kms = _sde_crtc_get_kms(crtc);
997 if (!sde_kms) {
998 SDE_ERROR("invalid kms handle\n");
999 return;
1000 }
Alan Kwong67a3f792016-11-01 23:16:53 -04001001 priv = sde_kms->dev->dev_private;
Alan Kwong628d19e2016-10-31 13:50:13 -04001002
1003 SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
1004 ktime_to_ns(fevent->ts));
1005
1006 if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE ||
Lloyd Atkinson8c49c582016-11-18 14:23:54 -05001007 (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR) ||
1008 (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
Alan Kwong628d19e2016-10-31 13:50:13 -04001009
1010 if (atomic_read(&sde_crtc->frame_pending) < 1) {
1011 /* this should not happen */
1012 SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n",
1013 crtc->base.id,
1014 ktime_to_ns(fevent->ts),
1015 atomic_read(&sde_crtc->frame_pending));
Dhaval Patel6c666622017-03-21 23:02:59 -07001016 SDE_EVT32(DRMID(crtc), fevent->event,
1017 SDE_EVTLOG_FUNC_CASE1);
Clarence Ip9c65f7b2017-03-20 06:48:15 -07001018
1019 /* don't propagate unexpected frame done events */
1020 return;
Alan Kwong628d19e2016-10-31 13:50:13 -04001021 } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) {
1022 /* release bandwidth and other resources */
1023 SDE_DEBUG("crtc%d ts:%lld last pending\n",
1024 crtc->base.id,
1025 ktime_to_ns(fevent->ts));
Dhaval Patel6c666622017-03-21 23:02:59 -07001026 SDE_EVT32(DRMID(crtc), fevent->event,
1027 SDE_EVTLOG_FUNC_CASE2);
Alan Kwong9aa061c2016-11-06 21:17:12 -05001028 sde_core_perf_crtc_release_bw(crtc);
Alan Kwong628d19e2016-10-31 13:50:13 -04001029 } else {
Dhaval Patel6c666622017-03-21 23:02:59 -07001030 SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event,
1031 SDE_EVTLOG_FUNC_CASE3);
Alan Kwong628d19e2016-10-31 13:50:13 -04001032 }
1033 } else {
1034 SDE_ERROR("crtc%d ts:%lld unknown event %u\n", crtc->base.id,
1035 ktime_to_ns(fevent->ts),
1036 fevent->event);
Dhaval Patel6c666622017-03-21 23:02:59 -07001037 SDE_EVT32(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_CASE4);
Alan Kwong628d19e2016-10-31 13:50:13 -04001038 }
1039
Lloyd Atkinson8c49c582016-11-18 14:23:54 -05001040 if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)
1041 SDE_ERROR("crtc%d ts:%lld received panel dead event\n",
1042 crtc->base.id, ktime_to_ns(fevent->ts));
1043
Alan Kwong628d19e2016-10-31 13:50:13 -04001044 spin_lock_irqsave(&sde_crtc->spin_lock, flags);
1045 list_add_tail(&fevent->list, &sde_crtc->frame_event_list);
1046 spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
1047}
1048
1049static void sde_crtc_frame_event_cb(void *data, u32 event)
1050{
1051 struct drm_crtc *crtc = (struct drm_crtc *)data;
1052 struct sde_crtc *sde_crtc;
1053 struct msm_drm_private *priv;
Alan Kwong628d19e2016-10-31 13:50:13 -04001054 struct sde_crtc_frame_event *fevent;
1055 unsigned long flags;
1056 int pipe_id;
1057
1058 if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
1059 SDE_ERROR("invalid parameters\n");
1060 return;
1061 }
1062 sde_crtc = to_sde_crtc(crtc);
1063 priv = crtc->dev->dev_private;
1064 pipe_id = drm_crtc_index(crtc);
1065
1066 SDE_DEBUG("crtc%d\n", crtc->base.id);
Dhaval Patel6c666622017-03-21 23:02:59 -07001067 SDE_EVT32_VERBOSE(DRMID(crtc));
Alan Kwong628d19e2016-10-31 13:50:13 -04001068
1069 spin_lock_irqsave(&sde_crtc->spin_lock, flags);
Lloyd Atkinson78831f82016-12-09 11:24:56 -05001070 fevent = list_first_entry_or_null(&sde_crtc->frame_event_list,
1071 struct sde_crtc_frame_event, list);
1072 if (fevent)
1073 list_del_init(&fevent->list);
Alan Kwong628d19e2016-10-31 13:50:13 -04001074 spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
1075
Lloyd Atkinson78831f82016-12-09 11:24:56 -05001076 if (!fevent) {
Alan Kwong628d19e2016-10-31 13:50:13 -04001077 SDE_ERROR("crtc%d event %d overflow\n",
1078 crtc->base.id, event);
1079 SDE_EVT32(DRMID(crtc), event);
1080 return;
1081 }
1082
Alan Kwong628d19e2016-10-31 13:50:13 -04001083 fevent->event = event;
1084 fevent->crtc = crtc;
1085 fevent->ts = ktime_get();
1086 kthread_queue_work(&priv->disp_thread[pipe_id].worker, &fevent->work);
1087}
1088
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001089void sde_crtc_complete_commit(struct drm_crtc *crtc,
1090 struct drm_crtc_state *old_state)
Clarence Ip24f80662016-06-13 19:05:32 -04001091{
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001092 struct sde_crtc *sde_crtc;
1093 struct sde_crtc_state *cstate;
1094 int i;
1095
1096 if (!crtc || !crtc->state) {
Clarence Ip24f80662016-06-13 19:05:32 -04001097 SDE_ERROR("invalid crtc\n");
1098 return;
1099 }
1100
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001101 sde_crtc = to_sde_crtc(crtc);
1102 cstate = to_sde_crtc_state(crtc->state);
Dhaval Patel6c666622017-03-21 23:02:59 -07001103 SDE_EVT32_VERBOSE(DRMID(crtc));
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001104
1105 /* signal output fence(s) at end of commit */
1106 sde_fence_signal(&sde_crtc->output_fence, 0);
1107
1108 for (i = 0; i < cstate->num_connectors; ++i)
1109 sde_connector_complete_commit(cstate->connectors[i]);
Clarence Ip24f80662016-06-13 19:05:32 -04001110}
1111
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001112/**
Clarence Ipcae1bb62016-07-07 12:07:13 -04001113 * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout
1114 * @cstate: Pointer to sde crtc state
1115 */
1116static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate)
1117{
1118 if (!cstate) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001119 SDE_ERROR("invalid cstate\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001120 return;
1121 }
1122 cstate->input_fence_timeout_ns =
1123 sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT);
1124 cstate->input_fence_timeout_ns *= NSEC_PER_MSEC;
1125}
1126
1127/**
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08001128 * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace
1129 * @cstate: Pointer to sde crtc state
1130 * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct
1131 */
1132static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate,
1133 void *usr_ptr)
1134{
1135 struct sde_drm_dim_layer_v1 dim_layer_v1;
1136 struct sde_drm_dim_layer_cfg *user_cfg;
1137 u32 count, i;
1138
1139 if (!cstate) {
1140 SDE_ERROR("invalid cstate\n");
1141 return;
1142 }
1143
1144 if (!usr_ptr) {
1145 SDE_DEBUG("dim layer data removed\n");
1146 return;
1147 }
1148
1149 if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) {
1150 SDE_ERROR("failed to copy dim layer data\n");
1151 return;
1152 }
1153
1154 count = dim_layer_v1.num_layers;
1155 if (!count || (count > SDE_MAX_DIM_LAYERS)) {
1156 SDE_ERROR("invalid number of Dim Layers:%d", count);
1157 return;
1158 }
1159
1160 /* populate from user space */
1161 cstate->num_dim_layers = count;
1162 for (i = 0; i < count; i++) {
1163 user_cfg = &dim_layer_v1.layer_cfg[i];
1164 cstate->dim_layer[i].flags = user_cfg->flags;
1165 cstate->dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0;
1166
1167 cstate->dim_layer[i].rect.x = user_cfg->rect.x1;
1168 cstate->dim_layer[i].rect.y = user_cfg->rect.y1;
1169 cstate->dim_layer[i].rect.w = user_cfg->rect.x2 -
1170 user_cfg->rect.x1 + 1;
1171 cstate->dim_layer[i].rect.h = user_cfg->rect.y2 -
1172 user_cfg->rect.y1 + 1;
1173
1174 cstate->dim_layer[i].color_fill = (struct sde_mdss_color) {
1175 user_cfg->color_fill.color_0,
1176 user_cfg->color_fill.color_1,
1177 user_cfg->color_fill.color_2,
1178 user_cfg->color_fill.color_3,
1179 };
1180 }
1181}
1182
1183/**
Clarence Ipcae1bb62016-07-07 12:07:13 -04001184 * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences
1185 * @crtc: Pointer to CRTC object
1186 */
1187static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc)
1188{
1189 struct drm_plane *plane = NULL;
1190 uint32_t wait_ms = 1;
Clarence Ip8dedc232016-09-09 16:41:00 -04001191 ktime_t kt_end, kt_wait;
Dhaval Patel39323d42017-03-01 23:48:24 -08001192 int rc = 0;
Clarence Ipcae1bb62016-07-07 12:07:13 -04001193
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04001194 SDE_DEBUG("\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001195
1196 if (!crtc || !crtc->state) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001197 SDE_ERROR("invalid crtc/state %pK\n", crtc);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001198 return;
1199 }
1200
1201 /* use monotonic timer to limit total fence wait time */
Clarence Ip8dedc232016-09-09 16:41:00 -04001202 kt_end = ktime_add_ns(ktime_get(),
1203 to_sde_crtc_state(crtc->state)->input_fence_timeout_ns);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001204
1205 /*
1206 * Wait for fences sequentially, as all of them need to be signalled
1207 * before we can proceed.
1208 *
1209 * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call
1210 * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so
1211 * that each plane can check its fence status and react appropriately
Dhaval Patel39323d42017-03-01 23:48:24 -08001212 * if its fence has timed out. Call input fence wait multiple times if
1213 * fence wait is interrupted due to interrupt call.
Clarence Ipcae1bb62016-07-07 12:07:13 -04001214 */
1215 drm_atomic_crtc_for_each_plane(plane, crtc) {
Dhaval Patel39323d42017-03-01 23:48:24 -08001216 do {
Clarence Ip8dedc232016-09-09 16:41:00 -04001217 kt_wait = ktime_sub(kt_end, ktime_get());
1218 if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0)
1219 wait_ms = ktime_to_ms(kt_wait);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001220 else
1221 wait_ms = 0;
Dhaval Patel39323d42017-03-01 23:48:24 -08001222
1223 rc = sde_plane_wait_input_fence(plane, wait_ms);
1224 } while (wait_ms && rc == -ERESTARTSYS);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001225 }
1226}
1227
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001228static void _sde_crtc_setup_mixer_for_encoder(
1229 struct drm_crtc *crtc,
1230 struct drm_encoder *enc)
1231{
1232 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04001233 struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001234 struct sde_rm *rm = &sde_kms->rm;
1235 struct sde_crtc_mixer *mixer;
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001236 struct sde_hw_ctl *last_valid_ctl = NULL;
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001237 int i;
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07001238 struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter;
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001239
1240 sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM);
1241 sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL);
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07001242 sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001243
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001244 /* Set up all the mixers and ctls reserved by this encoder */
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001245 for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
1246 mixer = &sde_crtc->mixers[i];
1247
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001248 if (!sde_rm_get_hw(rm, &lm_iter))
1249 break;
1250 mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
1251
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001252 /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */
1253 if (!sde_rm_get_hw(rm, &ctl_iter)) {
1254 SDE_DEBUG("no ctl assigned to lm %d, using previous\n",
Clarence Ip8e69ad02016-12-09 09:43:57 -05001255 mixer->hw_lm->idx - LM_0);
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001256 mixer->hw_ctl = last_valid_ctl;
1257 } else {
1258 mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw;
1259 last_valid_ctl = mixer->hw_ctl;
1260 }
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001261
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001262 /* Shouldn't happen, mixers are always >= ctls */
1263 if (!mixer->hw_ctl) {
1264 SDE_ERROR("no valid ctls found for lm %d\n",
Clarence Ip8e69ad02016-12-09 09:43:57 -05001265 mixer->hw_lm->idx - LM_0);
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001266 return;
1267 }
1268
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07001269 /* Dspp may be null */
1270 (void) sde_rm_get_hw(rm, &dspp_iter);
1271 mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw;
1272
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001273 mixer->encoder = enc;
1274
1275 sde_crtc->num_mixers++;
Clarence Ipd9f9fa62016-09-09 13:42:32 -04001276 SDE_DEBUG("setup mixer %d: lm %d\n",
1277 i, mixer->hw_lm->idx - LM_0);
1278 SDE_DEBUG("setup mixer %d: ctl %d\n",
1279 i, mixer->hw_ctl->idx - CTL_0);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001280 }
1281}
1282
1283static void _sde_crtc_setup_mixers(struct drm_crtc *crtc)
1284{
1285 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
1286 struct drm_encoder *enc;
1287
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001288 sde_crtc->num_mixers = 0;
1289 memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
1290
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07001291 mutex_lock(&sde_crtc->crtc_lock);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001292 /* Check for mixers on all encoders attached to this crtc */
1293 list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1294 if (enc->crtc != crtc)
1295 continue;
1296
1297 _sde_crtc_setup_mixer_for_encoder(crtc, enc);
1298 }
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07001299 mutex_unlock(&sde_crtc->crtc_lock);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001300}
1301
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001302static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
Clarence Ip0d0e96d2016-10-24 18:13:13 -04001303 struct drm_crtc_state *old_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001304{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001305 struct sde_crtc *sde_crtc;
1306 struct drm_device *dev;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001307 unsigned long flags;
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001308 u32 i;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001309
Clarence Ipcae1bb62016-07-07 12:07:13 -04001310 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001311 SDE_ERROR("invalid crtc\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001312 return;
1313 }
1314
Alan Kwong163d2612016-11-03 00:56:56 -04001315 if (!crtc->state->enable) {
1316 SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
1317 crtc->base.id, crtc->state->enable);
1318 return;
1319 }
1320
1321 SDE_DEBUG("crtc%d\n", crtc->base.id);
1322
Clarence Ipcae1bb62016-07-07 12:07:13 -04001323 sde_crtc = to_sde_crtc(crtc);
1324 dev = crtc->dev;
1325
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001326 if (!sde_crtc->num_mixers)
1327 _sde_crtc_setup_mixers(crtc);
Lloyd Atkinson11f34442016-08-11 11:19:52 -04001328
Lloyd Atkinson265d2212016-05-30 13:12:01 -04001329 if (sde_crtc->event) {
1330 WARN_ON(sde_crtc->event);
1331 } else {
1332 spin_lock_irqsave(&dev->event_lock, flags);
1333 sde_crtc->event = crtc->state->event;
1334 spin_unlock_irqrestore(&dev->event_lock, flags);
1335 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001336
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001337 /* Reset flush mask from previous commit */
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001338 for (i = 0; i < ARRAY_SIZE(sde_crtc->mixers); i++) {
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001339 struct sde_hw_ctl *ctl = sde_crtc->mixers[i].hw_ctl;
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001340
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001341 if (ctl)
1342 ctl->ops.clear_pending_flush(ctl);
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001343 }
1344
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001345 /*
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001346 * If no mixers have been allocated in sde_crtc_atomic_check(),
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001347 * it means we are trying to flush a CRTC whose state is disabled:
1348 * nothing else needs to be done.
1349 */
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001350 if (unlikely(!sde_crtc->num_mixers))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001351 return;
1352
Clarence Ipd9f9fa62016-09-09 13:42:32 -04001353 _sde_crtc_blend_setup(crtc);
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07001354 sde_cp_crtc_apply_properties(crtc);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001355
1356 /*
1357 * PP_DONE irq is only used by command mode for now.
1358 * It is better to request pending before FLUSH and START trigger
1359 * to make sure no pp_done irq missed.
1360 * This is safe because no pp_done will happen before SW trigger
1361 * in command mode.
1362 */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001363}
1364
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001365static void sde_crtc_atomic_flush(struct drm_crtc *crtc,
1366 struct drm_crtc_state *old_crtc_state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001367{
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001368 struct drm_encoder *encoder;
Clarence Ipcae1bb62016-07-07 12:07:13 -04001369 struct sde_crtc *sde_crtc;
1370 struct drm_device *dev;
Lloyd Atkinson265d2212016-05-30 13:12:01 -04001371 struct drm_plane *plane;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001372 unsigned long flags;
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001373 struct sde_crtc_state *cstate;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001374
Clarence Ipcae1bb62016-07-07 12:07:13 -04001375 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001376 SDE_ERROR("invalid crtc\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001377 return;
1378 }
1379
Alan Kwong163d2612016-11-03 00:56:56 -04001380 if (!crtc->state->enable) {
1381 SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
1382 crtc->base.id, crtc->state->enable);
1383 return;
1384 }
1385
1386 SDE_DEBUG("crtc%d\n", crtc->base.id);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001387
1388 sde_crtc = to_sde_crtc(crtc);
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001389 cstate = to_sde_crtc_state(crtc->state);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001390 dev = crtc->dev;
1391
Lloyd Atkinson265d2212016-05-30 13:12:01 -04001392 if (sde_crtc->event) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001393 SDE_DEBUG("already received sde_crtc->event\n");
Lloyd Atkinson265d2212016-05-30 13:12:01 -04001394 } else {
Lloyd Atkinson265d2212016-05-30 13:12:01 -04001395 spin_lock_irqsave(&dev->event_lock, flags);
1396 sde_crtc->event = crtc->state->event;
1397 spin_unlock_irqrestore(&dev->event_lock, flags);
1398 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001399
1400 /*
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001401 * If no mixers has been allocated in sde_crtc_atomic_check(),
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001402 * it means we are trying to flush a CRTC whose state is disabled:
1403 * nothing else needs to be done.
1404 */
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001405 if (unlikely(!sde_crtc->num_mixers))
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001406 return;
1407
Clarence Ipcae1bb62016-07-07 12:07:13 -04001408 /* wait for acquire fences before anything else is done */
1409 _sde_crtc_wait_for_fences(crtc);
1410
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001411 if (!cstate->rsc_update) {
1412 drm_for_each_encoder(encoder, dev) {
1413 if (encoder->crtc != crtc)
1414 continue;
1415
1416 cstate->rsc_client =
1417 sde_encoder_update_rsc_client(encoder, true);
1418 }
1419 cstate->rsc_update = true;
1420 }
1421
Alan Kwong9aa061c2016-11-06 21:17:12 -05001422 /* update performance setting before crtc kickoff */
1423 sde_core_perf_crtc_update(crtc, 1, false);
1424
Clarence Ipcae1bb62016-07-07 12:07:13 -04001425 /*
1426 * Final plane updates: Give each plane a chance to complete all
1427 * required writes/flushing before crtc's "flush
1428 * everything" call below.
1429 */
1430 drm_atomic_crtc_for_each_plane(plane, crtc)
1431 sde_plane_flush(plane);
1432
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001433 /* Kickoff will be scheduled by outer layer */
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001434}
1435
Clarence Ip7a753bb2016-07-07 11:47:44 -04001436/**
1437 * sde_crtc_destroy_state - state destroy hook
1438 * @crtc: drm CRTC
1439 * @state: CRTC state object to release
1440 */
1441static void sde_crtc_destroy_state(struct drm_crtc *crtc,
1442 struct drm_crtc_state *state)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001443{
Clarence Ip7a753bb2016-07-07 11:47:44 -04001444 struct sde_crtc *sde_crtc;
1445 struct sde_crtc_state *cstate;
1446
1447 if (!crtc || !state) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001448 SDE_ERROR("invalid argument(s)\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04001449 return;
1450 }
1451
1452 sde_crtc = to_sde_crtc(crtc);
1453 cstate = to_sde_crtc_state(state);
1454
Alan Kwong163d2612016-11-03 00:56:56 -04001455 SDE_DEBUG("crtc%d\n", crtc->base.id);
Clarence Ip7a753bb2016-07-07 11:47:44 -04001456
Alan Kwongcdb2f282017-03-18 13:42:06 -07001457 _sde_crtc_rp_destroy(&cstate->rp);
1458
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001459 __drm_atomic_helper_crtc_destroy_state(state);
Clarence Ip7a753bb2016-07-07 11:47:44 -04001460
1461 /* destroy value helper */
1462 msm_property_destroy_state(&sde_crtc->property_info, cstate,
1463 cstate->property_values, cstate->property_blobs);
1464}
1465
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001466void sde_crtc_commit_kickoff(struct drm_crtc *crtc)
1467{
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001468 struct drm_encoder *encoder;
1469 struct drm_device *dev;
Alan Kwong628d19e2016-10-31 13:50:13 -04001470 struct sde_crtc *sde_crtc;
Alan Kwong67a3f792016-11-01 23:16:53 -04001471 struct msm_drm_private *priv;
1472 struct sde_kms *sde_kms;
Alan Kwong4aacd532017-02-04 18:51:33 -08001473 struct sde_crtc_state *cstate;
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001474
1475 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001476 SDE_ERROR("invalid argument\n");
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001477 return;
1478 }
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001479 dev = crtc->dev;
Alan Kwong628d19e2016-10-31 13:50:13 -04001480 sde_crtc = to_sde_crtc(crtc);
Alan Kwong67a3f792016-11-01 23:16:53 -04001481 sde_kms = _sde_crtc_get_kms(crtc);
1482 priv = sde_kms->dev->dev_private;
Alan Kwong4aacd532017-02-04 18:51:33 -08001483 cstate = to_sde_crtc_state(crtc->state);
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001484
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001485 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
Alan Kwong4aacd532017-02-04 18:51:33 -08001486 struct sde_encoder_kickoff_params params = { 0 };
1487
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001488 if (encoder->crtc != crtc)
1489 continue;
1490
1491 /*
1492 * Encoder will flush/start now, unless it has a tx pending.
1493 * If so, it may delay and flush at an irq event (e.g. ppdone)
1494 */
Alan Kwong4aacd532017-02-04 18:51:33 -08001495 params.inline_rotate_prefill = cstate->sbuf_prefill_line;
1496 sde_encoder_prepare_for_kickoff(encoder, &params);
Alan Kwong628d19e2016-10-31 13:50:13 -04001497 }
1498
1499 if (atomic_read(&sde_crtc->frame_pending) > 2) {
1500 /* framework allows only 1 outstanding + current */
1501 SDE_ERROR("crtc%d invalid frame pending\n",
1502 crtc->base.id);
1503 SDE_EVT32(DRMID(crtc), 0);
1504 return;
1505 } else if (atomic_inc_return(&sde_crtc->frame_pending) == 1) {
1506 /* acquire bandwidth and other resources */
1507 SDE_DEBUG("crtc%d first commit\n", crtc->base.id);
1508 SDE_EVT32(DRMID(crtc), 1);
1509 } else {
1510 SDE_DEBUG("crtc%d commit\n", crtc->base.id);
1511 SDE_EVT32(DRMID(crtc), 2);
1512 }
1513
1514 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1515 if (encoder->crtc != crtc)
1516 continue;
1517
1518 sde_encoder_kickoff(encoder);
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001519 }
Lloyd Atkinson5d722782016-05-30 14:09:41 -04001520}
1521
Clarence Ip7a753bb2016-07-07 11:47:44 -04001522/**
Clarence Ip7f70ce42017-03-20 06:53:46 -07001523 * _sde_crtc_vblank_enable_nolock - update power resource and vblank request
1524 * @sde_crtc: Pointer to sde crtc structure
1525 * @enable: Whether to enable/disable vblanks
1526 */
1527static void _sde_crtc_vblank_enable_nolock(
1528 struct sde_crtc *sde_crtc, bool enable)
1529{
1530 struct drm_device *dev;
1531 struct drm_crtc *crtc;
1532 struct drm_encoder *enc;
Clarence Ip7f70ce42017-03-20 06:53:46 -07001533
1534 if (!sde_crtc) {
1535 SDE_ERROR("invalid crtc\n");
1536 return;
1537 }
1538
1539 crtc = &sde_crtc->base;
1540 dev = crtc->dev;
Clarence Ip7f70ce42017-03-20 06:53:46 -07001541
1542 if (enable) {
Dhaval Patelf9245d62017-03-28 16:24:00 -07001543 if (_sde_crtc_power_enable(sde_crtc, true))
1544 return;
1545
Clarence Ip7f70ce42017-03-20 06:53:46 -07001546 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
1547 if (enc->crtc != crtc)
1548 continue;
1549
1550 SDE_EVT32(DRMID(crtc), DRMID(enc), enable);
1551
1552 sde_encoder_register_vblank_callback(enc,
1553 sde_crtc_vblank_cb, (void *)crtc);
1554 }
1555 } else {
1556 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
1557 if (enc->crtc != crtc)
1558 continue;
1559
1560 SDE_EVT32(DRMID(crtc), DRMID(enc), enable);
1561
1562 sde_encoder_register_vblank_callback(enc, NULL, NULL);
1563 }
Dhaval Patelf9245d62017-03-28 16:24:00 -07001564 _sde_crtc_power_enable(sde_crtc, false);
Clarence Ip7f70ce42017-03-20 06:53:46 -07001565 }
1566}
1567
1568/**
1569 * _sde_crtc_set_suspend - notify crtc of suspend enable/disable
1570 * @crtc: Pointer to drm crtc object
1571 * @enable: true to enable suspend, false to indicate resume
1572 */
1573static void _sde_crtc_set_suspend(struct drm_crtc *crtc, bool enable)
1574{
1575 struct sde_crtc *sde_crtc;
1576 struct msm_drm_private *priv;
1577 struct sde_kms *sde_kms;
1578
1579 if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
1580 SDE_ERROR("invalid crtc\n");
1581 return;
1582 }
1583 sde_crtc = to_sde_crtc(crtc);
1584 priv = crtc->dev->dev_private;
1585
1586 if (!priv->kms) {
1587 SDE_ERROR("invalid crtc kms\n");
1588 return;
1589 }
1590 sde_kms = to_sde_kms(priv->kms);
1591
1592 SDE_DEBUG("crtc%d suspend = %d\n", crtc->base.id, enable);
1593
1594 mutex_lock(&sde_crtc->crtc_lock);
1595
1596 /*
Clarence Ip2f9beeb2017-03-16 11:04:53 -04001597 * Update CP on suspend/resume transitions
1598 */
1599 if (enable && !sde_crtc->suspend)
1600 sde_cp_crtc_suspend(crtc);
1601 else if (!enable && sde_crtc->suspend)
1602 sde_cp_crtc_resume(crtc);
1603
1604 /*
Clarence Ip7f70ce42017-03-20 06:53:46 -07001605 * If the vblank refcount != 0, release a power reference on suspend
1606 * and take it back during resume (if it is still != 0).
1607 */
1608 if (sde_crtc->suspend == enable)
1609 SDE_DEBUG("crtc%d suspend already set to %d, ignoring update\n",
1610 crtc->base.id, enable);
1611 else if (atomic_read(&sde_crtc->vblank_refcount) != 0)
1612 _sde_crtc_vblank_enable_nolock(sde_crtc, !enable);
1613
1614 sde_crtc->suspend = enable;
1615
1616 mutex_unlock(&sde_crtc->crtc_lock);
1617}
1618
1619/**
Clarence Ip7a753bb2016-07-07 11:47:44 -04001620 * sde_crtc_duplicate_state - state duplicate hook
1621 * @crtc: Pointer to drm crtc structure
1622 * @Returns: Pointer to new drm_crtc_state structure
1623 */
1624static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc)
1625{
1626 struct sde_crtc *sde_crtc;
1627 struct sde_crtc_state *cstate, *old_cstate;
1628
1629 if (!crtc || !crtc->state) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001630 SDE_ERROR("invalid argument(s)\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04001631 return NULL;
1632 }
1633
1634 sde_crtc = to_sde_crtc(crtc);
1635 old_cstate = to_sde_crtc_state(crtc->state);
1636 cstate = msm_property_alloc_state(&sde_crtc->property_info);
1637 if (!cstate) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001638 SDE_ERROR("failed to allocate state\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04001639 return NULL;
1640 }
1641
1642 /* duplicate value helper */
1643 msm_property_duplicate_state(&sde_crtc->property_info,
1644 old_cstate, cstate,
1645 cstate->property_values, cstate->property_blobs);
1646
1647 /* duplicate base helper */
1648 __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
1649
Alan Kwongcdb2f282017-03-18 13:42:06 -07001650 _sde_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp);
1651
Clarence Ip7a753bb2016-07-07 11:47:44 -04001652 return &cstate->base;
1653}
1654
1655/**
1656 * sde_crtc_reset - reset hook for CRTCs
1657 * Resets the atomic state for @crtc by freeing the state pointer (which might
1658 * be NULL, e.g. at driver load time) and allocating a new empty state object.
1659 * @crtc: Pointer to drm crtc structure
1660 */
1661static void sde_crtc_reset(struct drm_crtc *crtc)
1662{
1663 struct sde_crtc *sde_crtc;
1664 struct sde_crtc_state *cstate;
1665
1666 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001667 SDE_ERROR("invalid crtc\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04001668 return;
1669 }
1670
Clarence Ip7f70ce42017-03-20 06:53:46 -07001671 /* revert suspend actions, if necessary */
1672 if (msm_is_suspend_state(crtc->dev))
1673 _sde_crtc_set_suspend(crtc, false);
1674
Clarence Ip7a753bb2016-07-07 11:47:44 -04001675 /* remove previous state, if present */
1676 if (crtc->state) {
1677 sde_crtc_destroy_state(crtc, crtc->state);
1678 crtc->state = 0;
1679 }
1680
1681 sde_crtc = to_sde_crtc(crtc);
1682 cstate = msm_property_alloc_state(&sde_crtc->property_info);
1683 if (!cstate) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001684 SDE_ERROR("failed to allocate state\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04001685 return;
1686 }
1687
1688 /* reset value helper */
1689 msm_property_reset_state(&sde_crtc->property_info, cstate,
1690 cstate->property_values, cstate->property_blobs);
1691
Clarence Ipcae1bb62016-07-07 12:07:13 -04001692 _sde_crtc_set_input_fence_timeout(cstate);
1693
Alan Kwongcdb2f282017-03-18 13:42:06 -07001694 _sde_crtc_rp_reset(&cstate->rp);
1695
Clarence Ip7a753bb2016-07-07 11:47:44 -04001696 cstate->base.crtc = crtc;
1697 crtc->state = &cstate->base;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07001698}
1699
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001700static void sde_crtc_disable(struct drm_crtc *crtc)
1701{
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001702 struct sde_crtc *sde_crtc;
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001703 struct sde_crtc_state *cstate;
Alan Kwong07da0982016-11-04 12:57:45 -04001704 struct drm_encoder *encoder;
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07001705 unsigned long flags;
1706 struct sde_crtc_irq_info *node = NULL;
1707 int ret;
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001708
Clarence Ip7f70ce42017-03-20 06:53:46 -07001709 if (!crtc || !crtc->dev || !crtc->state) {
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04001710 SDE_ERROR("invalid crtc\n");
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001711 return;
1712 }
1713 sde_crtc = to_sde_crtc(crtc);
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001714 cstate = to_sde_crtc_state(crtc->state);
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001715
Alan Kwong163d2612016-11-03 00:56:56 -04001716 SDE_DEBUG("crtc%d\n", crtc->base.id);
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001717
Clarence Ip7f70ce42017-03-20 06:53:46 -07001718 if (msm_is_suspend_state(crtc->dev))
1719 _sde_crtc_set_suspend(crtc, true);
1720
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07001721 mutex_lock(&sde_crtc->crtc_lock);
Alan Kwong628d19e2016-10-31 13:50:13 -04001722 SDE_EVT32(DRMID(crtc));
1723
Clarence Ip7f70ce42017-03-20 06:53:46 -07001724 if (atomic_read(&sde_crtc->vblank_refcount) && !sde_crtc->suspend) {
Alan Kwong628d19e2016-10-31 13:50:13 -04001725 SDE_ERROR("crtc%d invalid vblank refcount\n",
1726 crtc->base.id);
Dhaval Patel6c666622017-03-21 23:02:59 -07001727 SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->vblank_refcount),
1728 SDE_EVTLOG_FUNC_CASE1);
Alan Kwong07da0982016-11-04 12:57:45 -04001729 drm_for_each_encoder(encoder, crtc->dev) {
1730 if (encoder->crtc != crtc)
1731 continue;
1732 sde_encoder_register_vblank_callback(encoder, NULL,
1733 NULL);
1734 }
1735 atomic_set(&sde_crtc->vblank_refcount, 0);
1736 }
1737
Alan Kwong628d19e2016-10-31 13:50:13 -04001738 if (atomic_read(&sde_crtc->frame_pending)) {
1739 /* release bandwidth and other resources */
1740 SDE_ERROR("crtc%d invalid frame pending\n",
1741 crtc->base.id);
Dhaval Patel6c666622017-03-21 23:02:59 -07001742 SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending),
1743 SDE_EVTLOG_FUNC_CASE2);
Alan Kwong9aa061c2016-11-06 21:17:12 -05001744 sde_core_perf_crtc_release_bw(crtc);
Alan Kwong628d19e2016-10-31 13:50:13 -04001745 atomic_set(&sde_crtc->frame_pending, 0);
1746 }
1747
Alan Kwong9aa061c2016-11-06 21:17:12 -05001748 sde_core_perf_crtc_update(crtc, 0, true);
1749
Alan Kwong628d19e2016-10-31 13:50:13 -04001750 drm_for_each_encoder(encoder, crtc->dev) {
1751 if (encoder->crtc != crtc)
1752 continue;
1753 sde_encoder_register_frame_event_callback(encoder, NULL, NULL);
Dhaval Patel82c8dbc2017-02-18 23:15:10 -08001754 sde_encoder_update_rsc_client(encoder, false);
1755 cstate->rsc_client = NULL;
1756 cstate->rsc_update = false;
Alan Kwong628d19e2016-10-31 13:50:13 -04001757 }
1758
Lloyd Atkinsonc44a52e2016-08-16 16:40:17 -04001759 memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers));
1760 sde_crtc->num_mixers = 0;
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07001761
1762 spin_lock_irqsave(&sde_crtc->spin_lock, flags);
1763 list_for_each_entry(node, &sde_crtc->user_event_list, list) {
1764 ret = 0;
1765 if (node->func)
1766 ret = node->func(crtc, false, &node->irq);
1767 if (ret)
1768 SDE_ERROR("%s failed to disable event %x\n",
1769 sde_crtc->name, node->event);
1770 }
1771 spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
1772
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07001773 mutex_unlock(&sde_crtc->crtc_lock);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001774}
1775
1776static void sde_crtc_enable(struct drm_crtc *crtc)
1777{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001778 struct sde_crtc *sde_crtc;
1779 struct sde_crtc_mixer *mixer;
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001780 struct sde_hw_mixer *lm;
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001781 struct drm_display_mode *mode;
Alan Kwong628d19e2016-10-31 13:50:13 -04001782 struct drm_encoder *encoder;
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07001783 unsigned long flags;
1784 struct sde_crtc_irq_info *node = NULL;
1785 int i, ret;
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001786
Clarence Ipcae1bb62016-07-07 12:07:13 -04001787 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001788 SDE_ERROR("invalid crtc\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001789 return;
1790 }
1791
Alan Kwong163d2612016-11-03 00:56:56 -04001792 SDE_DEBUG("crtc%d\n", crtc->base.id);
Alan Kwong628d19e2016-10-31 13:50:13 -04001793 SDE_EVT32(DRMID(crtc));
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001794
Clarence Ipcae1bb62016-07-07 12:07:13 -04001795 sde_crtc = to_sde_crtc(crtc);
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04001796 mixer = sde_crtc->mixers;
Clarence Ipcae1bb62016-07-07 12:07:13 -04001797
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001798 if (WARN_ON(!crtc->state))
1799 return;
1800
1801 mode = &crtc->state->adjusted_mode;
1802
1803 drm_mode_debug_printmodeline(mode);
1804
Alan Kwong628d19e2016-10-31 13:50:13 -04001805 drm_for_each_encoder(encoder, crtc->dev) {
1806 if (encoder->crtc != crtc)
1807 continue;
1808 sde_encoder_register_frame_event_callback(encoder,
1809 sde_crtc_frame_event_cb, (void *)crtc);
1810 }
1811
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001812 for (i = 0; i < sde_crtc->num_mixers; i++) {
1813 lm = mixer[i].hw_lm;
Gopikrishnaiah Anandan9ba43782017-01-31 18:23:08 -08001814 lm->cfg.out_width = sde_crtc_mixer_width(sde_crtc, mode);
1815 lm->cfg.out_height = mode->vdisplay;
1816 lm->cfg.right_mixer = (i == 0) ? false : true;
1817 lm->cfg.flags = 0;
1818 lm->ops.setup_mixer_out(lm, &lm->cfg);
Lloyd Atkinsonaf7952d2016-06-26 22:41:26 -04001819 }
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07001820
1821 spin_lock_irqsave(&sde_crtc->spin_lock, flags);
1822 list_for_each_entry(node, &sde_crtc->user_event_list, list) {
1823 ret = 0;
1824 if (node->func)
1825 ret = node->func(crtc, true, &node->irq);
1826 if (ret)
1827 SDE_ERROR("%s failed to enable event %x\n",
1828 sde_crtc->name, node->event);
1829 }
1830 spin_unlock_irqrestore(&sde_crtc->spin_lock, flags);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001831}
1832
1833struct plane_state {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001834 struct sde_plane_state *sde_pstate;
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001835 const struct drm_plane_state *drm_pstate;
Clarence Ipc47a0692016-10-11 10:54:17 -04001836 int stage;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001837 u32 pipe_id;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001838};
1839
Clarence Ipc47a0692016-10-11 10:54:17 -04001840static int pstate_cmp(const void *a, const void *b)
1841{
1842 struct plane_state *pa = (struct plane_state *)a;
1843 struct plane_state *pb = (struct plane_state *)b;
1844 int rc = 0;
1845 int pa_zpos, pb_zpos;
1846
1847 pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS);
1848 pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS);
1849
1850 if (pa_zpos != pb_zpos)
1851 rc = pa_zpos - pb_zpos;
1852 else
1853 rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x;
1854
1855 return rc;
1856}
1857
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001858static int sde_crtc_atomic_check(struct drm_crtc *crtc,
1859 struct drm_crtc_state *state)
1860{
Clarence Ipcae1bb62016-07-07 12:07:13 -04001861 struct sde_crtc *sde_crtc;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001862 struct plane_state pstates[SDE_STAGE_MAX * 4];
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08001863 struct sde_crtc_state *cstate;
Dhaval Patelec10fad2016-08-22 14:40:48 -07001864
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001865 const struct drm_plane_state *pstate;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001866 struct drm_plane *plane;
Dhaval Patelec10fad2016-08-22 14:40:48 -07001867 struct drm_display_mode *mode;
1868
1869 int cnt = 0, rc = 0, mixer_width, i, z_pos;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001870
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001871 struct sde_multirect_plane_states multirect_plane[SDE_STAGE_MAX * 2];
1872 int multirect_count = 0;
1873 const struct drm_plane_state *pipe_staged[SSPP_MAX];
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04001874 int left_zpos_cnt = 0, right_zpos_cnt = 0;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001875
Clarence Ipcae1bb62016-07-07 12:07:13 -04001876 if (!crtc) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07001877 SDE_ERROR("invalid crtc\n");
Clarence Ipcae1bb62016-07-07 12:07:13 -04001878 return -EINVAL;
1879 }
1880
Alan Kwongcdb2f282017-03-18 13:42:06 -07001881 sde_crtc = to_sde_crtc(crtc);
1882 cstate = to_sde_crtc_state(state);
1883
Lloyd Atkinson5217336c2016-09-15 18:21:18 -04001884 if (!state->enable || !state->active) {
1885 SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
1886 crtc->base.id, state->enable, state->active);
Alan Kwongcdb2f282017-03-18 13:42:06 -07001887 goto end;
Lloyd Atkinson5217336c2016-09-15 18:21:18 -04001888 }
1889
Dhaval Patelec10fad2016-08-22 14:40:48 -07001890 mode = &state->adjusted_mode;
1891 SDE_DEBUG("%s: check", sde_crtc->name);
Clarence Ipcae1bb62016-07-07 12:07:13 -04001892
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001893 memset(pipe_staged, 0, sizeof(pipe_staged));
1894
Dhaval Patelec10fad2016-08-22 14:40:48 -07001895 mixer_width = sde_crtc_mixer_width(sde_crtc, mode);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001896
Dhaval Patelec10fad2016-08-22 14:40:48 -07001897 /* get plane state for all drm planes associated with crtc state */
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07001898 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
Clarence Ipc47a0692016-10-11 10:54:17 -04001899 if (IS_ERR_OR_NULL(pstate)) {
1900 rc = PTR_ERR(pstate);
1901 SDE_ERROR("%s: failed to get plane%d state, %d\n",
1902 sde_crtc->name, plane->base.id, rc);
Alan Kwong85767282016-10-03 18:03:37 -04001903 goto end;
1904 }
Clarence Ipc47a0692016-10-11 10:54:17 -04001905 if (cnt >= ARRAY_SIZE(pstates))
1906 continue;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001907
Dhaval Patelec10fad2016-08-22 14:40:48 -07001908 pstates[cnt].sde_pstate = to_sde_plane_state(pstate);
1909 pstates[cnt].drm_pstate = pstate;
Clarence Ipc47a0692016-10-11 10:54:17 -04001910 pstates[cnt].stage = sde_plane_get_property(
1911 pstates[cnt].sde_pstate, PLANE_PROP_ZPOS);
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001912 pstates[cnt].pipe_id = sde_plane_pipe(plane);
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08001913
1914 /* check dim layer stage with every plane */
1915 for (i = 0; i < cstate->num_dim_layers; i++) {
1916 if (pstates[cnt].stage == cstate->dim_layer[i].stage) {
1917 SDE_ERROR("plane%d/dimlayer in same stage:%d\n",
1918 plane->base.id,
1919 cstate->dim_layer[i].stage);
1920 rc = -EINVAL;
1921 goto end;
1922 }
1923 }
1924
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001925 if (pipe_staged[pstates[cnt].pipe_id]) {
1926 multirect_plane[multirect_count].r0 =
1927 pipe_staged[pstates[cnt].pipe_id];
1928 multirect_plane[multirect_count].r1 = pstate;
1929 multirect_count++;
1930
1931 pipe_staged[pstates[cnt].pipe_id] = NULL;
1932 } else {
1933 pipe_staged[pstates[cnt].pipe_id] = pstate;
1934 }
1935
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001936 cnt++;
Dhaval Patelec10fad2016-08-22 14:40:48 -07001937
1938 if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h,
1939 mode->vdisplay) ||
1940 CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w,
1941 mode->hdisplay)) {
1942 SDE_ERROR("invalid vertical/horizontal destination\n");
1943 SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n",
1944 pstate->crtc_y, pstate->crtc_h, mode->vdisplay,
1945 pstate->crtc_x, pstate->crtc_w, mode->hdisplay);
1946 rc = -E2BIG;
1947 goto end;
1948 }
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04001949 }
1950
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08001951 for (i = 1; i < SSPP_MAX; i++) {
1952 if (pipe_staged[i] &&
1953 is_sde_plane_virtual(pipe_staged[i]->plane)) {
1954 SDE_ERROR("invalid use of virtual plane: %d\n",
1955 pipe_staged[i]->plane->base.id);
1956 goto end;
1957 }
1958 }
1959
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08001960 /* Check dim layer rect bounds and stage */
1961 for (i = 0; i < cstate->num_dim_layers; i++) {
1962 if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y,
1963 cstate->dim_layer[i].rect.h, mode->vdisplay)) ||
1964 (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x,
1965 cstate->dim_layer[i].rect.w, mode->hdisplay)) ||
1966 (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) ||
1967 (!cstate->dim_layer[i].rect.w) ||
1968 (!cstate->dim_layer[i].rect.h)) {
1969 SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n",
1970 cstate->dim_layer[i].rect.x,
1971 cstate->dim_layer[i].rect.y,
1972 cstate->dim_layer[i].rect.w,
1973 cstate->dim_layer[i].rect.h,
1974 cstate->dim_layer[i].stage);
1975 SDE_ERROR("display: %dx%d\n", mode->hdisplay,
1976 mode->vdisplay);
1977 rc = -E2BIG;
1978 goto end;
1979 }
1980 }
1981
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04001982 /* assign mixer stages based on sorted zpos property */
1983 sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);
1984
Clarence Ipc47a0692016-10-11 10:54:17 -04001985 if (!sde_is_custom_client()) {
1986 int stage_old = pstates[0].stage;
Dhaval Patelec10fad2016-08-22 14:40:48 -07001987
Clarence Ipc47a0692016-10-11 10:54:17 -04001988 z_pos = 0;
1989 for (i = 0; i < cnt; i++) {
1990 if (stage_old != pstates[i].stage)
1991 ++z_pos;
1992 stage_old = pstates[i].stage;
1993 pstates[i].stage = z_pos;
1994 }
1995 }
1996
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04001997 z_pos = -1;
Clarence Ipc47a0692016-10-11 10:54:17 -04001998 for (i = 0; i < cnt; i++) {
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04001999 /* reset counts at every new blend stage */
2000 if (pstates[i].stage != z_pos) {
2001 left_zpos_cnt = 0;
2002 right_zpos_cnt = 0;
2003 z_pos = pstates[i].stage;
2004 }
Clarence Ipc47a0692016-10-11 10:54:17 -04002005
2006 /* verify z_pos setting before using it */
Clarence Ip649989a2016-10-21 14:28:34 -04002007 if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) {
Clarence Ipc47a0692016-10-11 10:54:17 -04002008 SDE_ERROR("> %d plane stages assigned\n",
2009 SDE_STAGE_MAX - SDE_STAGE_0);
2010 rc = -EINVAL;
2011 goto end;
2012 } else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002013 if (left_zpos_cnt == 2) {
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002014 SDE_ERROR("> 2 planes @ stage %d on left\n",
Dhaval Patelec10fad2016-08-22 14:40:48 -07002015 z_pos);
2016 rc = -EINVAL;
2017 goto end;
2018 }
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002019 left_zpos_cnt++;
2020
Dhaval Patelec10fad2016-08-22 14:40:48 -07002021 } else {
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002022 if (right_zpos_cnt == 2) {
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002023 SDE_ERROR("> 2 planes @ stage %d on right\n",
Dhaval Patelec10fad2016-08-22 14:40:48 -07002024 z_pos);
2025 rc = -EINVAL;
2026 goto end;
2027 }
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002028 right_zpos_cnt++;
Dhaval Patelec10fad2016-08-22 14:40:48 -07002029 }
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002030
Clarence Ipc47a0692016-10-11 10:54:17 -04002031 pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0;
Dhaval Patelec10fad2016-08-22 14:40:48 -07002032 SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002033 }
2034
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002035 for (i = 0; i < multirect_count; i++) {
2036 if (sde_plane_validate_multirect_v2(&multirect_plane[i])) {
2037 SDE_ERROR(
2038 "multirect validation failed for planes (%d - %d)\n",
2039 multirect_plane[i].r0->plane->base.id,
2040 multirect_plane[i].r1->plane->base.id);
2041 rc = -EINVAL;
Alan Kwong9aa061c2016-11-06 21:17:12 -05002042 goto end;
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002043 }
2044 }
2045
Alan Kwong9aa061c2016-11-06 21:17:12 -05002046 rc = sde_core_perf_crtc_check(crtc, state);
2047 if (rc) {
2048 SDE_ERROR("crtc%d failed performance check %d\n",
2049 crtc->base.id, rc);
2050 goto end;
2051 }
2052
Lloyd Atkinson629ce1f2016-10-27 16:50:26 -04002053 /*
2054 * enforce pipe priority restrictions
2055 * use pstates sorted by stage to check planes on same stage
2056 * we assume that all pipes are in source split so its valid to compare
2057 * without taking into account left/right mixer placement
2058 */
2059 for (i = 1; i < cnt; i++) {
2060 struct plane_state *prv_pstate, *cur_pstate;
2061 int32_t prv_x, cur_x, prv_id, cur_id;
2062
2063 prv_pstate = &pstates[i - 1];
2064 cur_pstate = &pstates[i];
2065 if (prv_pstate->stage != cur_pstate->stage)
2066 continue;
2067
2068 prv_x = prv_pstate->drm_pstate->crtc_x;
2069 cur_x = cur_pstate->drm_pstate->crtc_x;
2070 prv_id = prv_pstate->sde_pstate->base.plane->base.id;
2071 cur_id = cur_pstate->sde_pstate->base.plane->base.id;
2072
2073 /*
2074 * Planes are enumerated in pipe-priority order such that planes
2075 * with lower drm_id must be left-most in a shared blend-stage
2076 * when using source split.
2077 */
2078 if (cur_x > prv_x && cur_id < prv_id) {
2079 SDE_ERROR(
2080 "shared z_pos %d lower id plane%d @ x%d should be left of plane%d @ x %d\n",
2081 cur_pstate->stage, cur_id, cur_x,
2082 prv_id, prv_x);
2083 rc = -EINVAL;
2084 goto end;
2085 } else if (cur_x < prv_x && cur_id > prv_id) {
2086 SDE_ERROR(
2087 "shared z_pos %d lower id plane%d @ x%d should be left of plane%d @ x %d\n",
2088 cur_pstate->stage, prv_id, prv_x,
2089 cur_id, cur_x);
2090 rc = -EINVAL;
2091 goto end;
2092 }
2093 }
2094
2095
Dhaval Patelec10fad2016-08-22 14:40:48 -07002096end:
Alan Kwongcdb2f282017-03-18 13:42:06 -07002097 _sde_crtc_rp_free_unused(&cstate->rp);
Dhaval Patelec10fad2016-08-22 14:40:48 -07002098 return rc;
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002099}
2100
Abhijit Kulkarni7acb3262016-07-05 15:27:25 -04002101int sde_crtc_vblank(struct drm_crtc *crtc, bool en)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002102{
Clarence Ip7f70ce42017-03-20 06:53:46 -07002103 struct sde_crtc *sde_crtc;
2104 int rc = 0;
Abhijit Kulkarni7acb3262016-07-05 15:27:25 -04002105
Clarence Ip7f70ce42017-03-20 06:53:46 -07002106 if (!crtc) {
2107 SDE_ERROR("invalid crtc\n");
2108 return -EINVAL;
2109 }
2110 sde_crtc = to_sde_crtc(crtc);
2111
2112 mutex_lock(&sde_crtc->crtc_lock);
Alan Kwong07da0982016-11-04 12:57:45 -04002113 if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) {
2114 SDE_DEBUG("crtc%d vblank enable\n", crtc->base.id);
Clarence Ip7f70ce42017-03-20 06:53:46 -07002115 if (!sde_crtc->suspend)
2116 _sde_crtc_vblank_enable_nolock(sde_crtc, true);
Alan Kwong07da0982016-11-04 12:57:45 -04002117 } else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) {
2118 SDE_ERROR("crtc%d invalid vblank disable\n", crtc->base.id);
Clarence Ip7f70ce42017-03-20 06:53:46 -07002119 rc = -EINVAL;
Alan Kwong07da0982016-11-04 12:57:45 -04002120 } else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) {
2121 SDE_DEBUG("crtc%d vblank disable\n", crtc->base.id);
Clarence Ip7f70ce42017-03-20 06:53:46 -07002122 if (!sde_crtc->suspend)
2123 _sde_crtc_vblank_enable_nolock(sde_crtc, false);
Alan Kwong07da0982016-11-04 12:57:45 -04002124 } else {
2125 SDE_DEBUG("crtc%d vblank %s refcount:%d\n",
2126 crtc->base.id,
2127 en ? "enable" : "disable",
2128 atomic_read(&sde_crtc->vblank_refcount));
Alan Kwong07da0982016-11-04 12:57:45 -04002129 }
Lloyd Atkinsone5c2c0b2016-07-05 12:23:29 -04002130
Clarence Ip7f70ce42017-03-20 06:53:46 -07002131 mutex_unlock(&sde_crtc->crtc_lock);
2132 return rc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002133}
2134
Lloyd Atkinson5217336c2016-09-15 18:21:18 -04002135void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file)
2136{
2137 struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
2138
Alan Kwong163d2612016-11-03 00:56:56 -04002139 SDE_DEBUG("%s: cancel: %p\n", sde_crtc->name, file);
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04002140 _sde_crtc_complete_flip(crtc, file);
Lloyd Atkinson5217336c2016-09-15 18:21:18 -04002141}
2142
Clarence Ip7a753bb2016-07-07 11:47:44 -04002143/**
2144 * sde_crtc_install_properties - install all drm properties for crtc
2145 * @crtc: Pointer to drm crtc structure
2146 */
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002147static void sde_crtc_install_properties(struct drm_crtc *crtc,
2148 struct sde_mdss_cfg *catalog)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002149{
Clarence Ip7a753bb2016-07-07 11:47:44 -04002150 struct sde_crtc *sde_crtc;
2151 struct drm_device *dev;
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002152 struct sde_kms_info *info;
Alan Kwong9aa061c2016-11-06 21:17:12 -05002153 struct sde_kms *sde_kms;
Clarence Ip7a753bb2016-07-07 11:47:44 -04002154
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04002155 SDE_DEBUG("\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002156
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002157 if (!crtc || !catalog) {
2158 SDE_ERROR("invalid crtc or catalog\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002159 return;
2160 }
2161
2162 sde_crtc = to_sde_crtc(crtc);
2163 dev = crtc->dev;
Alan Kwong9aa061c2016-11-06 21:17:12 -05002164 sde_kms = _sde_crtc_get_kms(crtc);
Clarence Ip7a753bb2016-07-07 11:47:44 -04002165
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002166 info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
2167 if (!info) {
2168 SDE_ERROR("failed to allocate info memory\n");
2169 return;
2170 }
2171
Clarence Ip7a753bb2016-07-07 11:47:44 -04002172 /* range properties */
2173 msm_property_install_range(&sde_crtc->property_info,
Dhaval Patel4e574842016-08-23 15:11:37 -07002174 "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT,
2175 SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT);
2176
2177 msm_property_install_range(&sde_crtc->property_info, "output_fence",
2178 0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE);
Clarence Ip1d9728b2016-09-01 11:10:54 -04002179
2180 msm_property_install_range(&sde_crtc->property_info,
2181 "output_fence_offset", 0x0, 0, 1, 0,
2182 CRTC_PROP_OUTPUT_FENCE_OFFSET);
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002183
Alan Kwong9aa061c2016-11-06 21:17:12 -05002184 msm_property_install_range(&sde_crtc->property_info,
2185 "core_clk", 0x0, 0, U64_MAX,
2186 sde_kms->perf.max_core_clk_rate,
2187 CRTC_PROP_CORE_CLK);
2188 msm_property_install_range(&sde_crtc->property_info,
2189 "core_ab", 0x0, 0, U64_MAX,
Dhaval Patel60c25062017-02-21 17:44:05 -08002190 SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
Alan Kwong9aa061c2016-11-06 21:17:12 -05002191 CRTC_PROP_CORE_AB);
2192 msm_property_install_range(&sde_crtc->property_info,
2193 "core_ib", 0x0, 0, U64_MAX,
Dhaval Patel60c25062017-02-21 17:44:05 -08002194 SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA,
Alan Kwong9aa061c2016-11-06 21:17:12 -05002195 CRTC_PROP_CORE_IB);
Alan Kwong4aacd532017-02-04 18:51:33 -08002196 msm_property_install_range(&sde_crtc->property_info,
Alan Kwong8c176bf2017-02-09 19:34:32 -08002197 "mem_ab", 0x0, 0, U64_MAX,
2198 SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
2199 CRTC_PROP_MEM_AB);
2200 msm_property_install_range(&sde_crtc->property_info,
2201 "mem_ib", 0x0, 0, U64_MAX,
2202 SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
2203 CRTC_PROP_MEM_IB);
2204 msm_property_install_range(&sde_crtc->property_info,
Alan Kwong4aacd532017-02-04 18:51:33 -08002205 "rot_prefill_bw", 0, 0, U64_MAX,
2206 catalog->perf.max_bw_high * 1000ULL,
2207 CRTC_PROP_ROT_PREFILL_BW);
Alan Kwong8c176bf2017-02-09 19:34:32 -08002208 msm_property_install_range(&sde_crtc->property_info,
2209 "rot_clk", 0, 0, U64_MAX,
2210 sde_kms->perf.max_core_clk_rate,
2211 CRTC_PROP_ROT_CLK);
Alan Kwong9aa061c2016-11-06 21:17:12 -05002212
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002213 msm_property_install_blob(&sde_crtc->property_info, "capabilities",
2214 DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO);
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08002215
2216 if (catalog->has_dim_layer) {
2217 msm_property_install_volatile_range(&sde_crtc->property_info,
2218 "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1);
2219 }
2220
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002221 sde_kms_info_reset(info);
2222
2223 sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion);
2224 sde_kms_info_add_keyint(info, "max_linewidth",
2225 catalog->max_mixer_width);
2226 sde_kms_info_add_keyint(info, "max_blendstages",
2227 catalog->max_mixer_blendstages);
2228 if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2)
2229 sde_kms_info_add_keystr(info, "qseed_type", "qseed2");
2230 if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3)
2231 sde_kms_info_add_keystr(info, "qseed_type", "qseed3");
Jeykumar Sankaran2e655032017-02-04 14:05:45 -08002232
2233 if (sde_is_custom_client()) {
2234 if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V1)
2235 sde_kms_info_add_keystr(info,
2236 "smart_dma_rev", "smart_dma_v1");
2237 if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2)
2238 sde_kms_info_add_keystr(info,
2239 "smart_dma_rev", "smart_dma_v2");
2240 }
2241
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002242 sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split);
Alan Kwong2f84f8a2016-12-29 13:07:47 -05002243 if (catalog->perf.max_bw_low)
2244 sde_kms_info_add_keyint(info, "max_bandwidth_low",
2245 catalog->perf.max_bw_low);
2246 if (catalog->perf.max_bw_high)
2247 sde_kms_info_add_keyint(info, "max_bandwidth_high",
2248 catalog->perf.max_bw_high);
2249 if (sde_kms->perf.max_core_clk_rate)
2250 sde_kms_info_add_keyint(info, "max_mdp_clk",
2251 sde_kms->perf.max_core_clk_rate);
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002252 msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info,
2253 info->data, info->len, CRTC_PROP_INFO);
2254
2255 kfree(info);
Clarence Ip7a753bb2016-07-07 11:47:44 -04002256}
2257
2258/**
2259 * sde_crtc_atomic_set_property - atomically set a crtc drm property
2260 * @crtc: Pointer to drm crtc structure
2261 * @state: Pointer to drm crtc state structure
2262 * @property: Pointer to targeted drm property
2263 * @val: Updated property value
2264 * @Returns: Zero on success
2265 */
2266static int sde_crtc_atomic_set_property(struct drm_crtc *crtc,
2267 struct drm_crtc_state *state,
2268 struct drm_property *property,
2269 uint64_t val)
2270{
2271 struct sde_crtc *sde_crtc;
2272 struct sde_crtc_state *cstate;
Clarence Ipcae1bb62016-07-07 12:07:13 -04002273 int idx, ret = -EINVAL;
Clarence Ip7a753bb2016-07-07 11:47:44 -04002274
2275 if (!crtc || !state || !property) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07002276 SDE_ERROR("invalid argument(s)\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002277 } else {
2278 sde_crtc = to_sde_crtc(crtc);
2279 cstate = to_sde_crtc_state(state);
2280 ret = msm_property_atomic_set(&sde_crtc->property_info,
2281 cstate->property_values, cstate->property_blobs,
2282 property, val);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002283 if (!ret) {
2284 idx = msm_property_index(&sde_crtc->property_info,
2285 property);
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08002286 switch (idx) {
2287 case CRTC_PROP_INPUT_FENCE_TIMEOUT:
Clarence Ipcae1bb62016-07-07 12:07:13 -04002288 _sde_crtc_set_input_fence_timeout(cstate);
Veera Sundaram Sankaran3171ff82017-01-04 14:34:47 -08002289 break;
2290 case CRTC_PROP_DIM_LAYER_V1:
2291 _sde_crtc_set_dim_layer_v1(cstate, (void *)val);
2292 break;
2293 default:
2294 /* nothing to do */
2295 break;
2296 }
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002297 } else {
2298 ret = sde_cp_crtc_set_property(crtc,
2299 property, val);
Clarence Ipcae1bb62016-07-07 12:07:13 -04002300 }
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002301 if (ret)
2302 DRM_ERROR("failed to set the property\n");
Alan Kwongcdb2f282017-03-18 13:42:06 -07002303
2304 SDE_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id,
2305 property->name, property->base.id, val, ret);
Clarence Ip7a753bb2016-07-07 11:47:44 -04002306 }
2307
2308 return ret;
2309}
2310
2311/**
2312 * sde_crtc_set_property - set a crtc drm property
2313 * @crtc: Pointer to drm crtc structure
2314 * @property: Pointer to targeted drm property
2315 * @val: Updated property value
2316 * @Returns: Zero on success
2317 */
2318static int sde_crtc_set_property(struct drm_crtc *crtc,
2319 struct drm_property *property, uint64_t val)
2320{
Lloyd Atkinson4f1c8692016-09-14 14:04:25 -04002321 SDE_DEBUG("\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002322
2323 return sde_crtc_atomic_set_property(crtc, crtc->state, property, val);
2324}
2325
2326/**
2327 * sde_crtc_atomic_get_property - retrieve a crtc drm property
2328 * @crtc: Pointer to drm crtc structure
2329 * @state: Pointer to drm crtc state structure
2330 * @property: Pointer to targeted drm property
2331 * @val: Pointer to variable for receiving property value
2332 * @Returns: Zero on success
2333 */
2334static int sde_crtc_atomic_get_property(struct drm_crtc *crtc,
2335 const struct drm_crtc_state *state,
2336 struct drm_property *property,
2337 uint64_t *val)
2338{
2339 struct sde_crtc *sde_crtc;
2340 struct sde_crtc_state *cstate;
Clarence Ip24f80662016-06-13 19:05:32 -04002341 int i, ret = -EINVAL;
Clarence Ip7a753bb2016-07-07 11:47:44 -04002342
2343 if (!crtc || !state) {
Dhaval Patelec10fad2016-08-22 14:40:48 -07002344 SDE_ERROR("invalid argument(s)\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002345 } else {
2346 sde_crtc = to_sde_crtc(crtc);
2347 cstate = to_sde_crtc_state(state);
Clarence Ip24f80662016-06-13 19:05:32 -04002348 i = msm_property_index(&sde_crtc->property_info, property);
2349 if (i == CRTC_PROP_OUTPUT_FENCE) {
Dhaval Patel39323d42017-03-01 23:48:24 -08002350 uint32_t offset = sde_crtc_get_property(cstate,
Clarence Ip1d9728b2016-09-01 11:10:54 -04002351 CRTC_PROP_OUTPUT_FENCE_OFFSET);
2352
2353 ret = sde_fence_create(
2354 &sde_crtc->output_fence, val, offset);
2355 if (ret)
2356 SDE_ERROR("fence create failed\n");
Clarence Ip24f80662016-06-13 19:05:32 -04002357 } else {
2358 ret = msm_property_atomic_get(&sde_crtc->property_info,
2359 cstate->property_values,
2360 cstate->property_blobs, property, val);
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002361 if (ret)
2362 ret = sde_cp_crtc_get_property(crtc,
2363 property, val);
Clarence Ip24f80662016-06-13 19:05:32 -04002364 }
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002365 if (ret)
2366 DRM_ERROR("get property failed\n");
Clarence Ip7a753bb2016-07-07 11:47:44 -04002367 }
Clarence Ip7a753bb2016-07-07 11:47:44 -04002368 return ret;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002369}
2370
Alan Kwong67a3f792016-11-01 23:16:53 -04002371#ifdef CONFIG_DEBUG_FS
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002372static int _sde_debugfs_status_show(struct seq_file *s, void *data)
Clarence Ip8f7366c2016-07-05 12:15:26 -04002373{
2374 struct sde_crtc *sde_crtc;
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002375 struct sde_plane_state *pstate = NULL;
Clarence Ip8f7366c2016-07-05 12:15:26 -04002376 struct sde_crtc_mixer *m;
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002377
2378 struct drm_crtc *crtc;
2379 struct drm_plane *plane;
2380 struct drm_display_mode *mode;
2381 struct drm_framebuffer *fb;
2382 struct drm_plane_state *state;
2383
2384 int i, out_width;
Clarence Ip8f7366c2016-07-05 12:15:26 -04002385
2386 if (!s || !s->private)
2387 return -EINVAL;
2388
2389 sde_crtc = s->private;
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002390 crtc = &sde_crtc->base;
2391
2392 mutex_lock(&sde_crtc->crtc_lock);
2393 mode = &crtc->state->adjusted_mode;
2394 out_width = sde_crtc_mixer_width(sde_crtc, mode);
2395
2396 seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
2397 mode->hdisplay, mode->vdisplay);
2398
2399 seq_puts(s, "\n");
2400
Clarence Ip8f7366c2016-07-05 12:15:26 -04002401 for (i = 0; i < sde_crtc->num_mixers; ++i) {
Lloyd Atkinsone7bcdd22016-08-11 10:53:37 -04002402 m = &sde_crtc->mixers[i];
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002403 if (!m->hw_lm)
2404 seq_printf(s, "\tmixer[%d] has no lm\n", i);
2405 else if (!m->hw_ctl)
2406 seq_printf(s, "\tmixer[%d] has no ctl\n", i);
2407 else
2408 seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
2409 m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0,
2410 out_width, mode->vdisplay);
Clarence Ip8f7366c2016-07-05 12:15:26 -04002411 }
Dhaval Patel44f12472016-08-29 12:19:47 -07002412
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002413 seq_puts(s, "\n");
Dhaval Patel48c76022016-09-01 17:51:23 -07002414
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002415 drm_atomic_crtc_for_each_plane(plane, crtc) {
2416 pstate = to_sde_plane_state(plane->state);
2417 state = plane->state;
2418
2419 if (!pstate || !state)
2420 continue;
2421
2422 seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
2423 pstate->stage);
2424
2425 if (plane->state->fb) {
2426 fb = plane->state->fb;
2427
2428 seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u bpp:%d\n",
2429 fb->base.id, (char *) &fb->pixel_format,
2430 fb->width, fb->height, fb->bits_per_pixel);
2431
2432 seq_puts(s, "\t");
2433 for (i = 0; i < ARRAY_SIZE(fb->modifier); i++)
2434 seq_printf(s, "modifier[%d]:%8llu ", i,
2435 fb->modifier[i]);
2436 seq_puts(s, "\n");
2437
2438 seq_puts(s, "\t");
2439 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
2440 seq_printf(s, "pitches[%d]:%8u ", i,
2441 fb->pitches[i]);
2442 seq_puts(s, "\n");
2443
2444 seq_puts(s, "\t");
2445 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
2446 seq_printf(s, "offsets[%d]:%8u ", i,
2447 fb->offsets[i]);
Dhaval Patel48c76022016-09-01 17:51:23 -07002448 seq_puts(s, "\n");
2449 }
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002450
2451 seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
2452 state->src_x, state->src_y, state->src_w, state->src_h);
2453
2454 seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
2455 state->crtc_x, state->crtc_y, state->crtc_w,
2456 state->crtc_h);
2457 seq_puts(s, "\n");
Clarence Ip8f7366c2016-07-05 12:15:26 -04002458 }
Alan Kwong07da0982016-11-04 12:57:45 -04002459
2460 if (sde_crtc->vblank_cb_count) {
2461 ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time);
2462 s64 diff_ms = ktime_to_ms(diff);
2463 s64 fps = diff_ms ? DIV_ROUND_CLOSEST(
2464 sde_crtc->vblank_cb_count * 1000, diff_ms) : 0;
2465
2466 seq_printf(s,
2467 "vblank fps:%lld count:%u total:%llums\n",
2468 fps,
2469 sde_crtc->vblank_cb_count,
2470 ktime_to_ms(diff));
2471
2472 /* reset time & count for next measurement */
2473 sde_crtc->vblank_cb_count = 0;
2474 sde_crtc->vblank_cb_time = ktime_set(0, 0);
2475 }
2476
2477 seq_printf(s, "vblank_refcount:%d\n",
2478 atomic_read(&sde_crtc->vblank_refcount));
2479
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002480 mutex_unlock(&sde_crtc->crtc_lock);
2481
Clarence Ip8f7366c2016-07-05 12:15:26 -04002482 return 0;
2483}
2484
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002485static int _sde_debugfs_status_open(struct inode *inode, struct file *file)
Clarence Ip8f7366c2016-07-05 12:15:26 -04002486{
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002487 return single_open(file, _sde_debugfs_status_show, inode->i_private);
Clarence Ip8f7366c2016-07-05 12:15:26 -04002488}
2489
Dhaval Patelf9245d62017-03-28 16:24:00 -07002490static ssize_t _sde_crtc_misr_setup(struct file *file,
2491 const char __user *user_buf, size_t count, loff_t *ppos)
2492{
2493 struct sde_crtc *sde_crtc;
2494 struct sde_crtc_mixer *m;
2495 int i = 0, rc;
2496 char buf[MISR_BUFF_SIZE + 1];
2497 u32 frame_count, enable;
2498 size_t buff_copy;
2499
2500 if (!file || !file->private_data)
2501 return -EINVAL;
2502
2503 sde_crtc = file->private_data;
2504 buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
2505 if (copy_from_user(buf, user_buf, buff_copy)) {
2506 SDE_ERROR("buffer copy failed\n");
2507 return -EINVAL;
2508 }
2509
2510 buf[buff_copy] = 0; /* end of string */
2511
2512 if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
2513 return -EINVAL;
2514
2515 rc = _sde_crtc_power_enable(sde_crtc, true);
2516 if (rc)
2517 return rc;
2518
2519 mutex_lock(&sde_crtc->crtc_lock);
2520 sde_crtc->misr_enable = enable;
2521 for (i = 0; i < sde_crtc->num_mixers; ++i) {
2522 m = &sde_crtc->mixers[i];
2523 if (!m->hw_lm)
2524 continue;
2525
2526 m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count);
2527 }
2528 mutex_unlock(&sde_crtc->crtc_lock);
2529 _sde_crtc_power_enable(sde_crtc, false);
2530
2531 return count;
2532}
2533
2534static ssize_t _sde_crtc_misr_read(struct file *file,
2535 char __user *user_buff, size_t count, loff_t *ppos)
2536{
2537 struct sde_crtc *sde_crtc;
2538 struct sde_crtc_mixer *m;
2539 int i = 0, rc;
2540 ssize_t len = 0;
2541 char buf[MISR_BUFF_SIZE + 1] = {'\0'};
2542
2543 if (*ppos)
2544 return 0;
2545
2546 if (!file || !file->private_data)
2547 return -EINVAL;
2548
2549 sde_crtc = file->private_data;
2550 rc = _sde_crtc_power_enable(sde_crtc, true);
2551 if (rc)
2552 return rc;
2553
2554 mutex_lock(&sde_crtc->crtc_lock);
2555 if (!sde_crtc->misr_enable) {
2556 len += snprintf(buf + len, MISR_BUFF_SIZE - len,
2557 "disabled\n");
2558 goto buff_check;
2559 }
2560
2561 for (i = 0; i < sde_crtc->num_mixers; ++i) {
2562 m = &sde_crtc->mixers[i];
2563 if (!m->hw_lm)
2564 continue;
2565
2566 len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n",
2567 m->hw_lm->idx - LM_0);
2568 len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n",
2569 m->hw_lm->ops.collect_misr(m->hw_lm));
2570 }
2571
2572buff_check:
2573 if (count <= len) {
2574 len = 0;
2575 goto end;
2576 }
2577
2578 if (copy_to_user(user_buff, buf, len)) {
2579 len = -EFAULT;
2580 goto end;
2581 }
2582
2583 *ppos += len; /* increase offset */
2584
2585end:
2586 mutex_unlock(&sde_crtc->crtc_lock);
2587 _sde_crtc_power_enable(sde_crtc, false);
2588 return len;
2589}
2590
2591#define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \
Alan Kwong67a3f792016-11-01 23:16:53 -04002592static int __prefix ## _open(struct inode *inode, struct file *file) \
2593{ \
2594 return single_open(file, __prefix ## _show, inode->i_private); \
2595} \
2596static const struct file_operations __prefix ## _fops = { \
2597 .owner = THIS_MODULE, \
2598 .open = __prefix ## _open, \
2599 .release = single_release, \
2600 .read = seq_read, \
2601 .llseek = seq_lseek, \
2602}
2603
2604static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v)
2605{
2606 struct drm_crtc *crtc = (struct drm_crtc *) s->private;
2607 struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state);
Alan Kwongcdb2f282017-03-18 13:42:06 -07002608 struct sde_crtc_res *res;
Alan Kwong67a3f792016-11-01 23:16:53 -04002609
2610 seq_printf(s, "num_connectors: %d\n", cstate->num_connectors);
Dhaval Patel4d424602017-02-18 19:40:14 -08002611 seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc));
Alan Kwong3e985f02017-02-12 15:08:44 -08002612 seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc));
Alan Kwong9aa061c2016-11-06 21:17:12 -05002613 seq_printf(s, "bw_ctl: %llu\n", cstate->cur_perf.bw_ctl);
2614 seq_printf(s, "core_clk_rate: %u\n", cstate->cur_perf.core_clk_rate);
2615 seq_printf(s, "max_per_pipe_ib: %llu\n",
2616 cstate->cur_perf.max_per_pipe_ib);
Alan Kwong67a3f792016-11-01 23:16:53 -04002617
Alan Kwongcdb2f282017-03-18 13:42:06 -07002618 seq_printf(s, "rp.%d: ", cstate->rp.sequence_id);
2619 list_for_each_entry(res, &cstate->rp.res_list, list)
2620 seq_printf(s, "0x%x/0x%llx/%pK/%d ",
2621 res->type, res->tag, res->val,
2622 atomic_read(&res->refcount));
2623 seq_puts(s, "\n");
2624
Alan Kwong67a3f792016-11-01 23:16:53 -04002625 return 0;
2626}
2627DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state);
2628
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002629static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
Clarence Ip8f7366c2016-07-05 12:15:26 -04002630{
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002631 struct sde_crtc *sde_crtc;
2632 struct sde_kms *sde_kms;
2633
Dhaval Patel3fbe6bf2016-10-20 20:00:41 -07002634 static const struct file_operations debugfs_status_fops = {
2635 .open = _sde_debugfs_status_open,
Clarence Ip8f7366c2016-07-05 12:15:26 -04002636 .read = seq_read,
2637 .llseek = seq_lseek,
2638 .release = single_release,
2639 };
Dhaval Patelf9245d62017-03-28 16:24:00 -07002640 static const struct file_operations debugfs_misr_fops = {
2641 .open = simple_open,
2642 .read = _sde_crtc_misr_read,
2643 .write = _sde_crtc_misr_setup,
2644 };
Alan Kwong67a3f792016-11-01 23:16:53 -04002645
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002646 if (!crtc)
2647 return -EINVAL;
2648 sde_crtc = to_sde_crtc(crtc);
2649
2650 sde_kms = _sde_crtc_get_kms(crtc);
2651 if (!sde_kms)
2652 return -EINVAL;
2653
2654 sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name,
2655 sde_debugfs_get_root(sde_kms));
2656 if (!sde_crtc->debugfs_root)
2657 return -ENOMEM;
2658
2659 /* don't error check these */
2660 debugfs_create_file("status", 0444,
2661 sde_crtc->debugfs_root,
2662 sde_crtc, &debugfs_status_fops);
2663 debugfs_create_file("state", 0644,
2664 sde_crtc->debugfs_root,
2665 &sde_crtc->base,
2666 &sde_crtc_debugfs_state_fops);
Dhaval Patelf9245d62017-03-28 16:24:00 -07002667 debugfs_create_file("misr_data", 0644, sde_crtc->debugfs_root,
2668 sde_crtc, &debugfs_misr_fops);
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002669
2670 return 0;
2671}
2672
2673static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
2674{
2675 struct sde_crtc *sde_crtc;
2676
2677 if (!crtc)
2678 return;
2679 sde_crtc = to_sde_crtc(crtc);
2680 debugfs_remove_recursive(sde_crtc->debugfs_root);
Clarence Ip8f7366c2016-07-05 12:15:26 -04002681}
Alan Kwong67a3f792016-11-01 23:16:53 -04002682#else
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002683static int _sde_crtc_init_debugfs(struct drm_crtc *crtc)
Alan Kwong67a3f792016-11-01 23:16:53 -04002684{
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002685 return 0;
Alan Kwong67a3f792016-11-01 23:16:53 -04002686}
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002687
2688static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc)
2689{
Lloyd Atkinsonb020e0f2017-03-14 08:05:18 -07002690}
2691#endif /* CONFIG_DEBUG_FS */
2692
2693static int sde_crtc_late_register(struct drm_crtc *crtc)
2694{
2695 return _sde_crtc_init_debugfs(crtc);
2696}
2697
2698static void sde_crtc_early_unregister(struct drm_crtc *crtc)
2699{
2700 _sde_crtc_destroy_debugfs(crtc);
2701}
2702
2703static const struct drm_crtc_funcs sde_crtc_funcs = {
2704 .set_config = drm_atomic_helper_set_config,
2705 .destroy = sde_crtc_destroy,
2706 .page_flip = drm_atomic_helper_page_flip,
2707 .set_property = sde_crtc_set_property,
2708 .atomic_set_property = sde_crtc_atomic_set_property,
2709 .atomic_get_property = sde_crtc_atomic_get_property,
2710 .reset = sde_crtc_reset,
2711 .atomic_duplicate_state = sde_crtc_duplicate_state,
2712 .atomic_destroy_state = sde_crtc_destroy_state,
2713 .late_register = sde_crtc_late_register,
2714 .early_unregister = sde_crtc_early_unregister,
2715};
2716
2717static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = {
2718 .mode_fixup = sde_crtc_mode_fixup,
2719 .disable = sde_crtc_disable,
2720 .enable = sde_crtc_enable,
2721 .atomic_check = sde_crtc_atomic_check,
2722 .atomic_begin = sde_crtc_atomic_begin,
2723 .atomic_flush = sde_crtc_atomic_flush,
2724};
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002725
Clarence Ipa18d4832017-03-13 12:35:44 -07002726static void _sde_crtc_event_cb(struct kthread_work *work)
2727{
2728 struct sde_crtc_event *event;
2729 struct sde_crtc *sde_crtc;
2730 unsigned long irq_flags;
2731
2732 if (!work) {
2733 SDE_ERROR("invalid work item\n");
2734 return;
2735 }
2736
2737 event = container_of(work, struct sde_crtc_event, kt_work);
Clarence Ipa18d4832017-03-13 12:35:44 -07002738
2739 /* set sde_crtc to NULL for static work structures */
2740 sde_crtc = event->sde_crtc;
2741 if (!sde_crtc)
2742 return;
2743
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002744 if (event->cb_func)
2745 event->cb_func(&sde_crtc->base, event->usr);
2746
Clarence Ipa18d4832017-03-13 12:35:44 -07002747 spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
2748 list_add_tail(&event->list, &sde_crtc->event_free_list);
2749 spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
2750}
2751
2752int sde_crtc_event_queue(struct drm_crtc *crtc,
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002753 void (*func)(struct drm_crtc *crtc, void *usr), void *usr)
Clarence Ipa18d4832017-03-13 12:35:44 -07002754{
2755 unsigned long irq_flags;
2756 struct sde_crtc *sde_crtc;
2757 struct sde_crtc_event *event = NULL;
2758
2759 if (!crtc || !func)
2760 return -EINVAL;
2761 sde_crtc = to_sde_crtc(crtc);
2762
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002763 if (!sde_crtc->event_thread)
2764 return -EINVAL;
Clarence Ipa18d4832017-03-13 12:35:44 -07002765 /*
2766 * Obtain an event struct from the private cache. This event
2767 * queue may be called from ISR contexts, so use a private
2768 * cache to avoid calling any memory allocation functions.
2769 */
2770 spin_lock_irqsave(&sde_crtc->event_lock, irq_flags);
2771 if (!list_empty(&sde_crtc->event_free_list)) {
2772 event = list_first_entry(&sde_crtc->event_free_list,
2773 struct sde_crtc_event, list);
2774 list_del_init(&event->list);
2775 }
2776 spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags);
2777
2778 if (!event)
2779 return -ENOMEM;
2780
2781 /* populate event node */
2782 event->sde_crtc = sde_crtc;
2783 event->cb_func = func;
2784 event->usr = usr;
2785
2786 /* queue new event request */
2787 kthread_init_work(&event->kt_work, _sde_crtc_event_cb);
2788 kthread_queue_work(&sde_crtc->event_worker, &event->kt_work);
2789
2790 return 0;
2791}
2792
2793static int _sde_crtc_init_events(struct sde_crtc *sde_crtc)
2794{
2795 int i, rc = 0;
2796
2797 if (!sde_crtc) {
2798 SDE_ERROR("invalid crtc\n");
2799 return -EINVAL;
2800 }
2801
2802 spin_lock_init(&sde_crtc->event_lock);
2803
2804 INIT_LIST_HEAD(&sde_crtc->event_free_list);
2805 for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i)
2806 list_add_tail(&sde_crtc->event_cache[i].list,
2807 &sde_crtc->event_free_list);
2808
2809 kthread_init_worker(&sde_crtc->event_worker);
2810 sde_crtc->event_thread = kthread_run(kthread_worker_fn,
2811 &sde_crtc->event_worker, "crtc_event:%d",
2812 sde_crtc->base.base.id);
2813
2814 if (IS_ERR_OR_NULL(sde_crtc->event_thread)) {
2815 SDE_ERROR("failed to create event thread\n");
2816 rc = PTR_ERR(sde_crtc->event_thread);
2817 sde_crtc->event_thread = NULL;
2818 }
2819
2820 return rc;
2821}
2822
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002823/* initialize crtc */
Lloyd Atkinsonac933642016-09-14 11:52:00 -04002824struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane)
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002825{
2826 struct drm_crtc *crtc = NULL;
Clarence Ip8f7366c2016-07-05 12:15:26 -04002827 struct sde_crtc *sde_crtc = NULL;
2828 struct msm_drm_private *priv = NULL;
2829 struct sde_kms *kms = NULL;
Clarence Ipa18d4832017-03-13 12:35:44 -07002830 int i, rc;
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002831
Clarence Ip8f7366c2016-07-05 12:15:26 -04002832 priv = dev->dev_private;
2833 kms = to_sde_kms(priv->kms);
2834
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002835 sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL);
2836 if (!sde_crtc)
2837 return ERR_PTR(-ENOMEM);
2838
2839 crtc = &sde_crtc->base;
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002840 crtc->dev = dev;
Alan Kwong07da0982016-11-04 12:57:45 -04002841 atomic_set(&sde_crtc->vblank_refcount, 0);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002842
Clarence Ip7f70ce42017-03-20 06:53:46 -07002843 mutex_init(&sde_crtc->crtc_lock);
Alan Kwong628d19e2016-10-31 13:50:13 -04002844 spin_lock_init(&sde_crtc->spin_lock);
2845 atomic_set(&sde_crtc->frame_pending, 0);
2846
2847 INIT_LIST_HEAD(&sde_crtc->frame_event_list);
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07002848 INIT_LIST_HEAD(&sde_crtc->user_event_list);
Alan Kwong628d19e2016-10-31 13:50:13 -04002849 for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) {
2850 INIT_LIST_HEAD(&sde_crtc->frame_events[i].list);
2851 list_add(&sde_crtc->frame_events[i].list,
2852 &sde_crtc->frame_event_list);
2853 kthread_init_work(&sde_crtc->frame_events[i].work,
2854 sde_crtc_frame_event_work);
2855 }
2856
Dhaval Patel04c7e8e2016-09-26 20:14:31 -07002857 drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs,
2858 NULL);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002859
2860 drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs);
Abhijit Kulkarni3e3e0d22016-06-24 17:56:13 -04002861 plane->crtc = crtc;
2862
Clarence Ip8f7366c2016-07-05 12:15:26 -04002863 /* save user friendly CRTC name for later */
2864 snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
2865
Clarence Ipa18d4832017-03-13 12:35:44 -07002866 /* initialize event handling */
2867 rc = _sde_crtc_init_events(sde_crtc);
2868 if (rc) {
2869 drm_crtc_cleanup(crtc);
2870 kfree(sde_crtc);
2871 return ERR_PTR(rc);
2872 }
2873
Clarence Ip9a74a442016-08-25 18:29:03 -04002874 /* initialize output fence support */
Lloyd Atkinson5d40d312016-09-06 08:34:13 -04002875 sde_fence_init(&sde_crtc->output_fence, sde_crtc->name, crtc->base.id);
Clarence Ip24f80662016-06-13 19:05:32 -04002876
Clarence Ip7a753bb2016-07-07 11:47:44 -04002877 /* create CRTC properties */
2878 msm_property_init(&sde_crtc->property_info, &crtc->base, dev,
2879 priv->crtc_property, sde_crtc->property_data,
2880 CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT,
2881 sizeof(struct sde_crtc_state));
2882
Dhaval Patele4a5dda2016-10-13 19:29:30 -07002883 sde_crtc_install_properties(crtc, kms->catalog);
Gopikrishnaiah Anandan703eb902016-10-06 18:43:57 -07002884
2885 /* Install color processing properties */
Gopikrishnaiah Anandane0e5e0c2016-05-25 11:05:33 -07002886 sde_cp_crtc_init(crtc);
Gopikrishnaiah Anandan703eb902016-10-06 18:43:57 -07002887 sde_cp_crtc_install_properties(crtc);
Clarence Ip7a753bb2016-07-07 11:47:44 -04002888
Dhaval Patelec10fad2016-08-22 14:40:48 -07002889 SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name);
Narendra Muppalla1b0b3352015-09-29 10:16:51 -07002890 return crtc;
2891}
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07002892
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002893static int _sde_crtc_event_enable(struct sde_kms *kms,
2894 struct drm_crtc *crtc_drm, u32 event)
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07002895{
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002896 struct sde_crtc *crtc = NULL;
2897 struct sde_crtc_irq_info *node;
2898 struct msm_drm_private *priv;
2899 unsigned long flags;
2900 bool found = false;
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002901 int ret, i = 0;
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002902
2903 crtc = to_sde_crtc(crtc_drm);
2904 spin_lock_irqsave(&crtc->spin_lock, flags);
2905 list_for_each_entry(node, &crtc->user_event_list, list) {
2906 if (node->event == event) {
2907 found = true;
2908 break;
2909 }
2910 }
2911 spin_unlock_irqrestore(&crtc->spin_lock, flags);
2912
2913 /* event already enabled */
2914 if (found)
2915 return 0;
2916
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002917 node = NULL;
2918 for (i = 0; i < ARRAY_SIZE(custom_events); i++) {
2919 if (custom_events[i].event == event &&
2920 custom_events[i].func) {
2921 node = kzalloc(sizeof(*node), GFP_KERNEL);
2922 if (!node)
2923 return -ENOMEM;
2924 node->event = event;
2925 INIT_LIST_HEAD(&node->list);
2926 node->func = custom_events[i].func;
2927 node->event = event;
2928 break;
2929 }
2930 }
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002931
Gopikrishnaiah Anandanb6b401f2017-03-14 16:39:49 -07002932 if (!node) {
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002933 SDE_ERROR("unsupported event %x\n", event);
Gopikrishnaiah Anandan5154c712017-02-27 17:48:24 -08002934 return -EINVAL;
2935 }
2936
2937 priv = kms->dev->dev_private;
2938 ret = 0;
2939 if (crtc_drm->enabled) {
2940 sde_power_resource_enable(&priv->phandle, kms->core_client,
2941 true);
2942 ret = node->func(crtc_drm, true, &node->irq);
2943 sde_power_resource_enable(&priv->phandle, kms->core_client,
2944 false);
2945 }
2946
2947 if (!ret) {
2948 spin_lock_irqsave(&crtc->spin_lock, flags);
2949 list_add_tail(&node->list, &crtc->user_event_list);
2950 spin_unlock_irqrestore(&crtc->spin_lock, flags);
2951 } else {
2952 kfree(node);
2953 }
2954
2955 return ret;
2956}
2957
2958static int _sde_crtc_event_disable(struct sde_kms *kms,
2959 struct drm_crtc *crtc_drm, u32 event)
2960{
2961 struct sde_crtc *crtc = NULL;
2962 struct sde_crtc_irq_info *node = NULL;
2963 struct msm_drm_private *priv;
2964 unsigned long flags;
2965 bool found = false;
2966 int ret;
2967
2968 crtc = to_sde_crtc(crtc_drm);
2969 spin_lock_irqsave(&crtc->spin_lock, flags);
2970 list_for_each_entry(node, &crtc->user_event_list, list) {
2971 if (node->event == event) {
2972 list_del(&node->list);
2973 found = true;
2974 break;
2975 }
2976 }
2977 spin_unlock_irqrestore(&crtc->spin_lock, flags);
2978
2979 /* event already disabled */
2980 if (!found)
2981 return 0;
2982
2983 /**
2984 * crtc is disabled interrupts are cleared remove from the list,
2985 * no need to disable/de-register.
2986 */
2987 if (!crtc_drm->enabled) {
2988 kfree(node);
2989 return 0;
2990 }
2991 priv = kms->dev->dev_private;
2992 sde_power_resource_enable(&priv->phandle, kms->core_client, true);
2993 ret = node->func(crtc_drm, false, &node->irq);
2994 sde_power_resource_enable(&priv->phandle, kms->core_client, false);
2995 return ret;
2996}
2997
2998int sde_crtc_register_custom_event(struct sde_kms *kms,
2999 struct drm_crtc *crtc_drm, u32 event, bool en)
3000{
3001 struct sde_crtc *crtc = NULL;
3002 int ret;
3003
3004 crtc = to_sde_crtc(crtc_drm);
3005 if (!crtc || !kms || !kms->dev) {
3006 DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc,
3007 kms, ((kms) ? (kms->dev) : NULL));
3008 return -EINVAL;
3009 }
3010
3011 if (en)
3012 ret = _sde_crtc_event_enable(kms, crtc_drm, event);
3013 else
3014 ret = _sde_crtc_event_disable(kms, crtc_drm, event);
3015
3016 return ret;
Gopikrishnaiah Anandande2c81b2017-03-15 12:41:29 -07003017}