| raghavendra ambadas | d865614 | 2018-03-13 15:52:39 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | &soc { |
| 15 | gfx_iommu: qcom,iommu@1f00000 { |
| 16 | status = "ok"; |
| 17 | compatible = "qcom,qsmmu-v500"; |
| 18 | reg = <0x1f00000 0x10000>, |
| 19 | <0x1ee2000 0x20>; |
| 20 | reg-names = "base", "tcu-base"; |
| 21 | #iommu-cells = <1>; |
| 22 | qcom,tz-device-id = "GPU"; |
| 23 | qcom,skip-init; |
| 24 | qcom,enable-static-cb; |
| 25 | qcom,dynamic; |
| 26 | qcom,use-3-lvl-tables; |
| 27 | #global-interrupts = <0>; |
| 28 | #size-cells = <1>; |
| 29 | #address-cells = <1>; |
| 30 | ranges; |
| 31 | interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, |
| 32 | <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, |
| 33 | <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, |
| 34 | <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; |
| 35 | clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>, |
| 36 | <&clock_gcc clk_gcc_gfx_tcu_clk>; |
| 37 | clock-names = "iface_clk", "core_clk"; |
| 38 | }; |
| 39 | |
| 40 | apps_iommu: qcom,iommu@1e00000 { |
| 41 | status = "okay"; |
| 42 | compatible = "qcom,qsmmu-v500"; |
| 43 | reg = <0x1e00000 0x40000>, |
| 44 | <0x1ee2000 0x20>; |
| 45 | reg-names = "base", "tcu-base"; |
| 46 | #iommu-cells = <2>; |
| 47 | qcom,tz-device-id = "APPS"; |
| 48 | qcom,skip-init; |
| 49 | qcom,disable-atos; |
| 50 | ranges; |
| 51 | qcom,enable-static-cb; |
| 52 | qcom,use-3-lvl-tables; |
| 53 | #global-interrupts = <0>; |
| 54 | #size-cells = <1>; |
| 55 | #address-cells = <1>; |
| 56 | interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, |
| 57 | <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, |
| 58 | <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, |
| 59 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| 60 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| 61 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| 62 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| 63 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| 64 | <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, |
| 66 | <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, |
| 68 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| 69 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| 71 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| 74 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| 75 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| 76 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| 78 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| 79 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| 81 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 84 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, |
| 85 | <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
| 86 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, |
| 87 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| 88 | clocks = <&clock_gcc clk_gcc_smmu_cfg_clk>, |
| 89 | <&clock_gcc clk_gcc_apss_tcu_clk>; |
| 90 | clock-names = "iface_clk", "core_clk"; |
| 91 | }; |
| 92 | }; |