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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/mtd/nand/spia.c
3 *
4 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
5 *
6 *
7 * 10-29-2001 TG change to support hardwarespecific access
8 * to controllines (due to change in nand.c)
9 * page_cache added
10 *
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000011 * $Id: spia.c,v 1.25 2005/11/07 11:14:31 gleixner Exp $
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 * Overview:
18 * This is a device driver for the NAND flash device found on the
19 * SPIA board which utilizes the Toshiba TC58V64AFT part. This is
20 * a 64Mibit (8MiB x 8 bits) NAND flash device.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <linux/mtd/mtd.h>
28#include <linux/mtd/nand.h>
29#include <linux/mtd/partitions.h>
30#include <asm/io.h>
31
32/*
33 * MTD structure for SPIA board
34 */
35static struct mtd_info *spia_mtd = NULL;
36
37/*
38 * Values specific to the SPIA board (used with EP7212 processor)
39 */
40#define SPIA_IO_BASE 0xd0000000 /* Start of EP7212 IO address space */
41#define SPIA_FIO_BASE 0xf0000000 /* Address where flash is mapped */
42#define SPIA_PEDR 0x0080 /*
43 * IO offset to Port E data register
44 * where the CLE, ALE and NCE pins
45 * are wired to.
46 */
47#define SPIA_PEDDR 0x00c0 /*
48 * IO offset to Port E data direction
49 * register so we can control the IO
50 * lines.
51 */
52
53/*
54 * Module stuff
55 */
56
57static int spia_io_base = SPIA_IO_BASE;
58static int spia_fio_base = SPIA_FIO_BASE;
59static int spia_pedr = SPIA_PEDR;
60static int spia_peddr = SPIA_PEDDR;
61
62module_param(spia_io_base, int, 0);
63module_param(spia_fio_base, int, 0);
64module_param(spia_pedr, int, 0);
65module_param(spia_peddr, int, 0);
66
67/*
68 * Define partitions for flash device
69 */
70const static struct mtd_partition partition_info[] = {
71 {
72 .name = "SPIA flash partition 1",
73 .offset = 0,
74 .size = 2*1024*1024
75 },
76 {
77 .name = "SPIA flash partition 2",
78 .offset = 2*1024*1024,
79 .size = 6*1024*1024
80 }
81};
82#define NUM_PARTITIONS 2
83
84
Thomas Gleixner61b03bd2005-11-07 11:15:49 +000085/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070086 * hardware specific access to control-lines
87*/
88static void spia_hwcontrol(struct mtd_info *mtd, int cmd){
89
90 switch(cmd){
91
92 case NAND_CTL_SETCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x01; break;
93 case NAND_CTL_CLRCLE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x01; break;
94
95 case NAND_CTL_SETALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x02; break;
96 case NAND_CTL_CLRALE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x02; break;
97
98 case NAND_CTL_SETNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) &= ~0x04; break;
99 case NAND_CTL_CLRNCE: (*(volatile unsigned char *) (spia_io_base + spia_pedr)) |= 0x04; break;
100 }
101}
102
103/*
104 * Main initialization routine
105 */
106int __init spia_init (void)
107{
108 struct nand_chip *this;
109
110 /* Allocate memory for MTD device structure and private data */
111 spia_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
112 GFP_KERNEL);
113 if (!spia_mtd) {
114 printk ("Unable to allocate SPIA NAND MTD device structure.\n");
115 return -ENOMEM;
116 }
117
118 /* Get pointer to private data */
119 this = (struct nand_chip *) (&spia_mtd[1]);
120
121 /* Initialize structures */
122 memset((char *) spia_mtd, 0, sizeof(struct mtd_info));
123 memset((char *) this, 0, sizeof(struct nand_chip));
124
125 /* Link the private data with the MTD structure */
126 spia_mtd->priv = this;
127
128 /*
129 * Set GPIO Port E control register so that the pins are configured
130 * to be outputs for controlling the NAND flash.
131 */
132 (*(volatile unsigned char *) (spia_io_base + spia_peddr)) = 0x07;
133
134 /* Set address of NAND IO lines */
135 this->IO_ADDR_R = (void __iomem *) spia_fio_base;
136 this->IO_ADDR_W = (void __iomem *) spia_fio_base;
137 /* Set address of hardware control function */
138 this->hwcontrol = spia_hwcontrol;
139 /* 15 us command delay time */
Thomas Gleixner61b03bd2005-11-07 11:15:49 +0000140 this->chip_delay = 15;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142 /* Scan to find existence of the device */
143 if (nand_scan (spia_mtd, 1)) {
144 kfree (spia_mtd);
145 return -ENXIO;
146 }
147
148 /* Register the partitions */
149 add_mtd_partitions(spia_mtd, partition_info, NUM_PARTITIONS);
150
151 /* Return happy */
152 return 0;
153}
154module_init(spia_init);
155
156/*
157 * Clean up routine
158 */
159#ifdef MODULE
160static void __exit spia_cleanup (void)
161{
162 /* Release resources, unregister device */
163 nand_release (spia_mtd);
164
165 /* Free the MTD device structure */
166 kfree (spia_mtd);
167}
168module_exit(spia_cleanup);
169#endif
170
171MODULE_LICENSE("GPL");
172MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com");
173MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on SPIA board");