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gerrit-public.fairphone.software / kernel / msm-4.9 / 61bb331312c5fc24f6b8dc308f6c76c4f8825847 / . / arch / arm / boot / dts / qcom / sdxpoorwills-usb.dtsi
blob: be2b63ea78aa1e3d2369ab367158dd1043e7c2f7 [file] [log] [blame]
Devdutt Patnaik4ff5bcd62017-05-05 19:45:01 -0700[diff] [blame]1/*
2 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#include <dt-bindings/clock/qcom,rpmh.h>
14#include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h>
15
16&soc {
17 /* USB port for DWC3 controller */
18 usb: ssusb@a600000 {
19 compatible = "qcom,dwc-usb3-msm";
20 reg = <0x0a600000 0xf8c00>;
21 reg-names = "core_base";
22 #address-cells = <1>;
23 #size-cells = <1>;
24 ranges;
25
26 interrupts = <0 131 0>, <0 130 0>, <0 59 0>;
27 interrupt-names = "hs_phy_irq", "pwr_event_irq", "ss_phy_irq";
28
29 USB3_GDSC-supply = <&gdsc_usb30>;
30 qcom,usb-dbm = <&dbm_1p5>;
31 qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
32 qcom,num-gsi-evt-buffs = <0x3>;
33
34 clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
35 <&clock_gcc GCC_SYS_NOC_USB3_CLK>,
36 <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,
37 <&clock_gcc GCC_USB30_SLEEP_CLK>,
38 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
39 <&clock_gcc GCC_USB3_PRIM_CLKREF_CLK>;
40
41 clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
42 "cfg_ahb_clk", "xo";
43
44 qcom,core-clk-rate = <133333333>;
45 qcom,core-clk-rate-hs = <66666667>;
46
47 resets = <&clock_gcc GCC_USB30_BCR>;
48 reset-names = "core_reset";
49
50 dwc3@a600000 {
51 compatible = "snps,dwc3";
52 reg = <0x0a600000 0xcd00>;
53 interrupt-parent = <&intc>;
54 interrupts = <0 133 0>;
55 usb-phy = <&usb2_phy>, <&usb3_qmp_phy>;
56 tx-fifo-resize;
57 linux,sysdev_is_parent;
58 snps,disable-clk-gating;
59 snps,has-lpm-erratum;
60 snps,hird-threshold = /bits/ 8 <0x10>;
61 };
62 };
63
64 /* USB port for High Speed PHY */
65 usb2_phy: hsphy@ff1000 {
66 compatible = "qcom,usb-hsphy-snps-femto";
67 reg = <0xff1000 0x400>;
68 reg-names = "hsusb_phy_base";
69
70 vdd-supply = <&pmxpoorwills_l4>;
71 vdda18-supply = <&pmxpoorwills_l5>;
72 vdda33-supply = <&pmxpoorwills_l10>;
73 qcom,vdd-voltage-level = <0 872000 872000>;
74 clocks = <&clock_rpmh RPMH_CXO_CLK>,
75 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
76 clock-names = "ref_clk_src", "cfg_ahb_clk";
77
78 resets = <&clock_gcc GCC_QUSB2PHY_BCR>;
79 reset-names = "phy_reset";
80 };
81
82 dbm_1p5: dbm@a6f8000 {
83 compatible = "qcom,usb-dbm-1p5";
84 reg = <0xa6f8000 0x400>;
85 qcom,reset-ep-after-lpm-resume;
86 };
87
88 usb_nop_phy: usb_nop_phy {
89 compatible = "usb-nop-xceiv";
90 };
91
92 /* USB port for Super Speed PHY */
93 usb3_qmp_phy: ssphy@ff0000 {
94 compatible = "qcom,usb-ssphy-qmp-v2";
95 reg = <0xff0000 0x1000>;
96 reg-names = "qmp_phy_base";
97
98 vdd-supply = <&pmxpoorwills_l4>;
99 core-supply = <&pmxpoorwills_l1>;
100 qcom,vdd-voltage-level = <0 872000 872000>;
101 qcom,vbus-valid-override;
102 qcom,qmp-phy-init-seq =
103 /* <reg_offset, value, delay> */
104 <0x048 0x07 0x00 /* QSERDES_COM_PLL_IVCO */
105 0x080 0x14 0x00 /* QSERDES_COM_SYSCLK_EN_SEL */
106 0x034 0x04 0x00 /* QSERDES_COM_BIAS_EN_CLKBUFLR_EN */
107 0x138 0x30 0x00 /* QSERDES_COM_CLK_SELECT */
108 0x03c 0x02 0x00 /* QSERDES_COM_SYS_CLK_CTRL */
109 0x08c 0x08 0x00 /* QSERDES_COM_RESETSM_CNTRL2 */
110 0x15c 0x06 0x00 /* QSERDES_COM_CMN_CONFIG */
111 0x164 0x01 0x00 /* QSERDES_COM_SVS_MODE_CLK_SEL */
112 0x13c 0x80 0x00 /* QSERDES_COM_HSCLK_SEL */
113 0x0b0 0x82 0x00 /* QSERDES_COM_DEC_START_MODE0 */
114 0x0b8 0xab 0x00 /* QSERDES_COM_DIV_FRAC_START1_MODE0 */
115 0x0bc 0xea 0x00 /* QSERDES_COM_DIV_FRAC_START2_MODE0 */
116 0x0c0 0x02 0x00 /* QSERDES_COM_DIV_FRAC_START3_MODE0 */
117 0x060 0x06 0x00 /* QSERDES_COM_CP_CTRL_MODE0 */
118 0x068 0x16 0x00 /* QSERDES_COM_PLL_RCTRL_MODE0 */
119 0x070 0x36 0x00 /* QSERDES_COM_PLL_CCTRL_MODE0 */
120 0x0dc 0x00 0x00 /* QSERDES_COM_INTEGLOOP_GAIN1_MODE0 */
121 0x0d8 0x3f 0x00 /* QSERDES_COM_INTEGLOOP_GAIN0_MODE0 */
122 0x0f8 0x01 0x00 /* QSERDES_COM_VCO_TUNE2_MODE0 */
123 0x0f4 0xc9 0x00 /* QSERDES_COM_VCO_TUNE1_MODE0 */
124 0x148 0x0a 0x00 /* QSERDES_COM_CORECLK_DIV_MODE0 */
125 0x0a0 0x00 0x00 /* QSERDES_COM_LOCK_CMP3_MODE0 */
126 0x09c 0x34 0x00 /* QSERDES_COM_LOCK_CMP2_MODE0 */
127 0x098 0x15 0x00 /* QSERDES_COM_LOCK_CMP1_MODE0 */
128 0x090 0x04 0x00 /* QSERDES_COM_LOCK_CMP_EN */
129 0x154 0x00 0x00 /* QSERDES_COM_CORE_CLK_EN */
130 0x094 0x00 0x00 /* QSERDES_COM_LOCK_CMP_CFG */
131 0x0f0 0x00 0x00 /* QSERDES_COM_VCO_TUNE_MAP */
132 0x040 0x0a 0x00 /* QSERDES_COM_SYSCLK_BUF_ENABLE */
133 0x0d0 0x80 0x00 /* QSERDES_COM_INTEGLOOP_INITVAL */
134 0x010 0x01 0x00 /* QSERDES_COM_SSC_EN_CENTER */
135 0x01c 0x31 0x00 /* QSERDES_COM_SSC_PER1 */
136 0x020 0x01 0x00 /* QSERDES_COM_SSC_PER2 */
137 0x014 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER1 */
138 0x018 0x00 0x00 /* QSERDES_COM_SSC_ADJ_PER2 */
139 0x024 0x85 0x00 /* QSERDES_COM_SSC_STEP_SIZE1 */
140 0x028 0x07 0x00 /* QSERDES_COM_SSC_STEP_SIZE2 */
141 0x4c0 0x0c 0x00 /* QSERDES_RX_VGA_CAL_CNTRL2 */
142 0x564 0x50 0x00 /* QSERDES_RX_RX_MODE_00 */
143 0x430 0x0b 0x00 /* QSERDES_RX_UCDR_FASTLOCK_FO_GAIN */
144 0x4d4 0x0e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 */
145 0x4d8 0x4e 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 */
146 0x4dc 0x18 0x00 /* QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 */
147 0x4f8 0x77 0x00 /* RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 */
148 0x4fc 0x80 0x00 /* RX_RX_OFFSET_ADAPTOR_CNTRL2 */
149 0x504 0x03 0x00 /* QSERDES_RX_SIGDET_CNTRL */
150 0x50c 0x1c 0x00 /* QSERDES_RX_SIGDET_DEGLITCH_CNTRL */
151 0x434 0x75 0x00 /* RX_UCDR_SO_SATURATION_AND_ENABLE */
152 0x444 0x80 0x00 /* QSERDES_RX_UCDR_PI_CONTROLS */
153 0x408 0x0a 0x00 /* QSERDES_RX_UCDR_FO_GAIN */
154 0x40c 0x06 0x00 /* QSERDES_RX_UCDR_SO_GAIN */
155 0x500 0x00 0x00 /* QSERDES_RX_SIGDET_ENABLES */
156 0x260 0x10 0x00 /* QSERDES_TX_HIGHZ_DRVR_EN */
157 0x2a4 0x12 0x00 /* QSERDES_TX_RCV_DETECT_LVL_2 */
158 0x28c 0xc6 0x00 /* QSERDES_TX_LANE_MODE_1 */
159 0x248 0x09 0x00 /* TX_RES_CODE_LANE_OFFSET_RX */
160 0x244 0x0d 0x00 /* TX_RES_CODE_LANE_OFFSET_TX */
161 0x8c8 0x83 0x00 /* USB3_UNI_PCS_FLL_CNTRL2 */
162 0x8cc 0x09 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_L */
163 0x8d0 0xa2 0x00 /* USB3_UNI_PCS_FLL_CNT_VAL_H_TOL */
164 0x8d4 0x40 0x00 /* USB3_UNI_PCS_FLL_MAN_CODE */
165 0x8c4 0x02 0x00 /* USB3_UNI_PCS_FLL_CNTRL1 */
166 0x864 0x1b 0x00 /* USB3_UNI_PCS_POWER_STATE_CONFIG2 */
167 0x80c 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V0 */
168 0x810 0x9f 0x00 /* USB3_UNI_PCS_TXMGN_V1 */
169 0x814 0xb5 0x00 /* USB3_UNI_PCS_TXMGN_V2 */
170 0x818 0x4c 0x00 /* USB3_UNI_PCS_TXMGN_V3 */
171 0x81c 0x64 0x00 /* USB3_UNI_PCS_TXMGN_V4 */
172 0x820 0x6a 0x00 /* USB3_UNI_PCS_TXMGN_LS */
173 0x824 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V0 */
174 0x828 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V0 */
175 0x82c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V1 */
176 0x830 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V1 */
177 0x834 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V2 */
178 0x838 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V2 */
179 0x83c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V3 */
180 0x840 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V3 */
181 0x844 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_V4 */
182 0x848 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_V4 */
183 0x84c 0x15 0x00 /* USB3_UNI_PCS_TXDEEMPH_M6DB_LS */
184 0x850 0x0d 0x00 /* USB3_UNI_PCS_TXDEEMPH_M3P5DB_LS */
185 0x85c 0x02 0x00 /* USB3_UNI_PCS_RATE_SLEW_CNTRL */
186 0x8a0 0x04 0x00 /* PCS_PWRUP_RESET_DLY_TIME_AUXCLK */
187 0x88c 0x44 0x00 /* USB3_UNI_PCS_TSYNC_RSYNC_TIME */
188 0x880 0xd1 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG1 */
189 0x884 0x1f 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG2 */
190 0x888 0x47 0x00 /* USB3_UNI_PCS_LOCK_DETECT_CONFIG3 */
191 0x870 0xe7 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L */
192 0x874 0x03 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H */
193 0x878 0x40 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_L */
194 0x87c 0x00 0x00 /* USB3_UNI_PCS_RCVR_DTCT_DLY_U3_H */
195 0x9d8 0xba 0x00 /* USB3_UNI_PCS_RX_SIGDET_LVL */
196 0x8b8 0x75 0x00 /* RXEQTRAINING_WAIT_TIME */
197 0x8b0 0x86 0x00 /* PCS_LFPS_TX_ECSTART_EQTLOCK */
198 0x8bc 0x13 0x00 /* PCS_RXEQTRAINING_RUN_TIME */
199 0xa0c 0x21 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG1 */
200 0xa10 0x60 0x00 /* USB3_UNI_PCS_REFGEN_REQ_CONFIG2 */
201 0xffffffff 0xffffffff 0x00>;
202
203 qcom,qmp-phy-reg-offset =
204 <0x974 /* USB3_UNI_PCS_PCS_STATUS */
205 0x8d8 /* USB3_UNI_PCS_AUTONOMOUS_MODE_CTRL */
206 0x8dc /* USB3_UNI_PCS_LFPS_RXTERM_IRQ_CLEAR */
207 0x804 /* USB3_UNI_PCS_POWER_DOWN_CONTROL */
208 0x800 /* USB3_UNI_PCS_SW_RESET */
209 0x808>; /* USB3_UNI_PCS_START_CONTROL */
210
211 clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,
212 <&clock_gcc GCC_USB3_PHY_PIPE_CLK>,
213 <&clock_rpmh RPMH_CXO_CLK>,
214 <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
215
216 clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
217 "cfg_ahb_clk";
218 };
219};