Vicky Wallace | aea22a0 | 2017-09-20 16:45:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "clk: %s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/module.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_device.h> |
| 23 | #include <linux/clk.h> |
| 24 | #include <linux/clk-provider.h> |
| 25 | #include <linux/regmap.h> |
| 26 | #include <linux/reset-controller.h> |
| 27 | |
| 28 | #include <dt-bindings/clock/qcom,gcc-sdxpoorwills.h> |
| 29 | |
| 30 | #include "common.h" |
| 31 | #include "clk-regmap.h" |
| 32 | #include "clk-pll.h" |
| 33 | #include "clk-rcg.h" |
| 34 | #include "clk-branch.h" |
| 35 | #include "reset.h" |
| 36 | |
| 37 | #include "clk-alpha-pll.h" |
| 38 | #include "vdd-level-sdm845.h" |
| 39 | |
| 40 | #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } |
| 41 | |
| 42 | static DEFINE_VDD_REGULATORS(vdd_cx, VDD_CX_NUM, 1, vdd_corner); |
| 43 | |
| 44 | enum { |
| 45 | P_BI_TCXO, |
| 46 | P_CORE_BI_PLL_TEST_SE, |
| 47 | P_GPLL0_OUT_EVEN, |
| 48 | P_GPLL0_OUT_MAIN, |
| 49 | P_GPLL4_OUT_EVEN, |
| 50 | P_SLEEP_CLK, |
| 51 | }; |
| 52 | |
| 53 | static const struct parent_map gcc_parent_map_0[] = { |
| 54 | { P_BI_TCXO, 0 }, |
| 55 | { P_GPLL0_OUT_MAIN, 1 }, |
| 56 | { P_GPLL0_OUT_EVEN, 6 }, |
| 57 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 58 | }; |
| 59 | |
| 60 | static const char * const gcc_parent_names_0[] = { |
| 61 | "bi_tcxo", |
| 62 | "gpll0", |
| 63 | "gpll0_out_even", |
| 64 | "core_bi_pll_test_se", |
| 65 | }; |
| 66 | |
| 67 | static const struct parent_map gcc_parent_map_1[] = { |
| 68 | { P_BI_TCXO, 0 }, |
| 69 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 70 | }; |
| 71 | |
| 72 | static const char * const gcc_parent_names_1[] = { |
| 73 | "bi_tcxo", |
| 74 | "core_bi_pll_test_se", |
| 75 | }; |
| 76 | |
| 77 | static const struct parent_map gcc_parent_map_2[] = { |
| 78 | { P_BI_TCXO, 0 }, |
| 79 | { P_GPLL0_OUT_MAIN, 1 }, |
| 80 | { P_SLEEP_CLK, 5 }, |
| 81 | { P_GPLL0_OUT_EVEN, 6 }, |
| 82 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 83 | }; |
| 84 | |
| 85 | static const char * const gcc_parent_names_2[] = { |
| 86 | "bi_tcxo", |
| 87 | "gpll0", |
| 88 | "core_pi_sleep_clk", |
| 89 | "gpll0_out_even", |
| 90 | "core_bi_pll_test_se", |
| 91 | }; |
| 92 | |
| 93 | static const struct parent_map gcc_parent_map_3[] = { |
| 94 | { P_BI_TCXO, 0 }, |
| 95 | { P_SLEEP_CLK, 5 }, |
| 96 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 97 | }; |
| 98 | |
| 99 | static const char * const gcc_parent_names_3[] = { |
| 100 | "bi_tcxo", |
| 101 | "core_pi_sleep_clk", |
| 102 | "core_bi_pll_test_se", |
| 103 | }; |
| 104 | |
| 105 | static const struct parent_map gcc_parent_map_4[] = { |
| 106 | { P_BI_TCXO, 0 }, |
| 107 | { P_GPLL0_OUT_MAIN, 1 }, |
| 108 | { P_GPLL4_OUT_EVEN, 2 }, |
| 109 | { P_GPLL0_OUT_EVEN, 6 }, |
| 110 | { P_CORE_BI_PLL_TEST_SE, 7 }, |
| 111 | }; |
| 112 | |
| 113 | static const char * const gcc_parent_names_4[] = { |
| 114 | "bi_tcxo", |
| 115 | "gpll0", |
| 116 | "gpll4_out_even", |
| 117 | "gpll0_out_even", |
| 118 | "core_bi_pll_test_se", |
| 119 | }; |
| 120 | |
| 121 | static struct pll_vco trion_vco[] = { |
| 122 | { 249600000, 2000000000, 0 }, |
| 123 | }; |
| 124 | |
| 125 | static struct clk_alpha_pll gpll0 = { |
| 126 | .offset = 0x0, |
| 127 | .vco_table = trion_vco, |
| 128 | .num_vco = ARRAY_SIZE(trion_vco), |
| 129 | .type = TRION_PLL, |
| 130 | .clkr = { |
| 131 | .enable_reg = 0x6d000, |
| 132 | .enable_mask = BIT(0), |
| 133 | .hw.init = &(struct clk_init_data){ |
| 134 | .name = "gpll0", |
| 135 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 136 | .num_parents = 1, |
| 137 | .ops = &clk_trion_fixed_pll_ops, |
| 138 | VDD_CX_FMAX_MAP4( |
| 139 | MIN, 615000000, |
| 140 | LOW, 1066000000, |
| 141 | LOW_L1, 1600000000, |
| 142 | NOMINAL, 2000000000), |
| 143 | }, |
| 144 | }, |
| 145 | }; |
| 146 | |
| 147 | static const struct clk_div_table post_div_table_trion_even[] = { |
| 148 | { 0x0, 1 }, |
| 149 | { 0x1, 2 }, |
| 150 | { 0x3, 4 }, |
| 151 | { 0x7, 8 }, |
| 152 | { } |
| 153 | }; |
| 154 | |
| 155 | static struct clk_alpha_pll_postdiv gpll0_out_even = { |
| 156 | .offset = 0x0, |
| 157 | .post_div_shift = 8, |
| 158 | .post_div_table = post_div_table_trion_even, |
| 159 | .num_post_div = ARRAY_SIZE(post_div_table_trion_even), |
| 160 | .width = 4, |
| 161 | .clkr.hw.init = &(struct clk_init_data){ |
| 162 | .name = "gpll0_out_even", |
| 163 | .parent_names = (const char *[]){ "gpll0" }, |
| 164 | .num_parents = 1, |
| 165 | .ops = &clk_trion_pll_postdiv_ops, |
| 166 | }, |
| 167 | }; |
| 168 | |
| 169 | static struct clk_alpha_pll gpll4 = { |
| 170 | .offset = 0x76000, |
| 171 | .vco_table = trion_vco, |
| 172 | .num_vco = ARRAY_SIZE(trion_vco), |
| 173 | .type = TRION_PLL, |
| 174 | .clkr = { |
| 175 | .enable_reg = 0x6d000, |
| 176 | .enable_mask = BIT(4), |
| 177 | .hw.init = &(struct clk_init_data){ |
| 178 | .name = "gpll4", |
| 179 | .parent_names = (const char *[]){ "bi_tcxo" }, |
| 180 | .num_parents = 1, |
| 181 | .ops = &clk_trion_fixed_pll_ops, |
| 182 | VDD_CX_FMAX_MAP4( |
| 183 | MIN, 615000000, |
| 184 | LOW, 1066000000, |
| 185 | LOW_L1, 1600000000, |
| 186 | NOMINAL, 2000000000), |
| 187 | }, |
| 188 | }, |
| 189 | }; |
| 190 | |
| 191 | static struct clk_alpha_pll_postdiv gpll4_out_even = { |
| 192 | .offset = 0x76000, |
| 193 | .post_div_shift = 8, |
| 194 | .post_div_table = post_div_table_trion_even, |
| 195 | .num_post_div = ARRAY_SIZE(post_div_table_trion_even), |
| 196 | .width = 4, |
| 197 | .clkr.hw.init = &(struct clk_init_data){ |
| 198 | .name = "gpll4_out_even", |
| 199 | .parent_names = (const char *[]){ "gpll4" }, |
| 200 | .num_parents = 1, |
| 201 | .ops = &clk_trion_pll_postdiv_ops, |
| 202 | }, |
| 203 | }; |
| 204 | |
| 205 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_i2c_apps_clk_src[] = { |
| 206 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 207 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 208 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 209 | { } |
| 210 | }; |
| 211 | |
| 212 | static struct clk_rcg2 gcc_blsp1_qup1_i2c_apps_clk_src = { |
| 213 | .cmd_rcgr = 0x11024, |
| 214 | .mnd_width = 8, |
| 215 | .hid_width = 5, |
| 216 | .parent_map = gcc_parent_map_0, |
| 217 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 218 | .clkr.hw.init = &(struct clk_init_data){ |
| 219 | .name = "gcc_blsp1_qup1_i2c_apps_clk_src", |
| 220 | .parent_names = gcc_parent_names_0, |
| 221 | .num_parents = 4, |
| 222 | .flags = CLK_SET_RATE_PARENT, |
| 223 | .ops = &clk_rcg2_ops, |
| 224 | VDD_CX_FMAX_MAP3( |
| 225 | MIN, 9600000, |
| 226 | LOWER, 19200000, |
| 227 | LOW, 50000000), |
| 228 | }, |
| 229 | }; |
| 230 | |
| 231 | static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = { |
| 232 | F(960000, P_BI_TCXO, 10, 1, 2), |
| 233 | F(4800000, P_BI_TCXO, 4, 0, 0), |
| 234 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 235 | F(15000000, P_GPLL0_OUT_EVEN, 5, 1, 4), |
| 236 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 237 | F(24000000, P_GPLL0_OUT_MAIN, 12.5, 1, 2), |
| 238 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
| 239 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 240 | { } |
| 241 | }; |
| 242 | |
| 243 | static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = { |
| 244 | .cmd_rcgr = 0x1100c, |
| 245 | .mnd_width = 8, |
| 246 | .hid_width = 5, |
| 247 | .parent_map = gcc_parent_map_0, |
| 248 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 249 | .clkr.hw.init = &(struct clk_init_data){ |
| 250 | .name = "gcc_blsp1_qup1_spi_apps_clk_src", |
| 251 | .parent_names = gcc_parent_names_0, |
| 252 | .num_parents = 4, |
| 253 | .flags = CLK_SET_RATE_PARENT, |
| 254 | .ops = &clk_rcg2_ops, |
| 255 | VDD_CX_FMAX_MAP4( |
| 256 | MIN, 9600000, |
| 257 | LOWER, 19200000, |
| 258 | LOW, 25000000, |
| 259 | NOMINAL, 50000000), |
| 260 | }, |
| 261 | }; |
| 262 | |
| 263 | static struct clk_rcg2 gcc_blsp1_qup2_i2c_apps_clk_src = { |
| 264 | .cmd_rcgr = 0x13024, |
| 265 | .mnd_width = 8, |
| 266 | .hid_width = 5, |
| 267 | .parent_map = gcc_parent_map_0, |
| 268 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 269 | .clkr.hw.init = &(struct clk_init_data){ |
| 270 | .name = "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 271 | .parent_names = gcc_parent_names_0, |
| 272 | .num_parents = 4, |
| 273 | .flags = CLK_SET_RATE_PARENT, |
| 274 | .ops = &clk_rcg2_ops, |
| 275 | VDD_CX_FMAX_MAP3( |
| 276 | MIN, 9600000, |
| 277 | LOWER, 19200000, |
| 278 | LOW, 50000000), |
| 279 | }, |
| 280 | }; |
| 281 | |
| 282 | static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = { |
| 283 | .cmd_rcgr = 0x1300c, |
| 284 | .mnd_width = 8, |
| 285 | .hid_width = 5, |
| 286 | .parent_map = gcc_parent_map_0, |
| 287 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 288 | .clkr.hw.init = &(struct clk_init_data){ |
| 289 | .name = "gcc_blsp1_qup2_spi_apps_clk_src", |
| 290 | .parent_names = gcc_parent_names_0, |
| 291 | .num_parents = 4, |
| 292 | .flags = CLK_SET_RATE_PARENT, |
| 293 | .ops = &clk_rcg2_ops, |
| 294 | VDD_CX_FMAX_MAP4( |
| 295 | MIN, 9600000, |
| 296 | LOWER, 19200000, |
| 297 | LOW, 25000000, |
| 298 | NOMINAL, 50000000), |
| 299 | }, |
| 300 | }; |
| 301 | |
| 302 | static struct clk_rcg2 gcc_blsp1_qup3_i2c_apps_clk_src = { |
| 303 | .cmd_rcgr = 0x15024, |
| 304 | .mnd_width = 8, |
| 305 | .hid_width = 5, |
| 306 | .parent_map = gcc_parent_map_0, |
| 307 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 308 | .clkr.hw.init = &(struct clk_init_data){ |
| 309 | .name = "gcc_blsp1_qup3_i2c_apps_clk_src", |
| 310 | .parent_names = gcc_parent_names_0, |
| 311 | .num_parents = 4, |
| 312 | .flags = CLK_SET_RATE_PARENT, |
| 313 | .ops = &clk_rcg2_ops, |
| 314 | VDD_CX_FMAX_MAP3( |
| 315 | MIN, 9600000, |
| 316 | LOWER, 19200000, |
| 317 | LOW, 50000000), |
| 318 | }, |
| 319 | }; |
| 320 | |
| 321 | static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = { |
| 322 | .cmd_rcgr = 0x1500c, |
| 323 | .mnd_width = 8, |
| 324 | .hid_width = 5, |
| 325 | .parent_map = gcc_parent_map_0, |
| 326 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 327 | .clkr.hw.init = &(struct clk_init_data){ |
| 328 | .name = "gcc_blsp1_qup3_spi_apps_clk_src", |
| 329 | .parent_names = gcc_parent_names_0, |
| 330 | .num_parents = 4, |
| 331 | .flags = CLK_SET_RATE_PARENT, |
| 332 | .ops = &clk_rcg2_ops, |
| 333 | VDD_CX_FMAX_MAP4( |
| 334 | MIN, 9600000, |
| 335 | LOWER, 19200000, |
| 336 | LOW, 25000000, |
| 337 | NOMINAL, 50000000), |
| 338 | }, |
| 339 | }; |
| 340 | |
| 341 | static struct clk_rcg2 gcc_blsp1_qup4_i2c_apps_clk_src = { |
| 342 | .cmd_rcgr = 0x17024, |
| 343 | .mnd_width = 8, |
| 344 | .hid_width = 5, |
| 345 | .parent_map = gcc_parent_map_0, |
| 346 | .freq_tbl = ftbl_gcc_blsp1_qup1_i2c_apps_clk_src, |
| 347 | .clkr.hw.init = &(struct clk_init_data){ |
| 348 | .name = "gcc_blsp1_qup4_i2c_apps_clk_src", |
| 349 | .parent_names = gcc_parent_names_0, |
| 350 | .num_parents = 4, |
| 351 | .flags = CLK_SET_RATE_PARENT, |
| 352 | .ops = &clk_rcg2_ops, |
| 353 | VDD_CX_FMAX_MAP3( |
| 354 | MIN, 9600000, |
| 355 | LOWER, 19200000, |
| 356 | LOW, 50000000), |
| 357 | }, |
| 358 | }; |
| 359 | |
| 360 | static struct clk_rcg2 gcc_blsp1_qup4_spi_apps_clk_src = { |
| 361 | .cmd_rcgr = 0x1700c, |
| 362 | .mnd_width = 8, |
| 363 | .hid_width = 5, |
| 364 | .parent_map = gcc_parent_map_0, |
| 365 | .freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src, |
| 366 | .clkr.hw.init = &(struct clk_init_data){ |
| 367 | .name = "gcc_blsp1_qup4_spi_apps_clk_src", |
| 368 | .parent_names = gcc_parent_names_0, |
| 369 | .num_parents = 4, |
| 370 | .flags = CLK_SET_RATE_PARENT, |
| 371 | .ops = &clk_rcg2_ops, |
| 372 | VDD_CX_FMAX_MAP4( |
| 373 | MIN, 9600000, |
| 374 | LOWER, 19200000, |
| 375 | LOW, 25000000, |
| 376 | NOMINAL, 50000000), |
| 377 | }, |
| 378 | }; |
| 379 | |
| 380 | static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = { |
| 381 | F(3686400, P_GPLL0_OUT_EVEN, 1, 192, 15625), |
| 382 | F(7372800, P_GPLL0_OUT_EVEN, 1, 384, 15625), |
| 383 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 384 | F(14745600, P_GPLL0_OUT_EVEN, 1, 768, 15625), |
| 385 | F(16000000, P_GPLL0_OUT_EVEN, 1, 4, 75), |
| 386 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 387 | F(19354839, P_GPLL0_OUT_MAIN, 15.5, 1, 2), |
| 388 | F(20000000, P_GPLL0_OUT_MAIN, 15, 1, 2), |
| 389 | F(20689655, P_GPLL0_OUT_MAIN, 14.5, 1, 2), |
| 390 | F(21428571, P_GPLL0_OUT_MAIN, 14, 1, 2), |
| 391 | F(22222222, P_GPLL0_OUT_MAIN, 13.5, 1, 2), |
| 392 | F(23076923, P_GPLL0_OUT_MAIN, 13, 1, 2), |
| 393 | F(24000000, P_GPLL0_OUT_MAIN, 5, 1, 5), |
| 394 | F(25000000, P_GPLL0_OUT_MAIN, 12, 1, 2), |
| 395 | F(26086957, P_GPLL0_OUT_MAIN, 11.5, 1, 2), |
| 396 | F(27272727, P_GPLL0_OUT_MAIN, 11, 1, 2), |
| 397 | F(28571429, P_GPLL0_OUT_MAIN, 10.5, 1, 2), |
| 398 | F(32000000, P_GPLL0_OUT_MAIN, 1, 4, 75), |
| 399 | F(40000000, P_GPLL0_OUT_MAIN, 15, 0, 0), |
| 400 | F(46400000, P_GPLL0_OUT_MAIN, 1, 29, 375), |
| 401 | F(48000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0), |
| 402 | F(51200000, P_GPLL0_OUT_MAIN, 1, 32, 375), |
| 403 | F(56000000, P_GPLL0_OUT_MAIN, 1, 7, 75), |
| 404 | F(58982400, P_GPLL0_OUT_MAIN, 1, 1536, 15625), |
| 405 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 406 | F(63157895, P_GPLL0_OUT_MAIN, 9.5, 0, 0), |
| 407 | { } |
| 408 | }; |
| 409 | |
| 410 | |
| 411 | static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = { |
| 412 | .cmd_rcgr = 0x1200c, |
| 413 | .mnd_width = 16, |
| 414 | .hid_width = 5, |
| 415 | .parent_map = gcc_parent_map_0, |
| 416 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 417 | .clkr.hw.init = &(struct clk_init_data){ |
| 418 | .name = "gcc_blsp1_uart1_apps_clk_src", |
| 419 | .parent_names = gcc_parent_names_0, |
| 420 | .num_parents = 4, |
| 421 | .flags = CLK_SET_RATE_PARENT, |
| 422 | .ops = &clk_rcg2_ops, |
| 423 | VDD_CX_FMAX_MAP4( |
| 424 | MIN, 9600000, |
| 425 | LOWER, 19200000, |
| 426 | LOW, 48000000, |
| 427 | NOMINAL, 63157895), |
| 428 | }, |
| 429 | }; |
| 430 | |
| 431 | static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = { |
| 432 | .cmd_rcgr = 0x1400c, |
| 433 | .mnd_width = 16, |
| 434 | .hid_width = 5, |
| 435 | .parent_map = gcc_parent_map_0, |
| 436 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 437 | .clkr.hw.init = &(struct clk_init_data){ |
| 438 | .name = "gcc_blsp1_uart2_apps_clk_src", |
| 439 | .parent_names = gcc_parent_names_0, |
| 440 | .num_parents = 4, |
| 441 | .flags = CLK_SET_RATE_PARENT, |
| 442 | .ops = &clk_rcg2_ops, |
| 443 | VDD_CX_FMAX_MAP4( |
| 444 | MIN, 9600000, |
| 445 | LOWER, 19200000, |
| 446 | LOW, 48000000, |
| 447 | NOMINAL, 63157895), |
| 448 | }, |
| 449 | }; |
| 450 | |
| 451 | static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = { |
| 452 | .cmd_rcgr = 0x1600c, |
| 453 | .mnd_width = 16, |
| 454 | .hid_width = 5, |
| 455 | .parent_map = gcc_parent_map_0, |
| 456 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 457 | .clkr.hw.init = &(struct clk_init_data){ |
| 458 | .name = "gcc_blsp1_uart3_apps_clk_src", |
| 459 | .parent_names = gcc_parent_names_0, |
| 460 | .num_parents = 4, |
| 461 | .flags = CLK_SET_RATE_PARENT, |
| 462 | .ops = &clk_rcg2_ops, |
| 463 | VDD_CX_FMAX_MAP4( |
| 464 | MIN, 9600000, |
| 465 | LOWER, 19200000, |
| 466 | LOW, 48000000, |
| 467 | NOMINAL, 63157895), |
| 468 | }, |
| 469 | }; |
| 470 | |
| 471 | static struct clk_rcg2 gcc_blsp1_uart4_apps_clk_src = { |
| 472 | .cmd_rcgr = 0x1800c, |
| 473 | .mnd_width = 16, |
| 474 | .hid_width = 5, |
| 475 | .parent_map = gcc_parent_map_0, |
| 476 | .freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src, |
| 477 | .clkr.hw.init = &(struct clk_init_data){ |
| 478 | .name = "gcc_blsp1_uart4_apps_clk_src", |
| 479 | .parent_names = gcc_parent_names_0, |
| 480 | .num_parents = 4, |
| 481 | .flags = CLK_SET_RATE_PARENT, |
| 482 | .ops = &clk_rcg2_ops, |
| 483 | VDD_CX_FMAX_MAP4( |
| 484 | MIN, 9600000, |
| 485 | LOWER, 19200000, |
| 486 | LOW, 48000000, |
| 487 | NOMINAL, 63157895), |
| 488 | }, |
| 489 | }; |
| 490 | |
| 491 | static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { |
| 492 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 493 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 494 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 495 | F(133333333, P_GPLL0_OUT_MAIN, 4.5, 0, 0), |
| 496 | { } |
| 497 | }; |
| 498 | |
| 499 | static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { |
| 500 | .cmd_rcgr = 0x24010, |
| 501 | .mnd_width = 0, |
| 502 | .hid_width = 5, |
| 503 | .parent_map = gcc_parent_map_0, |
| 504 | .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, |
| 505 | .clkr.hw.init = &(struct clk_init_data){ |
| 506 | .name = "gcc_cpuss_ahb_clk_src", |
| 507 | .parent_names = gcc_parent_names_0, |
| 508 | .num_parents = 4, |
| 509 | .flags = CLK_SET_RATE_PARENT, |
| 510 | .ops = &clk_rcg2_ops, |
| 511 | VDD_CX_FMAX_MAP4( |
| 512 | MIN, 19200000, |
| 513 | LOWER, 50000000, |
| 514 | NOMINAL, 100000000, |
| 515 | HIGH, 133333333), |
| 516 | }, |
| 517 | }; |
| 518 | |
| 519 | static const struct freq_tbl ftbl_gcc_cpuss_rbcpr_clk_src[] = { |
| 520 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 521 | F(50000000, P_GPLL0_OUT_MAIN, 12, 0, 0), |
| 522 | { } |
| 523 | }; |
| 524 | |
| 525 | static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { |
| 526 | .cmd_rcgr = 0x2402c, |
| 527 | .mnd_width = 0, |
| 528 | .hid_width = 5, |
| 529 | .parent_map = gcc_parent_map_0, |
| 530 | .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| 531 | .clkr.hw.init = &(struct clk_init_data){ |
| 532 | .name = "gcc_cpuss_rbcpr_clk_src", |
| 533 | .parent_names = gcc_parent_names_0, |
| 534 | .num_parents = 4, |
| 535 | .flags = CLK_SET_RATE_PARENT, |
| 536 | .ops = &clk_rcg2_ops, |
| 537 | VDD_CX_FMAX_MAP2( |
| 538 | MIN, 19200000, |
| 539 | NOMINAL, 50000000), |
| 540 | }, |
| 541 | }; |
| 542 | |
| 543 | static const struct freq_tbl ftbl_gcc_emac_clk_src[] = { |
| 544 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 545 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 546 | F(125000000, P_GPLL4_OUT_EVEN, 4, 0, 0), |
| 547 | F(250000000, P_GPLL4_OUT_EVEN, 2, 0, 0), |
| 548 | { } |
| 549 | }; |
| 550 | |
| 551 | static struct clk_rcg2 gcc_emac_clk_src = { |
| 552 | .cmd_rcgr = 0x47020, |
| 553 | .mnd_width = 8, |
| 554 | .hid_width = 5, |
| 555 | .parent_map = gcc_parent_map_4, |
| 556 | .freq_tbl = ftbl_gcc_emac_clk_src, |
| 557 | .clkr.hw.init = &(struct clk_init_data){ |
| 558 | .name = "gcc_emac_clk_src", |
| 559 | .parent_names = gcc_parent_names_4, |
| 560 | .num_parents = 5, |
| 561 | .flags = CLK_SET_RATE_PARENT, |
| 562 | .ops = &clk_rcg2_ops, |
| 563 | VDD_CX_FMAX_MAP4( |
| 564 | MIN, 19200000, |
| 565 | LOWER, 50000000, |
| 566 | LOW, 125000000, |
| 567 | NOMINAL, 250000000), |
| 568 | }, |
| 569 | }; |
| 570 | |
| 571 | static struct clk_rcg2 gcc_emac_ptp_clk_src = { |
| 572 | .cmd_rcgr = 0x47038, |
| 573 | .mnd_width = 0, |
| 574 | .hid_width = 5, |
| 575 | .parent_map = gcc_parent_map_4, |
| 576 | .freq_tbl = ftbl_gcc_emac_clk_src, |
| 577 | .clkr.hw.init = &(struct clk_init_data){ |
| 578 | .name = "gcc_emac_ptp_clk_src", |
| 579 | .parent_names = gcc_parent_names_4, |
| 580 | .num_parents = 5, |
| 581 | .flags = CLK_SET_RATE_PARENT, |
| 582 | .ops = &clk_rcg2_ops, |
| 583 | VDD_CX_FMAX_MAP4( |
| 584 | MIN, 19200000, |
| 585 | LOWER, 50000000, |
| 586 | LOW, 125000000, |
| 587 | NOMINAL, 250000000), |
| 588 | }, |
| 589 | }; |
| 590 | |
| 591 | static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { |
| 592 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 593 | F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0), |
| 594 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 595 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 596 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 597 | { } |
| 598 | }; |
| 599 | |
| 600 | static struct clk_rcg2 gcc_gp1_clk_src = { |
| 601 | .cmd_rcgr = 0x2b004, |
| 602 | .mnd_width = 8, |
| 603 | .hid_width = 5, |
| 604 | .parent_map = gcc_parent_map_2, |
| 605 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 606 | .clkr.hw.init = &(struct clk_init_data){ |
| 607 | .name = "gcc_gp1_clk_src", |
| 608 | .parent_names = gcc_parent_names_2, |
| 609 | .num_parents = 5, |
| 610 | .flags = CLK_SET_RATE_PARENT, |
| 611 | .ops = &clk_rcg2_ops, |
| 612 | VDD_CX_FMAX_MAP4( |
| 613 | MIN, 19200000, |
| 614 | LOWER, 50000000, |
| 615 | LOW, 100000000, |
| 616 | NOMINAL, 200000000), |
| 617 | }, |
| 618 | }; |
| 619 | |
| 620 | static struct clk_rcg2 gcc_gp2_clk_src = { |
| 621 | .cmd_rcgr = 0x2c004, |
| 622 | .mnd_width = 8, |
| 623 | .hid_width = 5, |
| 624 | .parent_map = gcc_parent_map_2, |
| 625 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 626 | .clkr.hw.init = &(struct clk_init_data){ |
| 627 | .name = "gcc_gp2_clk_src", |
| 628 | .parent_names = gcc_parent_names_2, |
| 629 | .num_parents = 5, |
| 630 | .flags = CLK_SET_RATE_PARENT, |
| 631 | .ops = &clk_rcg2_ops, |
| 632 | VDD_CX_FMAX_MAP4( |
| 633 | MIN, 19200000, |
| 634 | LOWER, 50000000, |
| 635 | LOW, 100000000, |
| 636 | NOMINAL, 200000000), |
| 637 | }, |
| 638 | }; |
| 639 | |
| 640 | static struct clk_rcg2 gcc_gp3_clk_src = { |
| 641 | .cmd_rcgr = 0x2d004, |
| 642 | .mnd_width = 8, |
| 643 | .hid_width = 5, |
| 644 | .parent_map = gcc_parent_map_2, |
| 645 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 646 | .clkr.hw.init = &(struct clk_init_data){ |
| 647 | .name = "gcc_gp3_clk_src", |
| 648 | .parent_names = gcc_parent_names_2, |
| 649 | .num_parents = 5, |
| 650 | .flags = CLK_SET_RATE_PARENT, |
| 651 | .ops = &clk_rcg2_ops, |
| 652 | VDD_CX_FMAX_MAP4( |
| 653 | MIN, 19200000, |
| 654 | LOWER, 50000000, |
| 655 | LOW, 100000000, |
| 656 | NOMINAL, 200000000), |
| 657 | }, |
| 658 | }; |
| 659 | |
| 660 | static const struct freq_tbl ftbl_gcc_pcie_aux_phy_clk_src[] = { |
| 661 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 662 | { } |
| 663 | }; |
| 664 | |
| 665 | static struct clk_rcg2 gcc_pcie_aux_phy_clk_src = { |
| 666 | .cmd_rcgr = 0x37030, |
| 667 | .mnd_width = 16, |
| 668 | .hid_width = 5, |
| 669 | .parent_map = gcc_parent_map_3, |
| 670 | .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src, |
| 671 | .clkr.hw.init = &(struct clk_init_data){ |
| 672 | .name = "gcc_pcie_aux_phy_clk_src", |
| 673 | .parent_names = gcc_parent_names_3, |
| 674 | .num_parents = 3, |
| 675 | .flags = CLK_SET_RATE_PARENT, |
| 676 | .ops = &clk_rcg2_ops, |
| 677 | VDD_CX_FMAX_MAP1( |
| 678 | MIN, 19200000), |
| 679 | }, |
| 680 | }; |
| 681 | |
| 682 | static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { |
| 683 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 684 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 685 | { } |
| 686 | }; |
| 687 | |
| 688 | static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { |
| 689 | .cmd_rcgr = 0x39010, |
| 690 | .mnd_width = 0, |
| 691 | .hid_width = 5, |
| 692 | .parent_map = gcc_parent_map_0, |
| 693 | .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, |
| 694 | .clkr.hw.init = &(struct clk_init_data){ |
| 695 | .name = "gcc_pcie_phy_refgen_clk_src", |
| 696 | .parent_names = gcc_parent_names_0, |
| 697 | .num_parents = 4, |
| 698 | .flags = CLK_SET_RATE_PARENT, |
| 699 | .ops = &clk_rcg2_ops, |
| 700 | VDD_CX_FMAX_MAP2( |
| 701 | MIN, 19200000, |
| 702 | LOW, 100000000), |
| 703 | }, |
| 704 | }; |
| 705 | |
| 706 | static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { |
| 707 | F(9600000, P_BI_TCXO, 2, 0, 0), |
| 708 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 709 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 710 | { } |
| 711 | }; |
| 712 | |
| 713 | static struct clk_rcg2 gcc_pdm2_clk_src = { |
| 714 | .cmd_rcgr = 0x19010, |
| 715 | .mnd_width = 0, |
| 716 | .hid_width = 5, |
| 717 | .parent_map = gcc_parent_map_0, |
| 718 | .freq_tbl = ftbl_gcc_pdm2_clk_src, |
| 719 | .clkr.hw.init = &(struct clk_init_data){ |
| 720 | .name = "gcc_pdm2_clk_src", |
| 721 | .parent_names = gcc_parent_names_0, |
| 722 | .num_parents = 4, |
| 723 | .flags = CLK_SET_RATE_PARENT, |
| 724 | .ops = &clk_rcg2_ops, |
| 725 | VDD_CX_FMAX_MAP3( |
| 726 | MIN, 9600000, |
| 727 | LOWER, 19200000, |
| 728 | LOW, 60000000), |
| 729 | }, |
| 730 | }; |
| 731 | |
| 732 | static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { |
| 733 | .cmd_rcgr = 0xf00c, |
| 734 | .mnd_width = 8, |
| 735 | .hid_width = 5, |
| 736 | .parent_map = gcc_parent_map_0, |
| 737 | .freq_tbl = ftbl_gcc_gp1_clk_src, |
| 738 | .clkr.hw.init = &(struct clk_init_data){ |
| 739 | .name = "gcc_sdcc1_apps_clk_src", |
| 740 | .parent_names = gcc_parent_names_0, |
| 741 | .num_parents = 4, |
| 742 | .flags = CLK_SET_RATE_PARENT, |
| 743 | .ops = &clk_rcg2_ops, |
| 744 | VDD_CX_FMAX_MAP4( |
| 745 | MIN, 19200000, |
| 746 | LOWER, 50000000, |
| 747 | LOW, 100000000, |
| 748 | NOMINAL, 200000000), |
| 749 | }, |
| 750 | }; |
| 751 | |
| 752 | static struct clk_rcg2 gcc_spmi_fetcher_clk_src = { |
| 753 | .cmd_rcgr = 0x3f00c, |
| 754 | .mnd_width = 0, |
| 755 | .hid_width = 5, |
| 756 | .parent_map = gcc_parent_map_1, |
| 757 | .freq_tbl = ftbl_gcc_pcie_aux_phy_clk_src, |
| 758 | .clkr.hw.init = &(struct clk_init_data){ |
| 759 | .name = "gcc_spmi_fetcher_clk_src", |
| 760 | .parent_names = gcc_parent_names_1, |
| 761 | .num_parents = 2, |
| 762 | .flags = CLK_SET_RATE_PARENT, |
| 763 | .ops = &clk_rcg2_ops, |
| 764 | VDD_CX_FMAX_MAP1( |
| 765 | MIN, 19200000), |
| 766 | }, |
| 767 | }; |
| 768 | |
| 769 | static const struct freq_tbl ftbl_gcc_usb30_master_clk_src[] = { |
| 770 | F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0), |
| 771 | F(75000000, P_GPLL0_OUT_EVEN, 4, 0, 0), |
| 772 | F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0), |
| 773 | F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0), |
| 774 | F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), |
| 775 | { } |
| 776 | }; |
| 777 | |
| 778 | static struct clk_rcg2 gcc_usb30_master_clk_src = { |
| 779 | .cmd_rcgr = 0xb01c, |
| 780 | .mnd_width = 8, |
| 781 | .hid_width = 5, |
| 782 | .parent_map = gcc_parent_map_0, |
| 783 | .freq_tbl = ftbl_gcc_usb30_master_clk_src, |
| 784 | .clkr.hw.init = &(struct clk_init_data){ |
| 785 | .name = "gcc_usb30_master_clk_src", |
| 786 | .parent_names = gcc_parent_names_0, |
| 787 | .num_parents = 4, |
| 788 | .flags = CLK_SET_RATE_PARENT, |
| 789 | .ops = &clk_rcg2_ops, |
| 790 | VDD_CX_FMAX_MAP5( |
| 791 | MIN, 50000000, |
| 792 | LOWER, 75000000, |
| 793 | LOW, 100000000, |
| 794 | NOMINAL, 200000000, |
| 795 | HIGH, 240000000), |
| 796 | }, |
| 797 | }; |
| 798 | |
| 799 | static const struct freq_tbl ftbl_gcc_usb30_mock_utmi_clk_src[] = { |
| 800 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 801 | F(40000000, P_GPLL0_OUT_EVEN, 7.5, 0, 0), |
| 802 | F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0), |
| 803 | { } |
| 804 | }; |
| 805 | |
| 806 | static struct clk_rcg2 gcc_usb30_mock_utmi_clk_src = { |
| 807 | .cmd_rcgr = 0xb034, |
| 808 | .mnd_width = 0, |
| 809 | .hid_width = 5, |
| 810 | .parent_map = gcc_parent_map_0, |
| 811 | .freq_tbl = ftbl_gcc_usb30_mock_utmi_clk_src, |
| 812 | .clkr.hw.init = &(struct clk_init_data){ |
| 813 | .name = "gcc_usb30_mock_utmi_clk_src", |
| 814 | .parent_names = gcc_parent_names_0, |
| 815 | .num_parents = 4, |
| 816 | .flags = CLK_SET_RATE_PARENT, |
| 817 | .ops = &clk_rcg2_ops, |
| 818 | VDD_CX_FMAX_MAP3( |
| 819 | MIN, 19200000, |
| 820 | LOWER, 40000000, |
| 821 | LOW, 60000000), |
| 822 | }, |
| 823 | }; |
| 824 | |
| 825 | static const struct freq_tbl ftbl_gcc_usb3_phy_aux_clk_src[] = { |
| 826 | F(1000000, P_BI_TCXO, 1, 5, 96), |
| 827 | F(19200000, P_BI_TCXO, 1, 0, 0), |
| 828 | { } |
| 829 | }; |
| 830 | |
| 831 | static struct clk_rcg2 gcc_usb3_phy_aux_clk_src = { |
| 832 | .cmd_rcgr = 0xb05c, |
| 833 | .mnd_width = 16, |
| 834 | .hid_width = 5, |
| 835 | .parent_map = gcc_parent_map_3, |
| 836 | .freq_tbl = ftbl_gcc_usb3_phy_aux_clk_src, |
| 837 | .clkr.hw.init = &(struct clk_init_data){ |
| 838 | .name = "gcc_usb3_phy_aux_clk_src", |
| 839 | .parent_names = gcc_parent_names_3, |
| 840 | .num_parents = 3, |
| 841 | .flags = CLK_SET_RATE_PARENT, |
| 842 | .ops = &clk_rcg2_ops, |
| 843 | VDD_CX_FMAX_MAP1( |
| 844 | MIN, 19200000), |
| 845 | }, |
| 846 | }; |
| 847 | |
| 848 | static struct clk_branch gcc_blsp1_ahb_clk = { |
| 849 | .halt_reg = 0x10004, |
| 850 | .halt_check = BRANCH_HALT_VOTED, |
| 851 | .clkr = { |
| 852 | .enable_reg = 0x6d004, |
| 853 | .enable_mask = BIT(25), |
| 854 | .hw.init = &(struct clk_init_data){ |
| 855 | .name = "gcc_blsp1_ahb_clk", |
| 856 | .ops = &clk_branch2_ops, |
| 857 | }, |
| 858 | }, |
| 859 | }; |
| 860 | |
| 861 | static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { |
| 862 | .halt_reg = 0x11008, |
| 863 | .halt_check = BRANCH_HALT, |
| 864 | .clkr = { |
| 865 | .enable_reg = 0x11008, |
| 866 | .enable_mask = BIT(0), |
| 867 | .hw.init = &(struct clk_init_data){ |
| 868 | .name = "gcc_blsp1_qup1_i2c_apps_clk", |
| 869 | .parent_names = (const char *[]){ |
| 870 | "gcc_blsp1_qup1_i2c_apps_clk_src", |
| 871 | }, |
| 872 | .num_parents = 1, |
| 873 | .flags = CLK_SET_RATE_PARENT, |
| 874 | .ops = &clk_branch2_ops, |
| 875 | }, |
| 876 | }, |
| 877 | }; |
| 878 | |
| 879 | static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { |
| 880 | .halt_reg = 0x11004, |
| 881 | .halt_check = BRANCH_HALT, |
| 882 | .clkr = { |
| 883 | .enable_reg = 0x11004, |
| 884 | .enable_mask = BIT(0), |
| 885 | .hw.init = &(struct clk_init_data){ |
| 886 | .name = "gcc_blsp1_qup1_spi_apps_clk", |
| 887 | .parent_names = (const char *[]){ |
| 888 | "gcc_blsp1_qup1_spi_apps_clk_src", |
| 889 | }, |
| 890 | .num_parents = 1, |
| 891 | .flags = CLK_SET_RATE_PARENT, |
| 892 | .ops = &clk_branch2_ops, |
| 893 | }, |
| 894 | }, |
| 895 | }; |
| 896 | |
| 897 | static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { |
| 898 | .halt_reg = 0x13008, |
| 899 | .halt_check = BRANCH_HALT, |
| 900 | .clkr = { |
| 901 | .enable_reg = 0x13008, |
| 902 | .enable_mask = BIT(0), |
| 903 | .hw.init = &(struct clk_init_data){ |
| 904 | .name = "gcc_blsp1_qup2_i2c_apps_clk", |
| 905 | .parent_names = (const char *[]){ |
| 906 | "gcc_blsp1_qup2_i2c_apps_clk_src", |
| 907 | }, |
| 908 | .num_parents = 1, |
| 909 | .flags = CLK_SET_RATE_PARENT, |
| 910 | .ops = &clk_branch2_ops, |
| 911 | }, |
| 912 | }, |
| 913 | }; |
| 914 | |
| 915 | static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { |
| 916 | .halt_reg = 0x13004, |
| 917 | .halt_check = BRANCH_HALT, |
| 918 | .clkr = { |
| 919 | .enable_reg = 0x13004, |
| 920 | .enable_mask = BIT(0), |
| 921 | .hw.init = &(struct clk_init_data){ |
| 922 | .name = "gcc_blsp1_qup2_spi_apps_clk", |
| 923 | .parent_names = (const char *[]){ |
| 924 | "gcc_blsp1_qup2_spi_apps_clk_src", |
| 925 | }, |
| 926 | .num_parents = 1, |
| 927 | .flags = CLK_SET_RATE_PARENT, |
| 928 | .ops = &clk_branch2_ops, |
| 929 | }, |
| 930 | }, |
| 931 | }; |
| 932 | |
| 933 | static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { |
| 934 | .halt_reg = 0x15008, |
| 935 | .halt_check = BRANCH_HALT, |
| 936 | .clkr = { |
| 937 | .enable_reg = 0x15008, |
| 938 | .enable_mask = BIT(0), |
| 939 | .hw.init = &(struct clk_init_data){ |
| 940 | .name = "gcc_blsp1_qup3_i2c_apps_clk", |
| 941 | .parent_names = (const char *[]){ |
| 942 | "gcc_blsp1_qup3_i2c_apps_clk_src", |
| 943 | }, |
| 944 | .num_parents = 1, |
| 945 | .flags = CLK_SET_RATE_PARENT, |
| 946 | .ops = &clk_branch2_ops, |
| 947 | }, |
| 948 | }, |
| 949 | }; |
| 950 | |
| 951 | static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { |
| 952 | .halt_reg = 0x15004, |
| 953 | .halt_check = BRANCH_HALT, |
| 954 | .clkr = { |
| 955 | .enable_reg = 0x15004, |
| 956 | .enable_mask = BIT(0), |
| 957 | .hw.init = &(struct clk_init_data){ |
| 958 | .name = "gcc_blsp1_qup3_spi_apps_clk", |
| 959 | .parent_names = (const char *[]){ |
| 960 | "gcc_blsp1_qup3_spi_apps_clk_src", |
| 961 | }, |
| 962 | .num_parents = 1, |
| 963 | .flags = CLK_SET_RATE_PARENT, |
| 964 | .ops = &clk_branch2_ops, |
| 965 | }, |
| 966 | }, |
| 967 | }; |
| 968 | |
| 969 | static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { |
| 970 | .halt_reg = 0x17008, |
| 971 | .halt_check = BRANCH_HALT, |
| 972 | .clkr = { |
| 973 | .enable_reg = 0x17008, |
| 974 | .enable_mask = BIT(0), |
| 975 | .hw.init = &(struct clk_init_data){ |
| 976 | .name = "gcc_blsp1_qup4_i2c_apps_clk", |
| 977 | .parent_names = (const char *[]){ |
| 978 | "gcc_blsp1_qup4_i2c_apps_clk_src", |
| 979 | }, |
| 980 | .num_parents = 1, |
| 981 | .flags = CLK_SET_RATE_PARENT, |
| 982 | .ops = &clk_branch2_ops, |
| 983 | }, |
| 984 | }, |
| 985 | }; |
| 986 | |
| 987 | static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { |
| 988 | .halt_reg = 0x17004, |
| 989 | .halt_check = BRANCH_HALT, |
| 990 | .clkr = { |
| 991 | .enable_reg = 0x17004, |
| 992 | .enable_mask = BIT(0), |
| 993 | .hw.init = &(struct clk_init_data){ |
| 994 | .name = "gcc_blsp1_qup4_spi_apps_clk", |
| 995 | .parent_names = (const char *[]){ |
| 996 | "gcc_blsp1_qup4_spi_apps_clk_src", |
| 997 | }, |
| 998 | .num_parents = 1, |
| 999 | .flags = CLK_SET_RATE_PARENT, |
| 1000 | .ops = &clk_branch2_ops, |
| 1001 | }, |
| 1002 | }, |
| 1003 | }; |
| 1004 | |
| 1005 | static struct clk_branch gcc_blsp1_sleep_clk = { |
| 1006 | .halt_reg = 0x10008, |
| 1007 | .halt_check = BRANCH_HALT_VOTED, |
| 1008 | .clkr = { |
| 1009 | .enable_reg = 0x6d004, |
| 1010 | .enable_mask = BIT(26), |
| 1011 | .hw.init = &(struct clk_init_data){ |
| 1012 | .name = "gcc_blsp1_sleep_clk", |
| 1013 | .ops = &clk_branch2_ops, |
| 1014 | }, |
| 1015 | }, |
| 1016 | }; |
| 1017 | |
| 1018 | static struct clk_branch gcc_blsp1_uart1_apps_clk = { |
| 1019 | .halt_reg = 0x12004, |
| 1020 | .halt_check = BRANCH_HALT, |
| 1021 | .clkr = { |
| 1022 | .enable_reg = 0x12004, |
| 1023 | .enable_mask = BIT(0), |
| 1024 | .hw.init = &(struct clk_init_data){ |
| 1025 | .name = "gcc_blsp1_uart1_apps_clk", |
| 1026 | .parent_names = (const char *[]){ |
| 1027 | "gcc_blsp1_uart1_apps_clk_src", |
| 1028 | }, |
| 1029 | .num_parents = 1, |
| 1030 | .flags = CLK_SET_RATE_PARENT, |
| 1031 | .ops = &clk_branch2_ops, |
| 1032 | }, |
| 1033 | }, |
| 1034 | }; |
| 1035 | |
| 1036 | static struct clk_branch gcc_blsp1_uart2_apps_clk = { |
| 1037 | .halt_reg = 0x14004, |
| 1038 | .halt_check = BRANCH_HALT, |
| 1039 | .clkr = { |
| 1040 | .enable_reg = 0x14004, |
| 1041 | .enable_mask = BIT(0), |
| 1042 | .hw.init = &(struct clk_init_data){ |
| 1043 | .name = "gcc_blsp1_uart2_apps_clk", |
| 1044 | .parent_names = (const char *[]){ |
| 1045 | "gcc_blsp1_uart2_apps_clk_src", |
| 1046 | }, |
| 1047 | .num_parents = 1, |
| 1048 | .flags = CLK_SET_RATE_PARENT, |
| 1049 | .ops = &clk_branch2_ops, |
| 1050 | }, |
| 1051 | }, |
| 1052 | }; |
| 1053 | |
| 1054 | static struct clk_branch gcc_blsp1_uart3_apps_clk = { |
| 1055 | .halt_reg = 0x16004, |
| 1056 | .halt_check = BRANCH_HALT, |
| 1057 | .clkr = { |
| 1058 | .enable_reg = 0x16004, |
| 1059 | .enable_mask = BIT(0), |
| 1060 | .hw.init = &(struct clk_init_data){ |
| 1061 | .name = "gcc_blsp1_uart3_apps_clk", |
| 1062 | .parent_names = (const char *[]){ |
| 1063 | "gcc_blsp1_uart3_apps_clk_src", |
| 1064 | }, |
| 1065 | .num_parents = 1, |
| 1066 | .flags = CLK_SET_RATE_PARENT, |
| 1067 | .ops = &clk_branch2_ops, |
| 1068 | }, |
| 1069 | }, |
| 1070 | }; |
| 1071 | |
| 1072 | static struct clk_branch gcc_blsp1_uart4_apps_clk = { |
| 1073 | .halt_reg = 0x18004, |
| 1074 | .halt_check = BRANCH_HALT, |
| 1075 | .clkr = { |
| 1076 | .enable_reg = 0x18004, |
| 1077 | .enable_mask = BIT(0), |
| 1078 | .hw.init = &(struct clk_init_data){ |
| 1079 | .name = "gcc_blsp1_uart4_apps_clk", |
| 1080 | .parent_names = (const char *[]){ |
| 1081 | "gcc_blsp1_uart4_apps_clk_src", |
| 1082 | }, |
| 1083 | .num_parents = 1, |
| 1084 | .flags = CLK_SET_RATE_PARENT, |
| 1085 | .ops = &clk_branch2_ops, |
| 1086 | }, |
| 1087 | }, |
| 1088 | }; |
| 1089 | |
| 1090 | static struct clk_branch gcc_boot_rom_ahb_clk = { |
| 1091 | .halt_reg = 0x1c004, |
| 1092 | .halt_check = BRANCH_HALT_VOTED, |
| 1093 | .hwcg_reg = 0x1c004, |
| 1094 | .hwcg_bit = 1, |
| 1095 | .clkr = { |
| 1096 | .enable_reg = 0x6d004, |
| 1097 | .enable_mask = BIT(10), |
| 1098 | .hw.init = &(struct clk_init_data){ |
| 1099 | .name = "gcc_boot_rom_ahb_clk", |
| 1100 | .ops = &clk_branch2_ops, |
| 1101 | }, |
| 1102 | }, |
| 1103 | }; |
| 1104 | |
| 1105 | static struct clk_branch gcc_ce1_ahb_clk = { |
| 1106 | .halt_reg = 0x2100c, |
| 1107 | .halt_check = BRANCH_HALT_VOTED, |
| 1108 | .hwcg_reg = 0x2100c, |
| 1109 | .hwcg_bit = 1, |
| 1110 | .clkr = { |
| 1111 | .enable_reg = 0x6d004, |
| 1112 | .enable_mask = BIT(3), |
| 1113 | .hw.init = &(struct clk_init_data){ |
| 1114 | .name = "gcc_ce1_ahb_clk", |
| 1115 | .ops = &clk_branch2_ops, |
| 1116 | }, |
| 1117 | }, |
| 1118 | }; |
| 1119 | |
| 1120 | static struct clk_branch gcc_ce1_axi_clk = { |
| 1121 | .halt_reg = 0x21008, |
| 1122 | .halt_check = BRANCH_HALT_VOTED, |
| 1123 | .clkr = { |
| 1124 | .enable_reg = 0x6d004, |
| 1125 | .enable_mask = BIT(4), |
| 1126 | .hw.init = &(struct clk_init_data){ |
| 1127 | .name = "gcc_ce1_axi_clk", |
| 1128 | .ops = &clk_branch2_ops, |
| 1129 | }, |
| 1130 | }, |
| 1131 | }; |
| 1132 | |
| 1133 | static struct clk_branch gcc_ce1_clk = { |
| 1134 | .halt_reg = 0x21004, |
| 1135 | .halt_check = BRANCH_HALT_VOTED, |
| 1136 | .clkr = { |
| 1137 | .enable_reg = 0x6d004, |
| 1138 | .enable_mask = BIT(5), |
| 1139 | .hw.init = &(struct clk_init_data){ |
| 1140 | .name = "gcc_ce1_clk", |
| 1141 | .ops = &clk_branch2_ops, |
| 1142 | }, |
| 1143 | }, |
| 1144 | }; |
| 1145 | |
| 1146 | static struct clk_branch gcc_cpuss_ahb_clk = { |
| 1147 | .halt_reg = 0x24000, |
| 1148 | .halt_check = BRANCH_HALT_VOTED, |
| 1149 | .clkr = { |
| 1150 | .enable_reg = 0x6d004, |
| 1151 | .enable_mask = BIT(21), |
| 1152 | .hw.init = &(struct clk_init_data){ |
| 1153 | .name = "gcc_cpuss_ahb_clk", |
| 1154 | .parent_names = (const char *[]){ |
| 1155 | "gcc_cpuss_ahb_clk_src", |
| 1156 | }, |
| 1157 | .num_parents = 1, |
| 1158 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
| 1159 | .ops = &clk_branch2_ops, |
| 1160 | }, |
| 1161 | }, |
| 1162 | }; |
| 1163 | |
| 1164 | static struct clk_branch gcc_cpuss_gnoc_clk = { |
| 1165 | .halt_reg = 0x24004, |
| 1166 | .halt_check = BRANCH_HALT_VOTED, |
| 1167 | .hwcg_reg = 0x24004, |
| 1168 | .hwcg_bit = 1, |
| 1169 | .clkr = { |
| 1170 | .enable_reg = 0x6d004, |
| 1171 | .enable_mask = BIT(22), |
| 1172 | .hw.init = &(struct clk_init_data){ |
| 1173 | .name = "gcc_cpuss_gnoc_clk", |
| 1174 | .flags = CLK_IS_CRITICAL, |
| 1175 | .ops = &clk_branch2_ops, |
| 1176 | }, |
| 1177 | }, |
| 1178 | }; |
| 1179 | |
| 1180 | static struct clk_branch gcc_cpuss_rbcpr_clk = { |
| 1181 | .halt_reg = 0x24008, |
| 1182 | .halt_check = BRANCH_HALT, |
| 1183 | .clkr = { |
| 1184 | .enable_reg = 0x24008, |
| 1185 | .enable_mask = BIT(0), |
| 1186 | .hw.init = &(struct clk_init_data){ |
| 1187 | .name = "gcc_cpuss_rbcpr_clk", |
| 1188 | .parent_names = (const char *[]){ |
| 1189 | "gcc_cpuss_rbcpr_clk_src", |
| 1190 | }, |
| 1191 | .num_parents = 1, |
| 1192 | .flags = CLK_SET_RATE_PARENT, |
| 1193 | .ops = &clk_branch2_ops, |
| 1194 | }, |
| 1195 | }, |
| 1196 | }; |
| 1197 | |
| 1198 | static struct clk_branch gcc_eth_axi_clk = { |
| 1199 | .halt_reg = 0x4701c, |
| 1200 | .halt_check = BRANCH_HALT, |
| 1201 | .clkr = { |
| 1202 | .enable_reg = 0x4701c, |
| 1203 | .enable_mask = BIT(0), |
| 1204 | .hw.init = &(struct clk_init_data){ |
| 1205 | .name = "gcc_eth_axi_clk", |
| 1206 | .ops = &clk_branch2_ops, |
| 1207 | }, |
| 1208 | }, |
| 1209 | }; |
| 1210 | |
| 1211 | static struct clk_branch gcc_eth_ptp_clk = { |
| 1212 | .halt_reg = 0x47018, |
| 1213 | .halt_check = BRANCH_HALT, |
| 1214 | .clkr = { |
| 1215 | .enable_reg = 0x47018, |
| 1216 | .enable_mask = BIT(0), |
| 1217 | .hw.init = &(struct clk_init_data){ |
| 1218 | .name = "gcc_eth_ptp_clk", |
| 1219 | .parent_names = (const char *[]){ |
| 1220 | "gcc_emac_ptp_clk_src", |
| 1221 | }, |
| 1222 | .num_parents = 1, |
| 1223 | .flags = CLK_SET_RATE_PARENT, |
| 1224 | .ops = &clk_branch2_ops, |
| 1225 | }, |
| 1226 | }, |
| 1227 | }; |
| 1228 | |
| 1229 | static struct clk_branch gcc_eth_rgmii_clk = { |
| 1230 | .halt_reg = 0x47010, |
| 1231 | .halt_check = BRANCH_HALT, |
| 1232 | .clkr = { |
| 1233 | .enable_reg = 0x47010, |
| 1234 | .enable_mask = BIT(0), |
| 1235 | .hw.init = &(struct clk_init_data){ |
| 1236 | .name = "gcc_eth_rgmii_clk", |
| 1237 | .parent_names = (const char *[]){ |
| 1238 | "gcc_emac_clk_src", |
| 1239 | }, |
| 1240 | .num_parents = 1, |
| 1241 | .flags = CLK_SET_RATE_PARENT, |
| 1242 | .ops = &clk_branch2_ops, |
| 1243 | }, |
| 1244 | }, |
| 1245 | }; |
| 1246 | |
| 1247 | static struct clk_branch gcc_eth_slave_ahb_clk = { |
| 1248 | .halt_reg = 0x47014, |
| 1249 | .halt_check = BRANCH_HALT, |
| 1250 | .hwcg_reg = 0x47014, |
| 1251 | .hwcg_bit = 1, |
| 1252 | .clkr = { |
| 1253 | .enable_reg = 0x47014, |
| 1254 | .enable_mask = BIT(0), |
| 1255 | .hw.init = &(struct clk_init_data){ |
| 1256 | .name = "gcc_eth_slave_ahb_clk", |
| 1257 | .ops = &clk_branch2_ops, |
| 1258 | }, |
| 1259 | }, |
| 1260 | }; |
| 1261 | |
| 1262 | static struct clk_branch gcc_gp1_clk = { |
| 1263 | .halt_reg = 0x2b000, |
| 1264 | .halt_check = BRANCH_HALT, |
| 1265 | .clkr = { |
| 1266 | .enable_reg = 0x2b000, |
| 1267 | .enable_mask = BIT(0), |
| 1268 | .hw.init = &(struct clk_init_data){ |
| 1269 | .name = "gcc_gp1_clk", |
| 1270 | .parent_names = (const char *[]){ |
| 1271 | "gcc_gp1_clk_src", |
| 1272 | }, |
| 1273 | .num_parents = 1, |
| 1274 | .flags = CLK_SET_RATE_PARENT, |
| 1275 | .ops = &clk_branch2_ops, |
| 1276 | }, |
| 1277 | }, |
| 1278 | }; |
| 1279 | |
| 1280 | static struct clk_branch gcc_gp2_clk = { |
| 1281 | .halt_reg = 0x2c000, |
| 1282 | .halt_check = BRANCH_HALT, |
| 1283 | .clkr = { |
| 1284 | .enable_reg = 0x2c000, |
| 1285 | .enable_mask = BIT(0), |
| 1286 | .hw.init = &(struct clk_init_data){ |
| 1287 | .name = "gcc_gp2_clk", |
| 1288 | .parent_names = (const char *[]){ |
| 1289 | "gcc_gp2_clk_src", |
| 1290 | }, |
| 1291 | .num_parents = 1, |
| 1292 | .flags = CLK_SET_RATE_PARENT, |
| 1293 | .ops = &clk_branch2_ops, |
| 1294 | }, |
| 1295 | }, |
| 1296 | }; |
| 1297 | |
| 1298 | static struct clk_branch gcc_gp3_clk = { |
| 1299 | .halt_reg = 0x2d000, |
| 1300 | .halt_check = BRANCH_HALT, |
| 1301 | .clkr = { |
| 1302 | .enable_reg = 0x2d000, |
| 1303 | .enable_mask = BIT(0), |
| 1304 | .hw.init = &(struct clk_init_data){ |
| 1305 | .name = "gcc_gp3_clk", |
| 1306 | .parent_names = (const char *[]){ |
| 1307 | "gcc_gp3_clk_src", |
| 1308 | }, |
| 1309 | .num_parents = 1, |
| 1310 | .flags = CLK_SET_RATE_PARENT, |
| 1311 | .ops = &clk_branch2_ops, |
| 1312 | }, |
| 1313 | }, |
| 1314 | }; |
| 1315 | |
| 1316 | static struct clk_branch gcc_mss_cfg_ahb_clk = { |
| 1317 | .halt_reg = 0x40000, |
| 1318 | .halt_check = BRANCH_HALT, |
| 1319 | .hwcg_reg = 0x40000, |
| 1320 | .hwcg_bit = 1, |
| 1321 | .clkr = { |
| 1322 | .enable_reg = 0x40000, |
| 1323 | .enable_mask = BIT(0), |
| 1324 | .hw.init = &(struct clk_init_data){ |
| 1325 | .name = "gcc_mss_cfg_ahb_clk", |
| 1326 | .ops = &clk_branch2_ops, |
| 1327 | }, |
| 1328 | }, |
| 1329 | }; |
| 1330 | |
| 1331 | static struct clk_gate2 gcc_mss_gpll0_div_clk_src = { |
| 1332 | .udelay = 500, |
| 1333 | .clkr = { |
| 1334 | .enable_reg = 0x6d004, |
| 1335 | .enable_mask = BIT(17), |
| 1336 | .hw.init = &(struct clk_init_data){ |
| 1337 | .name = "gcc_mss_gpll0_div_clk_src", |
| 1338 | .ops = &clk_gate2_ops, |
| 1339 | }, |
| 1340 | }, |
| 1341 | }; |
| 1342 | |
| 1343 | static struct clk_branch gcc_mss_snoc_axi_clk = { |
| 1344 | .halt_reg = 0x40148, |
| 1345 | .halt_check = BRANCH_HALT, |
| 1346 | .clkr = { |
| 1347 | .enable_reg = 0x40148, |
| 1348 | .enable_mask = BIT(0), |
| 1349 | .hw.init = &(struct clk_init_data){ |
| 1350 | .name = "gcc_mss_snoc_axi_clk", |
| 1351 | .ops = &clk_branch2_ops, |
| 1352 | }, |
| 1353 | }, |
| 1354 | }; |
| 1355 | |
| 1356 | static struct clk_branch gcc_pcie_aux_clk = { |
| 1357 | .halt_reg = 0x37020, |
| 1358 | .halt_check = BRANCH_HALT_VOTED, |
| 1359 | .clkr = { |
| 1360 | .enable_reg = 0x6d00c, |
| 1361 | .enable_mask = BIT(3), |
| 1362 | .hw.init = &(struct clk_init_data){ |
| 1363 | .name = "gcc_pcie_aux_clk", |
| 1364 | .ops = &clk_branch2_ops, |
| 1365 | }, |
| 1366 | }, |
| 1367 | }; |
| 1368 | |
| 1369 | static struct clk_branch gcc_pcie_cfg_ahb_clk = { |
| 1370 | .halt_reg = 0x3701c, |
| 1371 | .halt_check = BRANCH_HALT_VOTED, |
| 1372 | .hwcg_reg = 0x3701c, |
| 1373 | .hwcg_bit = 1, |
| 1374 | .clkr = { |
| 1375 | .enable_reg = 0x6d00c, |
| 1376 | .enable_mask = BIT(2), |
| 1377 | .hw.init = &(struct clk_init_data){ |
| 1378 | .name = "gcc_pcie_cfg_ahb_clk", |
| 1379 | .ops = &clk_branch2_ops, |
| 1380 | }, |
| 1381 | }, |
| 1382 | }; |
| 1383 | |
| 1384 | static struct clk_branch gcc_pcie_mstr_axi_clk = { |
| 1385 | .halt_reg = 0x37018, |
| 1386 | .halt_check = BRANCH_HALT_VOTED, |
| 1387 | .clkr = { |
| 1388 | .enable_reg = 0x6d00c, |
| 1389 | .enable_mask = BIT(1), |
| 1390 | .hw.init = &(struct clk_init_data){ |
| 1391 | .name = "gcc_pcie_mstr_axi_clk", |
| 1392 | .ops = &clk_branch2_ops, |
| 1393 | }, |
| 1394 | }, |
| 1395 | }; |
| 1396 | |
| 1397 | static struct clk_branch gcc_pcie_phy_refgen_clk = { |
| 1398 | .halt_reg = 0x39028, |
| 1399 | .halt_check = BRANCH_HALT, |
| 1400 | .clkr = { |
| 1401 | .enable_reg = 0x39028, |
| 1402 | .enable_mask = BIT(0), |
| 1403 | .hw.init = &(struct clk_init_data){ |
| 1404 | .name = "gcc_pcie_phy_refgen_clk", |
| 1405 | .parent_names = (const char *[]){ |
| 1406 | "gcc_pcie_phy_refgen_clk_src", |
| 1407 | }, |
| 1408 | .num_parents = 1, |
| 1409 | .flags = CLK_SET_RATE_PARENT, |
| 1410 | .ops = &clk_branch2_ops, |
| 1411 | }, |
| 1412 | }, |
| 1413 | }; |
| 1414 | |
| 1415 | static struct clk_branch gcc_pcie_pipe_clk = { |
| 1416 | .halt_reg = 0x37028, |
| 1417 | .halt_check = BRANCH_HALT_VOTED, |
| 1418 | .clkr = { |
| 1419 | .enable_reg = 0x6d00c, |
| 1420 | .enable_mask = BIT(4), |
| 1421 | .hw.init = &(struct clk_init_data){ |
| 1422 | .name = "gcc_pcie_pipe_clk", |
| 1423 | .ops = &clk_branch2_ops, |
| 1424 | }, |
| 1425 | }, |
| 1426 | }; |
| 1427 | |
| 1428 | static struct clk_branch gcc_pcie_sleep_clk = { |
| 1429 | .halt_reg = 0x37024, |
| 1430 | .halt_check = BRANCH_HALT_VOTED, |
| 1431 | .clkr = { |
| 1432 | .enable_reg = 0x6d00c, |
| 1433 | .enable_mask = BIT(6), |
| 1434 | .hw.init = &(struct clk_init_data){ |
| 1435 | .name = "gcc_pcie_sleep_clk", |
| 1436 | .parent_names = (const char *[]){ |
| 1437 | "gcc_pcie_aux_phy_clk_src", |
| 1438 | }, |
| 1439 | .num_parents = 1, |
| 1440 | .flags = CLK_SET_RATE_PARENT, |
| 1441 | .ops = &clk_branch2_ops, |
| 1442 | }, |
| 1443 | }, |
| 1444 | }; |
| 1445 | |
| 1446 | static struct clk_branch gcc_pcie_slv_axi_clk = { |
| 1447 | .halt_reg = 0x37014, |
| 1448 | .halt_check = BRANCH_HALT_VOTED, |
| 1449 | .hwcg_reg = 0x37014, |
| 1450 | .hwcg_bit = 1, |
| 1451 | .clkr = { |
| 1452 | .enable_reg = 0x6d00c, |
| 1453 | .enable_mask = BIT(0), |
| 1454 | .hw.init = &(struct clk_init_data){ |
| 1455 | .name = "gcc_pcie_slv_axi_clk", |
| 1456 | .ops = &clk_branch2_ops, |
| 1457 | }, |
| 1458 | }, |
| 1459 | }; |
| 1460 | |
| 1461 | static struct clk_branch gcc_pcie_slv_q2a_axi_clk = { |
| 1462 | .halt_reg = 0x37010, |
| 1463 | .halt_check = BRANCH_HALT_VOTED, |
| 1464 | .clkr = { |
| 1465 | .enable_reg = 0x6d00c, |
| 1466 | .enable_mask = BIT(5), |
| 1467 | .hw.init = &(struct clk_init_data){ |
| 1468 | .name = "gcc_pcie_slv_q2a_axi_clk", |
| 1469 | .ops = &clk_branch2_ops, |
| 1470 | }, |
| 1471 | }, |
| 1472 | }; |
| 1473 | |
| 1474 | static struct clk_branch gcc_pdm2_clk = { |
| 1475 | .halt_reg = 0x1900c, |
| 1476 | .halt_check = BRANCH_HALT, |
| 1477 | .clkr = { |
| 1478 | .enable_reg = 0x1900c, |
| 1479 | .enable_mask = BIT(0), |
| 1480 | .hw.init = &(struct clk_init_data){ |
| 1481 | .name = "gcc_pdm2_clk", |
| 1482 | .parent_names = (const char *[]){ |
| 1483 | "gcc_pdm2_clk_src", |
| 1484 | }, |
| 1485 | .num_parents = 1, |
| 1486 | .flags = CLK_SET_RATE_PARENT, |
| 1487 | .ops = &clk_branch2_ops, |
| 1488 | }, |
| 1489 | }, |
| 1490 | }; |
| 1491 | |
| 1492 | static struct clk_branch gcc_pdm_ahb_clk = { |
| 1493 | .halt_reg = 0x19004, |
| 1494 | .halt_check = BRANCH_HALT, |
| 1495 | .hwcg_reg = 0x19004, |
| 1496 | .hwcg_bit = 1, |
| 1497 | .clkr = { |
| 1498 | .enable_reg = 0x19004, |
| 1499 | .enable_mask = BIT(0), |
| 1500 | .hw.init = &(struct clk_init_data){ |
| 1501 | .name = "gcc_pdm_ahb_clk", |
| 1502 | .ops = &clk_branch2_ops, |
| 1503 | }, |
| 1504 | }, |
| 1505 | }; |
| 1506 | |
| 1507 | static struct clk_branch gcc_pdm_xo4_clk = { |
| 1508 | .halt_reg = 0x19008, |
| 1509 | .halt_check = BRANCH_HALT, |
| 1510 | .clkr = { |
| 1511 | .enable_reg = 0x19008, |
| 1512 | .enable_mask = BIT(0), |
| 1513 | .hw.init = &(struct clk_init_data){ |
| 1514 | .name = "gcc_pdm_xo4_clk", |
| 1515 | .ops = &clk_branch2_ops, |
| 1516 | }, |
| 1517 | }, |
| 1518 | }; |
| 1519 | |
| 1520 | static struct clk_branch gcc_prng_ahb_clk = { |
| 1521 | .halt_reg = 0x1a004, |
| 1522 | .halt_check = BRANCH_HALT_VOTED, |
| 1523 | .clkr = { |
| 1524 | .enable_reg = 0x6d004, |
| 1525 | .enable_mask = BIT(13), |
| 1526 | .hw.init = &(struct clk_init_data){ |
| 1527 | .name = "gcc_prng_ahb_clk", |
| 1528 | .ops = &clk_branch2_ops, |
| 1529 | }, |
| 1530 | }, |
| 1531 | }; |
| 1532 | |
| 1533 | static struct clk_branch gcc_sdcc1_ahb_clk = { |
| 1534 | .halt_reg = 0xf008, |
| 1535 | .halt_check = BRANCH_HALT, |
| 1536 | .clkr = { |
| 1537 | .enable_reg = 0xf008, |
| 1538 | .enable_mask = BIT(0), |
| 1539 | .hw.init = &(struct clk_init_data){ |
| 1540 | .name = "gcc_sdcc1_ahb_clk", |
| 1541 | .ops = &clk_branch2_ops, |
| 1542 | }, |
| 1543 | }, |
| 1544 | }; |
| 1545 | |
| 1546 | static struct clk_branch gcc_sdcc1_apps_clk = { |
| 1547 | .halt_reg = 0xf004, |
| 1548 | .halt_check = BRANCH_HALT, |
| 1549 | .clkr = { |
| 1550 | .enable_reg = 0xf004, |
| 1551 | .enable_mask = BIT(0), |
| 1552 | .hw.init = &(struct clk_init_data){ |
| 1553 | .name = "gcc_sdcc1_apps_clk", |
| 1554 | .parent_names = (const char *[]){ |
| 1555 | "gcc_sdcc1_apps_clk_src", |
| 1556 | }, |
| 1557 | .num_parents = 1, |
| 1558 | .flags = CLK_SET_RATE_PARENT, |
| 1559 | .ops = &clk_branch2_ops, |
| 1560 | }, |
| 1561 | }, |
| 1562 | }; |
| 1563 | |
| 1564 | static struct clk_branch gcc_spmi_fetcher_ahb_clk = { |
| 1565 | .halt_reg = 0x3f008, |
| 1566 | .halt_check = BRANCH_HALT, |
| 1567 | .clkr = { |
| 1568 | .enable_reg = 0x3f008, |
| 1569 | .enable_mask = BIT(0), |
| 1570 | .hw.init = &(struct clk_init_data){ |
| 1571 | .name = "gcc_spmi_fetcher_ahb_clk", |
| 1572 | .ops = &clk_branch2_ops, |
| 1573 | }, |
| 1574 | }, |
| 1575 | }; |
| 1576 | |
| 1577 | static struct clk_branch gcc_spmi_fetcher_clk = { |
| 1578 | .halt_reg = 0x3f004, |
| 1579 | .halt_check = BRANCH_HALT, |
| 1580 | .clkr = { |
| 1581 | .enable_reg = 0x3f004, |
| 1582 | .enable_mask = BIT(0), |
| 1583 | .hw.init = &(struct clk_init_data){ |
| 1584 | .name = "gcc_spmi_fetcher_clk", |
| 1585 | .parent_names = (const char *[]){ |
| 1586 | "gcc_spmi_fetcher_clk_src", |
| 1587 | }, |
| 1588 | .num_parents = 1, |
| 1589 | .flags = CLK_SET_RATE_PARENT, |
| 1590 | .ops = &clk_branch2_ops, |
| 1591 | }, |
| 1592 | }, |
| 1593 | }; |
| 1594 | |
| 1595 | static struct clk_branch gcc_sys_noc_cpuss_ahb_clk = { |
| 1596 | .halt_reg = 0x400c, |
| 1597 | .halt_check = BRANCH_HALT_VOTED, |
| 1598 | .clkr = { |
| 1599 | .enable_reg = 0x6d004, |
| 1600 | .enable_mask = BIT(0), |
| 1601 | .hw.init = &(struct clk_init_data){ |
| 1602 | .name = "gcc_sys_noc_cpuss_ahb_clk", |
| 1603 | .parent_names = (const char *[]){ |
| 1604 | "gcc_cpuss_ahb_clk_src", |
| 1605 | }, |
| 1606 | .num_parents = 1, |
| 1607 | .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, |
| 1608 | .ops = &clk_branch2_ops, |
| 1609 | }, |
| 1610 | }, |
| 1611 | }; |
| 1612 | |
| 1613 | static struct clk_branch gcc_sys_noc_usb3_clk = { |
| 1614 | .halt_reg = 0x4018, |
| 1615 | .halt_check = BRANCH_HALT, |
| 1616 | .clkr = { |
| 1617 | .enable_reg = 0x4018, |
| 1618 | .enable_mask = BIT(0), |
| 1619 | .hw.init = &(struct clk_init_data){ |
| 1620 | .name = "gcc_sys_noc_usb3_clk", |
| 1621 | .parent_names = (const char *[]){ |
| 1622 | "gcc_usb30_master_clk_src", |
| 1623 | }, |
| 1624 | .num_parents = 1, |
| 1625 | .flags = CLK_SET_RATE_PARENT, |
| 1626 | .ops = &clk_branch2_ops, |
| 1627 | }, |
| 1628 | }, |
| 1629 | }; |
| 1630 | |
| 1631 | static struct clk_branch gcc_usb30_master_clk = { |
| 1632 | .halt_reg = 0xb010, |
| 1633 | .halt_check = BRANCH_HALT, |
| 1634 | .clkr = { |
| 1635 | .enable_reg = 0xb010, |
| 1636 | .enable_mask = BIT(0), |
| 1637 | .hw.init = &(struct clk_init_data){ |
| 1638 | .name = "gcc_usb30_master_clk", |
| 1639 | .parent_names = (const char *[]){ |
| 1640 | "gcc_usb30_master_clk_src", |
| 1641 | }, |
| 1642 | .num_parents = 1, |
| 1643 | .flags = CLK_SET_RATE_PARENT, |
| 1644 | .ops = &clk_branch2_ops, |
| 1645 | }, |
| 1646 | }, |
| 1647 | }; |
| 1648 | |
| 1649 | static struct clk_branch gcc_usb30_mock_utmi_clk = { |
| 1650 | .halt_reg = 0xb018, |
| 1651 | .halt_check = BRANCH_HALT, |
| 1652 | .clkr = { |
| 1653 | .enable_reg = 0xb018, |
| 1654 | .enable_mask = BIT(0), |
| 1655 | .hw.init = &(struct clk_init_data){ |
| 1656 | .name = "gcc_usb30_mock_utmi_clk", |
| 1657 | .parent_names = (const char *[]){ |
| 1658 | "gcc_usb30_mock_utmi_clk_src", |
| 1659 | }, |
| 1660 | .num_parents = 1, |
| 1661 | .flags = CLK_SET_RATE_PARENT, |
| 1662 | .ops = &clk_branch2_ops, |
| 1663 | }, |
| 1664 | }, |
| 1665 | }; |
| 1666 | |
| 1667 | static struct clk_branch gcc_usb30_sleep_clk = { |
| 1668 | .halt_reg = 0xb014, |
| 1669 | .halt_check = BRANCH_HALT, |
| 1670 | .clkr = { |
| 1671 | .enable_reg = 0xb014, |
| 1672 | .enable_mask = BIT(0), |
| 1673 | .hw.init = &(struct clk_init_data){ |
| 1674 | .name = "gcc_usb30_sleep_clk", |
| 1675 | .ops = &clk_branch2_ops, |
| 1676 | }, |
| 1677 | }, |
| 1678 | }; |
| 1679 | |
| 1680 | static struct clk_branch gcc_usb3_phy_aux_clk = { |
| 1681 | .halt_reg = 0xb050, |
| 1682 | .halt_check = BRANCH_HALT, |
| 1683 | .clkr = { |
| 1684 | .enable_reg = 0xb050, |
| 1685 | .enable_mask = BIT(0), |
| 1686 | .hw.init = &(struct clk_init_data){ |
| 1687 | .name = "gcc_usb3_phy_aux_clk", |
| 1688 | .parent_names = (const char *[]){ |
| 1689 | "gcc_usb3_phy_aux_clk_src", |
| 1690 | }, |
| 1691 | .num_parents = 1, |
| 1692 | .flags = CLK_SET_RATE_PARENT, |
| 1693 | .ops = &clk_branch2_ops, |
| 1694 | }, |
| 1695 | }, |
| 1696 | }; |
| 1697 | |
| 1698 | static struct clk_branch gcc_usb3_phy_pipe_clk = { |
| 1699 | .halt_reg = 0xb054, |
| 1700 | .halt_check = BRANCH_HALT, |
| 1701 | .clkr = { |
| 1702 | .enable_reg = 0xb054, |
| 1703 | .enable_mask = BIT(0), |
| 1704 | .hw.init = &(struct clk_init_data){ |
| 1705 | .name = "gcc_usb3_phy_pipe_clk", |
| 1706 | .ops = &clk_branch2_ops, |
| 1707 | }, |
| 1708 | }, |
| 1709 | }; |
| 1710 | |
| 1711 | static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { |
| 1712 | .halt_reg = 0xe004, |
| 1713 | .halt_check = BRANCH_HALT, |
| 1714 | .hwcg_reg = 0xe004, |
| 1715 | .hwcg_bit = 1, |
| 1716 | .clkr = { |
| 1717 | .enable_reg = 0xe004, |
| 1718 | .enable_mask = BIT(0), |
| 1719 | .hw.init = &(struct clk_init_data){ |
| 1720 | .name = "gcc_usb_phy_cfg_ahb2phy_clk", |
| 1721 | .ops = &clk_branch2_ops, |
| 1722 | }, |
| 1723 | }, |
| 1724 | }; |
| 1725 | |
| 1726 | static struct clk_regmap *gcc_sdxpoorwills_clocks[] = { |
| 1727 | [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, |
| 1728 | [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, |
| 1729 | [GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC] = |
| 1730 | &gcc_blsp1_qup1_i2c_apps_clk_src.clkr, |
| 1731 | [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, |
| 1732 | [GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = |
| 1733 | &gcc_blsp1_qup1_spi_apps_clk_src.clkr, |
| 1734 | [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, |
| 1735 | [GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC] = |
| 1736 | &gcc_blsp1_qup2_i2c_apps_clk_src.clkr, |
| 1737 | [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, |
| 1738 | [GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = |
| 1739 | &gcc_blsp1_qup2_spi_apps_clk_src.clkr, |
| 1740 | [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, |
| 1741 | [GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC] = |
| 1742 | &gcc_blsp1_qup3_i2c_apps_clk_src.clkr, |
| 1743 | [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, |
| 1744 | [GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = |
| 1745 | &gcc_blsp1_qup3_spi_apps_clk_src.clkr, |
| 1746 | [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, |
| 1747 | [GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC] = |
| 1748 | &gcc_blsp1_qup4_i2c_apps_clk_src.clkr, |
| 1749 | [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, |
| 1750 | [GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC] = |
| 1751 | &gcc_blsp1_qup4_spi_apps_clk_src.clkr, |
| 1752 | [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, |
| 1753 | [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, |
| 1754 | [GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr, |
| 1755 | [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, |
| 1756 | [GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr, |
| 1757 | [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr, |
| 1758 | [GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr, |
| 1759 | [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr, |
| 1760 | [GCC_BLSP1_UART4_APPS_CLK_SRC] = &gcc_blsp1_uart4_apps_clk_src.clkr, |
| 1761 | [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, |
| 1762 | [GCC_CE1_AHB_CLK] = &gcc_ce1_ahb_clk.clkr, |
| 1763 | [GCC_CE1_AXI_CLK] = &gcc_ce1_axi_clk.clkr, |
| 1764 | [GCC_CE1_CLK] = &gcc_ce1_clk.clkr, |
| 1765 | [GCC_CPUSS_AHB_CLK] = &gcc_cpuss_ahb_clk.clkr, |
| 1766 | [GCC_CPUSS_AHB_CLK_SRC] = &gcc_cpuss_ahb_clk_src.clkr, |
| 1767 | [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr, |
| 1768 | [GCC_CPUSS_RBCPR_CLK] = &gcc_cpuss_rbcpr_clk.clkr, |
| 1769 | [GCC_CPUSS_RBCPR_CLK_SRC] = &gcc_cpuss_rbcpr_clk_src.clkr, |
| 1770 | [GCC_EMAC_CLK_SRC] = &gcc_emac_clk_src.clkr, |
| 1771 | [GCC_EMAC_PTP_CLK_SRC] = &gcc_emac_ptp_clk_src.clkr, |
| 1772 | [GCC_ETH_AXI_CLK] = &gcc_eth_axi_clk.clkr, |
| 1773 | [GCC_ETH_PTP_CLK] = &gcc_eth_ptp_clk.clkr, |
| 1774 | [GCC_ETH_RGMII_CLK] = &gcc_eth_rgmii_clk.clkr, |
| 1775 | [GCC_ETH_SLAVE_AHB_CLK] = &gcc_eth_slave_ahb_clk.clkr, |
| 1776 | [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, |
| 1777 | [GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr, |
| 1778 | [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, |
| 1779 | [GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr, |
| 1780 | [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, |
| 1781 | [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, |
| 1782 | [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, |
| 1783 | [GCC_MSS_GPLL0_DIV_CLK_SRC] = &gcc_mss_gpll0_div_clk_src.clkr, |
| 1784 | [GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr, |
| 1785 | [GCC_PCIE_AUX_CLK] = &gcc_pcie_aux_clk.clkr, |
| 1786 | [GCC_PCIE_AUX_PHY_CLK_SRC] = &gcc_pcie_aux_phy_clk_src.clkr, |
| 1787 | [GCC_PCIE_CFG_AHB_CLK] = &gcc_pcie_cfg_ahb_clk.clkr, |
| 1788 | [GCC_PCIE_MSTR_AXI_CLK] = &gcc_pcie_mstr_axi_clk.clkr, |
| 1789 | [GCC_PCIE_PHY_REFGEN_CLK] = &gcc_pcie_phy_refgen_clk.clkr, |
| 1790 | [GCC_PCIE_PHY_REFGEN_CLK_SRC] = &gcc_pcie_phy_refgen_clk_src.clkr, |
| 1791 | [GCC_PCIE_PIPE_CLK] = &gcc_pcie_pipe_clk.clkr, |
| 1792 | [GCC_PCIE_SLEEP_CLK] = &gcc_pcie_sleep_clk.clkr, |
| 1793 | [GCC_PCIE_SLV_AXI_CLK] = &gcc_pcie_slv_axi_clk.clkr, |
| 1794 | [GCC_PCIE_SLV_Q2A_AXI_CLK] = &gcc_pcie_slv_q2a_axi_clk.clkr, |
| 1795 | [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, |
| 1796 | [GCC_PDM2_CLK_SRC] = &gcc_pdm2_clk_src.clkr, |
| 1797 | [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, |
| 1798 | [GCC_PDM_XO4_CLK] = &gcc_pdm_xo4_clk.clkr, |
| 1799 | [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, |
| 1800 | [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, |
| 1801 | [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, |
| 1802 | [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, |
| 1803 | [GCC_SPMI_FETCHER_AHB_CLK] = &gcc_spmi_fetcher_ahb_clk.clkr, |
| 1804 | [GCC_SPMI_FETCHER_CLK] = &gcc_spmi_fetcher_clk.clkr, |
| 1805 | [GCC_SPMI_FETCHER_CLK_SRC] = &gcc_spmi_fetcher_clk_src.clkr, |
| 1806 | [GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr, |
| 1807 | [GCC_SYS_NOC_USB3_CLK] = &gcc_sys_noc_usb3_clk.clkr, |
| 1808 | [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr, |
| 1809 | [GCC_USB30_MASTER_CLK_SRC] = &gcc_usb30_master_clk_src.clkr, |
| 1810 | [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, |
| 1811 | [GCC_USB30_MOCK_UTMI_CLK_SRC] = &gcc_usb30_mock_utmi_clk_src.clkr, |
| 1812 | [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, |
| 1813 | [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, |
| 1814 | [GCC_USB3_PHY_AUX_CLK_SRC] = &gcc_usb3_phy_aux_clk_src.clkr, |
| 1815 | [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, |
| 1816 | [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, |
| 1817 | [GPLL0] = &gpll0.clkr, |
| 1818 | [GPLL0_OUT_EVEN] = &gpll0_out_even.clkr, |
| 1819 | [GPLL4] = &gpll4.clkr, |
| 1820 | [GPLL4_OUT_EVEN] = &gpll4_out_even.clkr, |
| 1821 | }; |
| 1822 | |
| 1823 | static const struct qcom_reset_map gcc_sdxpoorwills_resets[] = { |
| 1824 | [GCC_BLSP1_QUP1_BCR] = { 0x11000 }, |
| 1825 | [GCC_BLSP1_QUP2_BCR] = { 0x13000 }, |
| 1826 | [GCC_BLSP1_QUP3_BCR] = { 0x15000 }, |
| 1827 | [GCC_BLSP1_QUP4_BCR] = { 0x17000 }, |
| 1828 | [GCC_BLSP1_UART2_BCR] = { 0x14000 }, |
| 1829 | [GCC_BLSP1_UART3_BCR] = { 0x16000 }, |
| 1830 | [GCC_BLSP1_UART4_BCR] = { 0x18000 }, |
| 1831 | [GCC_CE1_BCR] = { 0x21000 }, |
| 1832 | [GCC_EMAC_BCR] = { 0x47000 }, |
| 1833 | [GCC_PCIE_BCR] = { 0x37000 }, |
| 1834 | [GCC_PCIE_PHY_BCR] = { 0x39000 }, |
| 1835 | [GCC_PDM_BCR] = { 0x19000 }, |
| 1836 | [GCC_PRNG_BCR] = { 0x1a000 }, |
| 1837 | [GCC_SDCC1_BCR] = { 0xf000 }, |
| 1838 | [GCC_SPMI_FETCHER_BCR] = { 0x3f000 }, |
| 1839 | [GCC_USB30_BCR] = { 0xb000 }, |
| 1840 | [GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0xe000 }, |
| 1841 | }; |
| 1842 | |
| 1843 | |
| 1844 | static const struct regmap_config gcc_sdxpoorwills_regmap_config = { |
| 1845 | .reg_bits = 32, |
| 1846 | .reg_stride = 4, |
| 1847 | .val_bits = 32, |
| 1848 | .max_register = 0x9b040, |
| 1849 | .fast_io = true, |
| 1850 | }; |
| 1851 | |
| 1852 | static const struct qcom_cc_desc gcc_sdxpoorwills_desc = { |
| 1853 | .config = &gcc_sdxpoorwills_regmap_config, |
| 1854 | .clks = gcc_sdxpoorwills_clocks, |
| 1855 | .num_clks = ARRAY_SIZE(gcc_sdxpoorwills_clocks), |
| 1856 | .resets = gcc_sdxpoorwills_resets, |
| 1857 | .num_resets = ARRAY_SIZE(gcc_sdxpoorwills_resets), |
| 1858 | }; |
| 1859 | |
| 1860 | static const struct of_device_id gcc_sdxpoorwills_match_table[] = { |
| 1861 | { .compatible = "qcom,gcc-sdxpoorwills" }, |
| 1862 | { } |
| 1863 | }; |
| 1864 | MODULE_DEVICE_TABLE(of, gcc_sdxpoorwills_match_table); |
| 1865 | |
| 1866 | static int gcc_sdxpoorwills_probe(struct platform_device *pdev) |
| 1867 | { |
| 1868 | int ret = 0; |
| 1869 | struct regmap *regmap; |
| 1870 | |
| 1871 | regmap = qcom_cc_map(pdev, &gcc_sdxpoorwills_desc); |
| 1872 | if (IS_ERR(regmap)) |
| 1873 | return PTR_ERR(regmap); |
| 1874 | |
| 1875 | vdd_cx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_cx"); |
| 1876 | if (IS_ERR(vdd_cx.regulator[0])) { |
| 1877 | if (!(PTR_ERR(vdd_cx.regulator[0]) == -EPROBE_DEFER)) |
| 1878 | dev_err(&pdev->dev, |
| 1879 | "Unable to get vdd_cx regulator\n"); |
| 1880 | return PTR_ERR(vdd_cx.regulator[0]); |
| 1881 | } |
| 1882 | |
| 1883 | ret = qcom_cc_really_probe(pdev, &gcc_sdxpoorwills_desc, regmap); |
| 1884 | if (ret) { |
| 1885 | dev_err(&pdev->dev, "Failed to register GCC clocks\n"); |
| 1886 | return ret; |
| 1887 | } |
| 1888 | |
| 1889 | dev_info(&pdev->dev, "Registered GCC clocks\n"); |
| 1890 | |
| 1891 | return ret; |
| 1892 | } |
| 1893 | |
| 1894 | static struct platform_driver gcc_sdxpoorwills_driver = { |
| 1895 | .probe = gcc_sdxpoorwills_probe, |
| 1896 | .driver = { |
| 1897 | .name = "gcc-sdxpoorwills", |
| 1898 | .of_match_table = gcc_sdxpoorwills_match_table, |
| 1899 | }, |
| 1900 | }; |
| 1901 | |
| 1902 | static int __init gcc_sdxpoorwills_init(void) |
| 1903 | { |
| 1904 | return platform_driver_register(&gcc_sdxpoorwills_driver); |
| 1905 | } |
| 1906 | core_initcall(gcc_sdxpoorwills_init); |
| 1907 | |
| 1908 | static void __exit gcc_sdxpoorwills_exit(void) |
| 1909 | { |
| 1910 | platform_driver_unregister(&gcc_sdxpoorwills_driver); |
| 1911 | } |
| 1912 | module_exit(gcc_sdxpoorwills_exit); |
| 1913 | |
| 1914 | MODULE_DESCRIPTION("QTI GCC SDXPOORWILLS Driver"); |
| 1915 | MODULE_LICENSE("GPL v2"); |
| 1916 | MODULE_ALIAS("platform:gcc-sdxpoorwills"); |