Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 1 | /* |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 and |
| 6 | * only version 2 as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | */ |
| 14 | |
| 15 | #ifndef _DSI_CTRL_H_ |
| 16 | #define _DSI_CTRL_H_ |
| 17 | |
Ajay Singh Parmar | 48ea427 | 2016-06-27 11:44:34 -0700 | [diff] [blame] | 18 | #include <linux/debugfs.h> |
| 19 | |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 20 | #include "dsi_defs.h" |
| 21 | #include "dsi_ctrl_hw.h" |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 22 | #include "dsi_clk.h" |
| 23 | #include "dsi_pwr.h" |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 24 | #include "drm_mipi_dsi.h" |
| 25 | |
| 26 | /* |
| 27 | * DSI Command transfer modifiers |
| 28 | * @DSI_CTRL_CMD_READ: The current transfer involves reading data. |
| 29 | * @DSI_CTRL_CMD_BROADCAST: The current transfer needs to be done in |
| 30 | * broadcast mode to multiple slaves. |
| 31 | * @DSI_CTRL_CMD_BROADCAST_MASTER: This controller is the master and the slaves |
| 32 | * sync to this trigger. |
| 33 | * @DSI_CTRL_CMD_DEFER_TRIGGER: Defer the command trigger to later. |
| 34 | * @DSI_CTRL_CMD_FIFO_STORE: Use FIFO for command transfer in place of |
| 35 | * reading data from memory. |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 36 | * @DSI_CTRL_CMD_FETCH_MEMORY: Fetch command from memory through AXI bus |
| 37 | * and transfer it. |
Vara Reddy | 326612b | 2017-09-20 04:41:10 -0700 | [diff] [blame] | 38 | * @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last |
| 39 | * command in the batch. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 40 | */ |
| 41 | #define DSI_CTRL_CMD_READ 0x1 |
| 42 | #define DSI_CTRL_CMD_BROADCAST 0x2 |
| 43 | #define DSI_CTRL_CMD_BROADCAST_MASTER 0x4 |
| 44 | #define DSI_CTRL_CMD_DEFER_TRIGGER 0x8 |
| 45 | #define DSI_CTRL_CMD_FIFO_STORE 0x10 |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 46 | #define DSI_CTRL_CMD_FETCH_MEMORY 0x20 |
Vara Reddy | 326612b | 2017-09-20 04:41:10 -0700 | [diff] [blame] | 47 | #define DSI_CTRL_CMD_LAST_COMMAND 0x40 |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 48 | |
Veera Sundaram Sankaran | d2a9394 | 2017-10-20 12:44:18 -0700 | [diff] [blame] | 49 | /* max size supported for dsi cmd transfer using TPG */ |
| 50 | #define DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE 64 |
| 51 | |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 52 | /** |
| 53 | * enum dsi_power_state - defines power states for dsi controller. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 54 | * @DSI_CTRL_POWER_VREG_OFF: Digital and analog supplies for DSI controller |
| 55 | turned off |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 56 | * @DSI_CTRL_POWER_VREG_ON: Digital and analog supplies for DSI controller |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 57 | * @DSI_CTRL_POWER_MAX: Maximum value. |
| 58 | */ |
| 59 | enum dsi_power_state { |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 60 | DSI_CTRL_POWER_VREG_OFF = 0, |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 61 | DSI_CTRL_POWER_VREG_ON, |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 62 | DSI_CTRL_POWER_MAX, |
| 63 | }; |
| 64 | |
| 65 | /** |
| 66 | * enum dsi_engine_state - define engine status for dsi controller. |
| 67 | * @DSI_CTRL_ENGINE_OFF: Engine is turned off. |
| 68 | * @DSI_CTRL_ENGINE_ON: Engine is turned on. |
| 69 | * @DSI_CTRL_ENGINE_MAX: Maximum value. |
| 70 | */ |
| 71 | enum dsi_engine_state { |
| 72 | DSI_CTRL_ENGINE_OFF = 0, |
| 73 | DSI_CTRL_ENGINE_ON, |
| 74 | DSI_CTRL_ENGINE_MAX, |
| 75 | }; |
| 76 | |
| 77 | /** |
| 78 | * struct dsi_ctrl_power_info - digital and analog power supplies for dsi host |
| 79 | * @digital: Digital power supply required to turn on DSI controller hardware. |
| 80 | * @host_pwr: Analog power supplies required to turn on DSI controller hardware. |
| 81 | * Even though DSI controller it self does not require an analog |
| 82 | * power supply, supplies required for PLL can be defined here to |
| 83 | * allow proper control over these supplies. |
| 84 | */ |
| 85 | struct dsi_ctrl_power_info { |
| 86 | struct dsi_regulator_info digital; |
| 87 | struct dsi_regulator_info host_pwr; |
| 88 | }; |
| 89 | |
| 90 | /** |
| 91 | * struct dsi_ctrl_clk_info - clock information for DSI controller |
| 92 | * @core_clks: Core clocks needed to access DSI controller registers. |
| 93 | * @link_clks: Link clocks required to transmit data over DSI link. |
| 94 | * @rcg_clks: Root clock generation clocks generated in MMSS_CC. The |
| 95 | * output of the PLL is set as parent for these root |
| 96 | * clocks. These clocks are specific to controller |
| 97 | * instance. |
| 98 | * @mux_clks: Mux clocks used for Dynamic refresh feature. |
| 99 | * @ext_clks: External byte/pixel clocks from the MMSS block. These |
| 100 | * clocks are set as parent to rcg clocks. |
| 101 | * @pll_op_clks: TODO: |
| 102 | * @shadow_clks: TODO: |
| 103 | */ |
| 104 | struct dsi_ctrl_clk_info { |
| 105 | /* Clocks parsed from DT */ |
| 106 | struct dsi_core_clk_info core_clks; |
| 107 | struct dsi_link_clk_info link_clks; |
| 108 | struct dsi_clk_link_set rcg_clks; |
| 109 | |
| 110 | /* Clocks set by DSI Manager */ |
| 111 | struct dsi_clk_link_set mux_clks; |
| 112 | struct dsi_clk_link_set ext_clks; |
| 113 | struct dsi_clk_link_set pll_op_clks; |
| 114 | struct dsi_clk_link_set shadow_clks; |
| 115 | }; |
| 116 | |
| 117 | /** |
| 118 | * struct dsi_ctrl_bus_scale_info - Bus scale info for msm-bus bandwidth voting |
| 119 | * @bus_scale_table: Bus scale voting usecases. |
| 120 | * @bus_handle: Handle used for voting bandwidth. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 121 | */ |
| 122 | struct dsi_ctrl_bus_scale_info { |
| 123 | struct msm_bus_scale_pdata *bus_scale_table; |
| 124 | u32 bus_handle; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 125 | }; |
| 126 | |
| 127 | /** |
| 128 | * struct dsi_ctrl_state_info - current driver state information |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 129 | * @power_state: Status of power states on DSI controller. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 130 | * @cmd_engine_state: Status of DSI command engine. |
| 131 | * @vid_engine_state: Status of DSI video engine. |
| 132 | * @controller_state: Status of DSI Controller engine. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 133 | * @host_initialized: Boolean to indicate status of DSi host Initialization |
| 134 | * @tpg_enabled: Boolean to indicate whether tpg is enabled. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 135 | */ |
| 136 | struct dsi_ctrl_state_info { |
| 137 | enum dsi_power_state power_state; |
| 138 | enum dsi_engine_state cmd_engine_state; |
| 139 | enum dsi_engine_state vid_engine_state; |
| 140 | enum dsi_engine_state controller_state; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 141 | bool host_initialized; |
| 142 | bool tpg_enabled; |
| 143 | }; |
| 144 | |
| 145 | /** |
| 146 | * struct dsi_ctrl_interrupts - define interrupt information |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 147 | * @irq_lock: Spinlock for ISR handler. |
| 148 | * @irq_num: Linux interrupt number associated with device. |
| 149 | * @irq_stat_mask: Hardware mask of currently enabled interrupts. |
| 150 | * @irq_stat_refcount: Number of times each interrupt has been requested. |
| 151 | * @irq_stat_cb: Status IRQ callback definitions. |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 152 | * @irq_err_cb: IRQ callback definition to handle DSI ERRORs. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 153 | * @cmd_dma_done: Completion signal for DSI_CMD_MODE_DMA_DONE interrupt |
| 154 | * @vid_frame_done: Completion signal for DSI_VIDEO_MODE_FRAME_DONE int. |
| 155 | * @cmd_frame_done: Completion signal for DSI_CMD_FRAME_DONE interrupt. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 156 | */ |
| 157 | struct dsi_ctrl_interrupts { |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 158 | spinlock_t irq_lock; |
| 159 | int irq_num; |
| 160 | uint32_t irq_stat_mask; |
| 161 | int irq_stat_refcount[DSI_STATUS_INTERRUPT_COUNT]; |
| 162 | struct dsi_event_cb_info irq_stat_cb[DSI_STATUS_INTERRUPT_COUNT]; |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 163 | struct dsi_event_cb_info irq_err_cb; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 164 | |
| 165 | struct completion cmd_dma_done; |
| 166 | struct completion vid_frame_done; |
| 167 | struct completion cmd_frame_done; |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 168 | struct completion bta_done; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 169 | }; |
| 170 | |
| 171 | /** |
| 172 | * struct dsi_ctrl - DSI controller object |
| 173 | * @pdev: Pointer to platform device. |
Alexander Beykun | 32a6a18 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 174 | * @cell_index: Instance cell id. |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 175 | * @horiz_index: Index in physical horizontal CTRL layout, 0 = leftmost |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 176 | * @name: Name of the controller instance. |
| 177 | * @refcount: ref counter. |
| 178 | * @ctrl_lock: Mutex for hardware and object access. |
| 179 | * @drm_dev: Pointer to DRM device. |
| 180 | * @version: DSI controller version. |
| 181 | * @hw: DSI controller hardware object. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 182 | * @current_state: Current driver and hardware state. |
| 183 | * @clk_cb: Callback for DSI clock control. |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 184 | * @irq_info: Interrupt information. |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 185 | * @recovery_cb: Recovery call back to SDE. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 186 | * @clk_info: Clock information. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 187 | * @clk_freq: DSi Link clock frequency information. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 188 | * @pwr_info: Power information. |
| 189 | * @axi_bus_info: AXI bus information. |
| 190 | * @host_config: Current host configuration. |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 191 | * @mode_bounds: Boundaries of the default mode ROI. |
| 192 | * Origin is at top left of all CTRLs. |
| 193 | * @roi: Partial update region of interest. |
| 194 | * Origin is top left of this CTRL. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 195 | * @tx_cmd_buf: Tx command buffer. |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 196 | * @cmd_buffer_iova: cmd buffer mapped address. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 197 | * @cmd_buffer_size: Size of command buffer. |
Veera Sundaram Sankaran | d2a9394 | 2017-10-20 12:44:18 -0700 | [diff] [blame] | 198 | * @vaddr: CPU virtual address of cmd buffer. |
| 199 | * @secure_mode: Indicates if secure-session is in progress |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 200 | * @debugfs_root: Root for debugfs entries. |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 201 | * @misr_enable: Frame MISR enable/disable |
| 202 | * @misr_cache: Cached Frame MISR value |
Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 203 | * @phy_isolation_enabled: A boolean property allows to isolate the phy from |
| 204 | * dsi controller and run only dsi controller. |
Sravanthi Kollukuduru | d880932 | 2017-10-26 15:24:13 +0530 | [diff] [blame] | 205 | * @null_insertion_enabled: A boolean property to allow dsi controller to |
| 206 | * insert null packet. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 207 | */ |
| 208 | struct dsi_ctrl { |
| 209 | struct platform_device *pdev; |
Alexander Beykun | 32a6a18 | 2017-02-27 17:46:51 -0500 | [diff] [blame] | 210 | u32 cell_index; |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 211 | u32 horiz_index; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 212 | const char *name; |
| 213 | u32 refcount; |
| 214 | struct mutex ctrl_lock; |
| 215 | struct drm_device *drm_dev; |
| 216 | |
| 217 | enum dsi_ctrl_version version; |
| 218 | struct dsi_ctrl_hw hw; |
| 219 | |
| 220 | /* Current state */ |
| 221 | struct dsi_ctrl_state_info current_state; |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 222 | struct clk_ctrl_cb clk_cb; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 223 | |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 224 | struct dsi_ctrl_interrupts irq_info; |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 225 | struct dsi_event_cb_info recovery_cb; |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 226 | |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 227 | /* Clock and power states */ |
| 228 | struct dsi_ctrl_clk_info clk_info; |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 229 | struct link_clk_freq clk_freq; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 230 | struct dsi_ctrl_power_info pwr_info; |
| 231 | struct dsi_ctrl_bus_scale_info axi_bus_info; |
| 232 | |
| 233 | struct dsi_host_config host_config; |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 234 | struct dsi_rect mode_bounds; |
| 235 | struct dsi_rect roi; |
| 236 | |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 237 | /* Command tx and rx */ |
| 238 | struct drm_gem_object *tx_cmd_buf; |
| 239 | u32 cmd_buffer_size; |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 240 | u32 cmd_buffer_iova; |
Vara Reddy | 326612b | 2017-09-20 04:41:10 -0700 | [diff] [blame] | 241 | u32 cmd_len; |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 242 | void *vaddr; |
Veera Sundaram Sankaran | d2a9394 | 2017-10-20 12:44:18 -0700 | [diff] [blame] | 243 | u32 secure_mode; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 244 | |
| 245 | /* Debug Information */ |
| 246 | struct dentry *debugfs_root; |
| 247 | |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 248 | /* MISR */ |
| 249 | bool misr_enable; |
| 250 | u32 misr_cache; |
| 251 | |
Dhaval Patel | abfaa08 | 2017-07-28 12:41:10 -0700 | [diff] [blame] | 252 | bool phy_isolation_enabled; |
Sravanthi Kollukuduru | d880932 | 2017-10-26 15:24:13 +0530 | [diff] [blame] | 253 | bool null_insertion_enabled; |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 254 | }; |
| 255 | |
| 256 | /** |
| 257 | * dsi_ctrl_get() - get a dsi_ctrl handle from an of_node |
| 258 | * @of_node: of_node of the DSI controller. |
| 259 | * |
| 260 | * Gets the DSI controller handle for the corresponding of_node. The ref count |
| 261 | * is incremented to one and all subsequent gets will fail until the original |
| 262 | * clients calls a put. |
| 263 | * |
| 264 | * Return: DSI Controller handle. |
| 265 | */ |
| 266 | struct dsi_ctrl *dsi_ctrl_get(struct device_node *of_node); |
| 267 | |
| 268 | /** |
| 269 | * dsi_ctrl_put() - releases a dsi controller handle. |
| 270 | * @dsi_ctrl: DSI controller handle. |
| 271 | * |
| 272 | * Releases the DSI controller. Driver will clean up all resources and puts back |
| 273 | * the DSI controller into reset state. |
| 274 | */ |
| 275 | void dsi_ctrl_put(struct dsi_ctrl *dsi_ctrl); |
| 276 | |
| 277 | /** |
| 278 | * dsi_ctrl_drv_init() - initialize dsi controller driver. |
| 279 | * @dsi_ctrl: DSI controller handle. |
Ajay Singh Parmar | 48ea427 | 2016-06-27 11:44:34 -0700 | [diff] [blame] | 280 | * @parent: Parent directory for debug fs. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 281 | * |
| 282 | * Initializes DSI controller driver. Driver should be initialized after |
| 283 | * dsi_ctrl_get() succeeds. |
| 284 | * |
| 285 | * Return: error code. |
| 286 | */ |
Ajay Singh Parmar | 48ea427 | 2016-06-27 11:44:34 -0700 | [diff] [blame] | 287 | int dsi_ctrl_drv_init(struct dsi_ctrl *dsi_ctrl, struct dentry *parent); |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 288 | |
| 289 | /** |
| 290 | * dsi_ctrl_drv_deinit() - de-initializes dsi controller driver |
| 291 | * @dsi_ctrl: DSI controller handle. |
| 292 | * |
| 293 | * Releases all resources acquired by dsi_ctrl_drv_init(). |
| 294 | * |
| 295 | * Return: error code. |
| 296 | */ |
| 297 | int dsi_ctrl_drv_deinit(struct dsi_ctrl *dsi_ctrl); |
| 298 | |
| 299 | /** |
| 300 | * dsi_ctrl_validate_timing() - validate a video timing configuration |
| 301 | * @dsi_ctrl: DSI controller handle. |
| 302 | * @timing: Pointer to timing data. |
| 303 | * |
| 304 | * Driver will validate if the timing configuration is supported on the |
| 305 | * controller hardware. |
| 306 | * |
| 307 | * Return: error code if timing is not supported. |
| 308 | */ |
| 309 | int dsi_ctrl_validate_timing(struct dsi_ctrl *dsi_ctrl, |
| 310 | struct dsi_mode_info *timing); |
| 311 | |
| 312 | /** |
| 313 | * dsi_ctrl_update_host_config() - update dsi host configuration |
| 314 | * @dsi_ctrl: DSI controller handle. |
| 315 | * @config: DSI host configuration. |
Ajay Singh Parmar | 62f795b | 2016-06-10 23:20:23 -0700 | [diff] [blame] | 316 | * @flags: dsi_mode_flags modifying the behavior |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 317 | * @clk_handle: Clock handle for DSI clocks |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 318 | * |
| 319 | * Updates driver with new Host configuration to use for host initialization. |
| 320 | * This function call will only update the software context. The stored |
| 321 | * configuration information will be used when the host is initialized. |
| 322 | * |
| 323 | * Return: error code. |
| 324 | */ |
| 325 | int dsi_ctrl_update_host_config(struct dsi_ctrl *dsi_ctrl, |
Ajay Singh Parmar | 62f795b | 2016-06-10 23:20:23 -0700 | [diff] [blame] | 326 | struct dsi_host_config *config, |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 327 | int flags, void *clk_handle); |
Ajay Singh Parmar | 62f795b | 2016-06-10 23:20:23 -0700 | [diff] [blame] | 328 | |
| 329 | /** |
Raviteja Tamatam | 68892de | 2017-06-20 04:47:19 +0530 | [diff] [blame] | 330 | * dsi_ctrl_timing_db_update() - update only controller Timing DB |
| 331 | * @dsi_ctrl: DSI controller handle. |
| 332 | * @enable: Enable/disable Timing DB register |
| 333 | * |
| 334 | * Update timing db register value during dfps usecases |
| 335 | * |
| 336 | * Return: error code. |
| 337 | */ |
| 338 | int dsi_ctrl_timing_db_update(struct dsi_ctrl *dsi_ctrl, |
| 339 | bool enable); |
| 340 | |
| 341 | /** |
Ajay Singh Parmar | 62f795b | 2016-06-10 23:20:23 -0700 | [diff] [blame] | 342 | * dsi_ctrl_async_timing_update() - update only controller timing |
| 343 | * @dsi_ctrl: DSI controller handle. |
| 344 | * @timing: New DSI timing info |
| 345 | * |
| 346 | * Updates host timing values to asynchronously transition to new timing |
| 347 | * For example, to update the porch values in a seamless/dynamic fps switch. |
| 348 | * |
| 349 | * Return: error code. |
| 350 | */ |
| 351 | int dsi_ctrl_async_timing_update(struct dsi_ctrl *dsi_ctrl, |
| 352 | struct dsi_mode_info *timing); |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 353 | |
| 354 | /** |
| 355 | * dsi_ctrl_phy_sw_reset() - perform a PHY software reset |
| 356 | * @dsi_ctrl: DSI controller handle. |
| 357 | * |
| 358 | * Performs a PHY software reset on the DSI controller. Reset should be done |
| 359 | * when the controller power state is DSI_CTRL_POWER_CORE_CLK_ON and the PHY is |
| 360 | * not enabled. |
| 361 | * |
| 362 | * This function will fail if driver is in any other state. |
| 363 | * |
| 364 | * Return: error code. |
| 365 | */ |
| 366 | int dsi_ctrl_phy_sw_reset(struct dsi_ctrl *dsi_ctrl); |
| 367 | |
| 368 | /** |
Padmanabhan Komanduru | 8ee8ee5 | 2016-12-19 12:10:51 +0530 | [diff] [blame] | 369 | * dsi_ctrl_phy_reset_config() - Mask/unmask propagation of ahb reset signal |
| 370 | * to DSI PHY hardware. |
| 371 | * @dsi_ctrl: DSI controller handle. |
| 372 | * @enable: Mask/unmask the PHY reset signal. |
| 373 | * |
| 374 | * Return: error code. |
| 375 | */ |
| 376 | int dsi_ctrl_phy_reset_config(struct dsi_ctrl *dsi_ctrl, bool enable); |
| 377 | |
| 378 | /** |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 379 | * dsi_ctrl_soft_reset() - perform a soft reset on DSI controller |
| 380 | * @dsi_ctrl: DSI controller handle. |
| 381 | * |
| 382 | * The video, command and controller engines will be disabled before the |
| 383 | * reset is triggered. After, the engines will be re-enabled to the same state |
| 384 | * as before the reset. |
| 385 | * |
| 386 | * If the reset is done while MDP timing engine is turned on, the video |
| 387 | * engine should be re-enabled only during the vertical blanking time. |
| 388 | * |
| 389 | * Return: error code |
| 390 | */ |
| 391 | int dsi_ctrl_soft_reset(struct dsi_ctrl *dsi_ctrl); |
| 392 | |
| 393 | /** |
Jeykumar Sankaran | a7c7bbe | 2017-05-31 18:12:05 -0700 | [diff] [blame] | 394 | * dsi_ctrl_host_timing_update - reinitialize host with new timing values |
| 395 | * @dsi_ctrl: DSI controller handle. |
| 396 | * |
| 397 | * Reinitialize DSI controller hardware with new display timing values |
| 398 | * when resolution is switched dynamically. |
| 399 | * |
| 400 | * Return: error code |
| 401 | */ |
| 402 | int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl); |
| 403 | |
| 404 | /** |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 405 | * dsi_ctrl_host_init() - Initialize DSI host hardware. |
| 406 | * @dsi_ctrl: DSI controller handle. |
Shashank Babu Chinta Venkata | 7d60873 | 2017-05-31 14:10:26 -0700 | [diff] [blame] | 407 | * @is_splash_enabled: boolean signifying splash status. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 408 | * |
| 409 | * Initializes DSI controller hardware with host configuration provided by |
| 410 | * dsi_ctrl_update_host_config(). Initialization can be performed only during |
| 411 | * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been |
| 412 | * performed. |
| 413 | * |
| 414 | * Return: error code. |
| 415 | */ |
Shashank Babu Chinta Venkata | 7d60873 | 2017-05-31 14:10:26 -0700 | [diff] [blame] | 416 | int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool is_splash_enabled); |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 417 | |
| 418 | /** |
| 419 | * dsi_ctrl_host_deinit() - De-Initialize DSI host hardware. |
| 420 | * @dsi_ctrl: DSI controller handle. |
| 421 | * |
| 422 | * De-initializes DSI controller hardware. It can be performed only during |
| 423 | * DSI_CTRL_POWER_CORE_CLK_ON state after LINK clocks have been turned off. |
| 424 | * |
| 425 | * Return: error code. |
| 426 | */ |
| 427 | int dsi_ctrl_host_deinit(struct dsi_ctrl *dsi_ctrl); |
| 428 | |
| 429 | /** |
Shashank Babu Chinta Venkata | 8210952 | 2017-05-09 18:59:21 -0700 | [diff] [blame] | 430 | * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes. |
| 431 | * @dsi_ctrl: DSI controller handle. |
| 432 | * @enable: enable/disable ULPS. |
| 433 | * |
| 434 | * ULPS can be enabled/disabled after DSI host engine is turned on. |
| 435 | * |
| 436 | * Return: error code. |
| 437 | */ |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 438 | int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable); |
| 439 | |
| 440 | /** |
| 441 | * dsi_ctrl_setup() - Setup DSI host hardware while coming out of idle screen. |
| 442 | * @dsi_ctrl: DSI controller handle. |
| 443 | * |
| 444 | * Initializes DSI controller hardware with host configuration provided by |
| 445 | * dsi_ctrl_update_host_config(). Initialization can be performed only during |
| 446 | * DSI_CTRL_POWER_CORE_CLK_ON state and after the PHY SW reset has been |
| 447 | * performed. |
| 448 | * |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 449 | * Also used to program the video mode timing values. |
| 450 | * |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 451 | * Return: error code. |
| 452 | */ |
| 453 | int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl); |
| 454 | |
| 455 | /** |
Lloyd Atkinson | e53b737 | 2017-03-22 17:16:47 -0400 | [diff] [blame] | 456 | * dsi_ctrl_set_roi() - Set DSI controller's region of interest |
| 457 | * @dsi_ctrl: DSI controller handle. |
| 458 | * @roi: Region of interest rectangle, must be less than mode bounds |
| 459 | * @changed: Output parameter, set to true of the controller's ROI was |
| 460 | * dirtied by setting the new ROI, and DCS cmd update needed |
| 461 | * |
| 462 | * Return: error code. |
| 463 | */ |
| 464 | int dsi_ctrl_set_roi(struct dsi_ctrl *dsi_ctrl, struct dsi_rect *roi, |
| 465 | bool *changed); |
| 466 | |
| 467 | /** |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 468 | * dsi_ctrl_set_tpg_state() - enable/disable test pattern on the controller |
| 469 | * @dsi_ctrl: DSI controller handle. |
| 470 | * @on: enable/disable test pattern. |
| 471 | * |
| 472 | * Test pattern can be enabled only after Video engine (for video mode panels) |
| 473 | * or command engine (for cmd mode panels) is enabled. |
| 474 | * |
| 475 | * Return: error code. |
| 476 | */ |
| 477 | int dsi_ctrl_set_tpg_state(struct dsi_ctrl *dsi_ctrl, bool on); |
| 478 | |
| 479 | /** |
| 480 | * dsi_ctrl_cmd_transfer() - Transfer commands on DSI link |
| 481 | * @dsi_ctrl: DSI controller handle. |
| 482 | * @msg: Message to transfer on DSI link. |
| 483 | * @flags: Modifiers for message transfer. |
| 484 | * |
| 485 | * Command transfer can be done only when command engine is enabled. The |
| 486 | * transfer API will until either the command transfer finishes or the timeout |
| 487 | * value is reached. If the trigger is deferred, it will return without |
| 488 | * triggering the transfer. Command parameters are programmed to hardware. |
| 489 | * |
| 490 | * Return: error code. |
| 491 | */ |
| 492 | int dsi_ctrl_cmd_transfer(struct dsi_ctrl *dsi_ctrl, |
| 493 | const struct mipi_dsi_msg *msg, |
| 494 | u32 flags); |
| 495 | |
| 496 | /** |
| 497 | * dsi_ctrl_cmd_tx_trigger() - Trigger a deferred command. |
| 498 | * @dsi_ctrl: DSI controller handle. |
| 499 | * @flags: Modifiers. |
| 500 | * |
| 501 | * Return: error code. |
| 502 | */ |
| 503 | int dsi_ctrl_cmd_tx_trigger(struct dsi_ctrl *dsi_ctrl, u32 flags); |
| 504 | |
| 505 | /** |
Shashank Babu Chinta Venkata | 7d60873 | 2017-05-31 14:10:26 -0700 | [diff] [blame] | 506 | * dsi_ctrl_update_host_engine_state_for_cont_splash() - update engine |
| 507 | * states for cont splash usecase |
| 508 | * @dsi_ctrl: DSI controller handle. |
| 509 | * @state: DSI engine state |
| 510 | * |
| 511 | * Return: error code. |
| 512 | */ |
| 513 | int dsi_ctrl_update_host_engine_state_for_cont_splash(struct dsi_ctrl *dsi_ctrl, |
| 514 | enum dsi_engine_state state); |
| 515 | |
| 516 | /** |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 517 | * dsi_ctrl_set_power_state() - set power state for dsi controller |
| 518 | * @dsi_ctrl: DSI controller handle. |
| 519 | * @state: Power state. |
| 520 | * |
| 521 | * Set power state for DSI controller. Power state can be changed only when |
| 522 | * Controller, Video and Command engines are turned off. |
| 523 | * |
| 524 | * Return: error code. |
| 525 | */ |
| 526 | int dsi_ctrl_set_power_state(struct dsi_ctrl *dsi_ctrl, |
| 527 | enum dsi_power_state state); |
| 528 | |
| 529 | /** |
| 530 | * dsi_ctrl_set_cmd_engine_state() - set command engine state |
| 531 | * @dsi_ctrl: DSI Controller handle. |
| 532 | * @state: Engine state. |
| 533 | * |
| 534 | * Command engine state can be modified only when DSI controller power state is |
| 535 | * set to DSI_CTRL_POWER_LINK_CLK_ON. |
| 536 | * |
| 537 | * Return: error code. |
| 538 | */ |
| 539 | int dsi_ctrl_set_cmd_engine_state(struct dsi_ctrl *dsi_ctrl, |
| 540 | enum dsi_engine_state state); |
| 541 | |
| 542 | /** |
| 543 | * dsi_ctrl_set_vid_engine_state() - set video engine state |
| 544 | * @dsi_ctrl: DSI Controller handle. |
| 545 | * @state: Engine state. |
| 546 | * |
| 547 | * Video engine state can be modified only when DSI controller power state is |
| 548 | * set to DSI_CTRL_POWER_LINK_CLK_ON. |
| 549 | * |
| 550 | * Return: error code. |
| 551 | */ |
| 552 | int dsi_ctrl_set_vid_engine_state(struct dsi_ctrl *dsi_ctrl, |
| 553 | enum dsi_engine_state state); |
| 554 | |
| 555 | /** |
| 556 | * dsi_ctrl_set_host_engine_state() - set host engine state |
| 557 | * @dsi_ctrl: DSI Controller handle. |
| 558 | * @state: Engine state. |
| 559 | * |
| 560 | * Host engine state can be modified only when DSI controller power state is |
| 561 | * set to DSI_CTRL_POWER_LINK_CLK_ON and cmd, video engines are disabled. |
| 562 | * |
| 563 | * Return: error code. |
| 564 | */ |
| 565 | int dsi_ctrl_set_host_engine_state(struct dsi_ctrl *dsi_ctrl, |
| 566 | enum dsi_engine_state state); |
| 567 | |
| 568 | /** |
| 569 | * dsi_ctrl_set_ulps() - set ULPS state for DSI lanes. |
| 570 | * @dsi_ctrl: DSI controller handle. |
| 571 | * @enable: enable/disable ULPS. |
| 572 | * |
| 573 | * ULPS can be enabled/disabled after DSI host engine is turned on. |
| 574 | * |
| 575 | * Return: error code. |
| 576 | */ |
| 577 | int dsi_ctrl_set_ulps(struct dsi_ctrl *dsi_ctrl, bool enable); |
| 578 | |
| 579 | /** |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 580 | * dsi_ctrl_clk_cb_register() - Register DSI controller clk control callback |
| 581 | * @dsi_ctrl: DSI controller handle. |
| 582 | * @clk__cb: Structure containing callback for clock control. |
| 583 | * |
| 584 | * Register call for DSI clock control |
| 585 | * |
| 586 | * Return: error code. |
| 587 | */ |
| 588 | int dsi_ctrl_clk_cb_register(struct dsi_ctrl *dsi_ctrl, |
| 589 | struct clk_ctrl_cb *clk_cb); |
| 590 | |
| 591 | /** |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 592 | * dsi_ctrl_set_clamp_state() - set clamp state for DSI phy |
| 593 | * @dsi_ctrl: DSI controller handle. |
| 594 | * @enable: enable/disable clamping. |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 595 | * @ulps_enabled: ulps state. |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 596 | * |
| 597 | * Clamps can be enabled/disabled while DSI contoller is still turned on. |
| 598 | * |
| 599 | * Return: error code. |
| 600 | */ |
Padmanabhan Komanduru | dbd2fb0 | 2016-12-02 15:18:49 +0530 | [diff] [blame] | 601 | int dsi_ctrl_set_clamp_state(struct dsi_ctrl *dsi_Ctrl, |
| 602 | bool enable, bool ulps_enabled); |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 603 | |
| 604 | /** |
| 605 | * dsi_ctrl_set_clock_source() - set clock source fpr dsi link clocks |
| 606 | * @dsi_ctrl: DSI controller handle. |
| 607 | * @source_clks: Source clocks for DSI link clocks. |
| 608 | * |
| 609 | * Clock source should be changed while link clocks are disabled. |
| 610 | * |
| 611 | * Return: error code. |
| 612 | */ |
| 613 | int dsi_ctrl_set_clock_source(struct dsi_ctrl *dsi_ctrl, |
| 614 | struct dsi_clk_link_set *source_clks); |
| 615 | |
| 616 | /** |
Clarence Ip | 80ada7f | 2017-05-04 09:55:21 -0700 | [diff] [blame] | 617 | * dsi_ctrl_enable_status_interrupt() - enable status interrupts |
| 618 | * @dsi_ctrl: DSI controller handle. |
| 619 | * @intr_idx: Index interrupt to disable. |
| 620 | * @event_info: Pointer to event callback definition |
| 621 | */ |
| 622 | void dsi_ctrl_enable_status_interrupt(struct dsi_ctrl *dsi_ctrl, |
| 623 | uint32_t intr_idx, struct dsi_event_cb_info *event_info); |
| 624 | |
| 625 | /** |
| 626 | * dsi_ctrl_disable_status_interrupt() - disable status interrupts |
| 627 | * @dsi_ctrl: DSI controller handle. |
| 628 | * @intr_idx: Index interrupt to disable. |
| 629 | */ |
| 630 | void dsi_ctrl_disable_status_interrupt( |
| 631 | struct dsi_ctrl *dsi_ctrl, uint32_t intr_idx); |
| 632 | |
| 633 | /** |
Rajkumar Subbiah | 01e6dd64 | 2017-07-05 14:47:47 -0400 | [diff] [blame] | 634 | * dsi_ctrl_setup_misr() - Setup frame MISR |
| 635 | * @dsi_ctrl: DSI controller handle. |
| 636 | * @enable: enable/disable MISR. |
| 637 | * @frame_count: Number of frames to accumulate MISR. |
| 638 | * |
| 639 | * Return: error code. |
| 640 | */ |
| 641 | int dsi_ctrl_setup_misr(struct dsi_ctrl *dsi_ctrl, |
| 642 | bool enable, |
| 643 | u32 frame_count); |
| 644 | |
| 645 | /** |
| 646 | * dsi_ctrl_collect_misr() - Read frame MISR |
| 647 | * @dsi_ctrl: DSI controller handle. |
| 648 | * |
| 649 | * Return: MISR value. |
| 650 | */ |
| 651 | u32 dsi_ctrl_collect_misr(struct dsi_ctrl *dsi_ctrl); |
| 652 | |
| 653 | /** |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 654 | * dsi_ctrl_drv_register() - register platform driver for dsi controller |
| 655 | */ |
| 656 | void dsi_ctrl_drv_register(void); |
| 657 | |
| 658 | /** |
| 659 | * dsi_ctrl_drv_unregister() - unregister platform driver |
| 660 | */ |
| 661 | void dsi_ctrl_drv_unregister(void); |
| 662 | |
Sandeep Panda | 11b20d8 | 2017-06-19 12:57:27 +0530 | [diff] [blame] | 663 | /** |
| 664 | * dsi_ctrl_reset() - Reset DSI PHY CLK/DATA lane |
| 665 | * @dsi_ctrl: DSI controller handle. |
| 666 | * @mask: Mask to indicate if CLK and/or DATA lane needs reset. |
| 667 | */ |
| 668 | int dsi_ctrl_reset(struct dsi_ctrl *dsi_ctrl, int mask); |
| 669 | |
| 670 | /** |
| 671 | * dsi_ctrl_get_hw_version() - read dsi controller hw revision |
| 672 | * @dsi_ctrl: DSI controller handle. |
| 673 | */ |
| 674 | int dsi_ctrl_get_hw_version(struct dsi_ctrl *dsi_ctrl); |
| 675 | |
| 676 | /** |
| 677 | * dsi_ctrl_vid_engine_en() - Control DSI video engine HW state |
| 678 | * @dsi_ctrl: DSI controller handle. |
| 679 | * @on: variable to control video engine ON/OFF. |
| 680 | */ |
| 681 | int dsi_ctrl_vid_engine_en(struct dsi_ctrl *dsi_ctrl, bool on); |
| 682 | |
Ajay Singh Parmar | 5c6b486 | 2016-06-22 17:31:21 -0700 | [diff] [blame] | 683 | #endif /* _DSI_CTRL_H_ */ |