Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #ifndef _SDE_RSC_PRIV_H_ |
| 15 | #define _SDE_RSC_PRIV_H_ |
| 16 | |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/sde_io_util.h> |
| 19 | #include <linux/sde_rsc.h> |
| 20 | |
| 21 | #include <soc/qcom/tcs.h> |
| 22 | #include "sde_power_handle.h" |
| 23 | |
| 24 | #define SDE_RSC_COMPATIBLE "disp_rscc" |
| 25 | |
| 26 | #define MAX_RSC_COUNT 5 |
| 27 | |
Dhaval Patel | 3d56f89 | 2017-05-05 12:21:08 -0700 | [diff] [blame] | 28 | #define ALL_MODES_DISABLED 0x0 |
| 29 | #define ONLY_MODE_0_ENABLED 0x1 |
| 30 | #define ONLY_MODE_0_1_ENABLED 0x3 |
| 31 | #define ALL_MODES_ENABLED 0x7 |
| 32 | |
| 33 | #define MAX_COUNT_SIZE_SUPPORTED 128 |
| 34 | |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 35 | struct sde_rsc_priv; |
| 36 | |
| 37 | /** |
| 38 | * rsc_mode_req: sde rsc mode request information |
| 39 | * MODE_READ: read vsync status |
Dhaval Patel | 3d56f89 | 2017-05-05 12:21:08 -0700 | [diff] [blame] | 40 | * MODE_UPDATE: mode timeslot update |
| 41 | * 0x0: all modes are disabled. |
| 42 | * 0x1: Mode-0 is enabled and other two modes are disabled. |
| 43 | * 0x3: Mode-0 & Mode-1 are enabled and mode-2 is disabled. |
| 44 | * 0x7: all modes are enabled. |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 45 | */ |
| 46 | enum rsc_mode_req { |
| 47 | MODE_READ, |
Dhaval Patel | 3d56f89 | 2017-05-05 12:21:08 -0700 | [diff] [blame] | 48 | MODE_UPDATE = 0x1, |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 49 | }; |
| 50 | |
| 51 | /** |
| 52 | * rsc_vsync_req: sde rsc vsync request information |
| 53 | * VSYNC_READ: read vsync status |
Lloyd Atkinson | f68a213 | 2017-07-17 10:16:30 -0400 | [diff] [blame] | 54 | * VSYNC_READ_VSYNC0: read value vsync0 timestamp (cast to int from u32) |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 55 | * VSYNC_ENABLE: enable rsc wrapper vsync status |
| 56 | * VSYNC_DISABLE: disable rsc wrapper vsync status |
| 57 | */ |
| 58 | enum rsc_vsync_req { |
| 59 | VSYNC_READ, |
Lloyd Atkinson | f68a213 | 2017-07-17 10:16:30 -0400 | [diff] [blame] | 60 | VSYNC_READ_VSYNC0, |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 61 | VSYNC_ENABLE, |
| 62 | VSYNC_DISABLE, |
| 63 | }; |
| 64 | |
| 65 | /** |
| 66 | * struct sde_rsc_hw_ops - sde resource state coordinator hardware ops |
| 67 | * @init: Initialize the sequencer, solver, qtimer, |
| 68 | etc. hardware blocks on RSC. |
Dhaval Patel | f9c5c60 | 2017-08-01 12:32:04 -0700 | [diff] [blame] | 69 | * @timer_update: update the static wrapper time and pdc/rsc |
| 70 | backoff time. |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 71 | * @tcs_wait: Waits for TCS block OK to allow sending a |
| 72 | * TCS command. |
| 73 | * @hw_vsync: Enables the vsync on RSC block. |
| 74 | * @tcs_use_ok: set TCS set to high to allow RSC to use it. |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 75 | * @is_amc_mode: Check current amc mode status |
Dhaval Patel | c5a2e5d | 2017-09-18 12:39:41 -0700 | [diff] [blame] | 76 | * @debug_dump: dump debug bus registers or enable debug bus |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 77 | * @state_update: Enable/override the solver based on rsc state |
| 78 | * status (command/video) |
| 79 | * @mode_show: shows current mode status, mode0/1/2 |
| 80 | * @debug_show: Show current debug status. |
| 81 | */ |
| 82 | |
| 83 | struct sde_rsc_hw_ops { |
| 84 | int (*init)(struct sde_rsc_priv *rsc); |
Dhaval Patel | f9c5c60 | 2017-08-01 12:32:04 -0700 | [diff] [blame] | 85 | int (*timer_update)(struct sde_rsc_priv *rsc); |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 86 | int (*tcs_wait)(struct sde_rsc_priv *rsc); |
| 87 | int (*hw_vsync)(struct sde_rsc_priv *rsc, enum rsc_vsync_req request, |
| 88 | char *buffer, int buffer_size, u32 mode); |
| 89 | int (*tcs_use_ok)(struct sde_rsc_priv *rsc); |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 90 | bool (*is_amc_mode)(struct sde_rsc_priv *rsc); |
Dhaval Patel | c5a2e5d | 2017-09-18 12:39:41 -0700 | [diff] [blame] | 91 | void (*debug_dump)(struct sde_rsc_priv *rsc, u32 mux_sel); |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 92 | int (*state_update)(struct sde_rsc_priv *rsc, enum sde_rsc_state state); |
| 93 | int (*debug_show)(struct seq_file *s, struct sde_rsc_priv *rsc); |
| 94 | int (*mode_ctrl)(struct sde_rsc_priv *rsc, enum rsc_mode_req request, |
Dhaval Patel | 3d56f89 | 2017-05-05 12:21:08 -0700 | [diff] [blame] | 95 | char *buffer, int buffer_size, u32 mode); |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 96 | }; |
| 97 | |
| 98 | /** |
| 99 | * struct sde_rsc_timer_config: this is internal configuration between |
| 100 | * rsc and rsc_hw API. |
| 101 | * |
| 102 | * @static_wakeup_time_ns: wrapper backoff time in nano seconds |
| 103 | * @rsc_backoff_time_ns: rsc backoff time in nano seconds |
| 104 | * @pdc_backoff_time_ns: pdc backoff time in nano seconds |
| 105 | * @rsc_mode_threshold_time_ns: rsc mode threshold time in nano seconds |
| 106 | * @rsc_time_slot_0_ns: mode-0 time slot threshold in nano seconds |
| 107 | * @rsc_time_slot_1_ns: mode-1 time slot threshold in nano seconds |
| 108 | * @rsc_time_slot_2_ns: mode-2 time slot threshold in nano seconds |
| 109 | */ |
| 110 | struct sde_rsc_timer_config { |
| 111 | u32 static_wakeup_time_ns; |
| 112 | |
| 113 | u32 rsc_backoff_time_ns; |
| 114 | u32 pdc_backoff_time_ns; |
| 115 | u32 rsc_mode_threshold_time_ns; |
| 116 | u32 rsc_time_slot_0_ns; |
| 117 | u32 rsc_time_slot_1_ns; |
| 118 | u32 rsc_time_slot_2_ns; |
| 119 | }; |
| 120 | |
| 121 | /** |
| 122 | * struct sde_rsc_priv: sde resource state coordinator(rsc) private handle |
| 123 | * @version: rsc sequence version |
| 124 | * @phandle: module power handle for clocks |
| 125 | * @pclient: module power client of phandle |
| 126 | * @fs: "MDSS GDSC" handle |
| 127 | * |
Dhaval Patel | d2dd1ad | 2017-03-29 16:13:17 -0700 | [diff] [blame] | 128 | * @disp_rsc: display rsc handle |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 129 | * @drv_io: sde drv io data mapping |
| 130 | * @wrapper_io: wrapper io data mapping |
| 131 | * |
| 132 | * @client_list: current rsc client list handle |
| 133 | * @event_list: current rsc event list handle |
| 134 | * @client_lock: current rsc client synchronization lock |
| 135 | * |
| 136 | * timer_config: current rsc timer configuration |
| 137 | * cmd_config: current panel config |
| 138 | * current_state: current rsc state (video/command), solver |
| 139 | * override/enabled. |
| 140 | * debug_mode: enables the logging for each register read/write |
| 141 | * debugfs_root: debugfs file system root node |
| 142 | * |
| 143 | * hw_ops: sde rsc hardware operations |
| 144 | * power_collapse: if all clients are in IDLE state then it enters in |
| 145 | * mode2 state and enable the power collapse state |
| 146 | * power_collapse_block:By default, rsc move to mode-2 if all clients are in |
| 147 | * invalid state. It can be blocked by this boolean entry. |
| 148 | * primary_client: A client which is allowed to make command state request |
| 149 | * and ab/ib vote on display rsc |
| 150 | * master_drm: Primary client waits for vsync on this drm object based |
| 151 | * on crtc id |
| 152 | */ |
| 153 | struct sde_rsc_priv { |
| 154 | u32 version; |
| 155 | struct sde_power_handle phandle; |
| 156 | struct sde_power_client *pclient; |
| 157 | struct regulator *fs; |
| 158 | |
Dhaval Patel | d2dd1ad | 2017-03-29 16:13:17 -0700 | [diff] [blame] | 159 | struct rpmh_client *disp_rsc; |
Dhaval Patel | 49ef6d7 | 2017-03-26 09:35:53 -0700 | [diff] [blame] | 160 | struct dss_io_data drv_io; |
| 161 | struct dss_io_data wrapper_io; |
| 162 | |
| 163 | struct list_head client_list; |
| 164 | struct list_head event_list; |
| 165 | struct mutex client_lock; |
| 166 | |
| 167 | struct sde_rsc_timer_config timer_config; |
| 168 | struct sde_rsc_cmd_config cmd_config; |
| 169 | u32 current_state; |
| 170 | |
| 171 | u32 debug_mode; |
| 172 | struct dentry *debugfs_root; |
| 173 | |
| 174 | struct sde_rsc_hw_ops hw_ops; |
| 175 | bool power_collapse; |
| 176 | bool power_collapse_block; |
| 177 | struct sde_rsc_client *primary_client; |
| 178 | |
| 179 | struct drm_device *master_drm; |
| 180 | }; |
| 181 | |
| 182 | /** |
| 183 | * sde_rsc_hw_register() - register hardware API |
| 184 | * |
| 185 | * @client: Client pointer provided by sde_rsc_client_create(). |
| 186 | * |
| 187 | * Return: error code. |
| 188 | */ |
| 189 | int sde_rsc_hw_register(struct sde_rsc_priv *rsc); |
| 190 | |
| 191 | #endif /* _SDE_RSC_PRIV_H_ */ |