blob: 063099d48839943a98faadaed0957083bfc8fa1d [file] [log] [blame]
Mike Rapoport22caf042006-07-14 00:24:34 -07001#ifndef __REGS_2700G_
2#define __REGS_2700G_
3
4/* extern unsigned long virt_base_2700; */
5/* #define __REG_2700G(x) (*(volatile unsigned long*)((x)+virt_base_2700)) */
6#define __REG_2700G(x) ((x)+virt_base_2700)
7
8/* System Configuration Registers (0x0000_0000 0x0000_0010) */
9#define SYSCFG __REG_2700G(0x00000000)
10#define PFBASE __REG_2700G(0x00000004)
11#define PFCEIL __REG_2700G(0x00000008)
12#define POLLFLAG __REG_2700G(0x0000000c)
13#define SYSRST __REG_2700G(0x00000010)
14
15/* Interrupt Control Registers (0x0000_0014 0x0000_002F) */
16#define NINTPW __REG_2700G(0x00000014)
17#define MINTENABLE __REG_2700G(0x00000018)
18#define MINTSTAT __REG_2700G(0x0000001c)
19#define SINTENABLE __REG_2700G(0x00000020)
20#define SINTSTAT __REG_2700G(0x00000024)
21#define SINTCLR __REG_2700G(0x00000028)
22
23/* Clock Control Registers (0x0000_002C 0x0000_005F) */
24#define SYSCLKSRC __REG_2700G(0x0000002c)
25#define PIXCLKSRC __REG_2700G(0x00000030)
26#define CLKSLEEP __REG_2700G(0x00000034)
27#define COREPLL __REG_2700G(0x00000038)
28#define DISPPLL __REG_2700G(0x0000003c)
29#define PLLSTAT __REG_2700G(0x00000040)
30#define VOVRCLK __REG_2700G(0x00000044)
31#define PIXCLK __REG_2700G(0x00000048)
32#define MEMCLK __REG_2700G(0x0000004c)
Raphael Assenatba282da2007-10-16 01:28:40 -070033#define M24CLK __REG_2700G(0x00000050)
Mike Rapoport22caf042006-07-14 00:24:34 -070034#define MBXCLK __REG_2700G(0x00000054)
35#define SDCLK __REG_2700G(0x00000058)
36#define PIXCLKDIV __REG_2700G(0x0000005c)
37
38/* LCD Port Control Register (0x0000_0060 0x0000_006F) */
39#define LCD_CONFIG __REG_2700G(0x00000060)
40
41/* On-Die Frame Buffer Registers (0x0000_0064 0x0000_006B) */
42#define ODFBPWR __REG_2700G(0x00000064)
43#define ODFBSTAT __REG_2700G(0x00000068)
44
45/* GPIO Registers (0x0000_006C 0x0000_007F) */
46#define GPIOCGF __REG_2700G(0x0000006c)
47#define GPIOHI __REG_2700G(0x00000070)
48#define GPIOLO __REG_2700G(0x00000074)
49#define GPIOSTAT __REG_2700G(0x00000078)
50
51/* Pulse Width Modulator (PWM) Registers (0x0000_0200 0x0000_02FF) */
52#define PWMRST __REG_2700G(0x00000200)
53#define PWMCFG __REG_2700G(0x00000204)
54#define PWM0DIV __REG_2700G(0x00000210)
55#define PWM0DUTY __REG_2700G(0x00000214)
56#define PWM0PER __REG_2700G(0x00000218)
57#define PWM1DIV __REG_2700G(0x00000220)
58#define PWM1DUTY __REG_2700G(0x00000224)
59#define PWM1PER __REG_2700G(0x00000228)
60
61/* Identification (ID) Registers (0x0000_0300 0x0000_0FFF) */
62#define ID __REG_2700G(0x00000FF0)
63
64/* Local Memory (SDRAM) Interface Registers (0x0000_1000 0x0000_1FFF) */
65#define LMRST __REG_2700G(0x00001000)
66#define LMCFG __REG_2700G(0x00001004)
67#define LMPWR __REG_2700G(0x00001008)
68#define LMPWRSTAT __REG_2700G(0x0000100c)
69#define LMCEMR __REG_2700G(0x00001010)
70#define LMTYPE __REG_2700G(0x00001014)
71#define LMTIM __REG_2700G(0x00001018)
72#define LMREFRESH __REG_2700G(0x0000101c)
73#define LMPROTMIN __REG_2700G(0x00001020)
74#define LMPROTMAX __REG_2700G(0x00001024)
75#define LMPROTCFG __REG_2700G(0x00001028)
76#define LMPROTERR __REG_2700G(0x0000102c)
77
78/* Plane Controller Registers (0x0000_2000 0x0000_2FFF) */
79#define GSCTRL __REG_2700G(0x00002000)
80#define VSCTRL __REG_2700G(0x00002004)
81#define GBBASE __REG_2700G(0x00002020)
82#define VBBASE __REG_2700G(0x00002024)
83#define GDRCTRL __REG_2700G(0x00002040)
84#define VCMSK __REG_2700G(0x00002044)
85#define GSCADR __REG_2700G(0x00002060)
86#define VSCADR __REG_2700G(0x00002064)
87#define VUBASE __REG_2700G(0x00002084)
88#define VVBASE __REG_2700G(0x000020a4)
89#define GSADR __REG_2700G(0x000020c0)
90#define VSADR __REG_2700G(0x000020c4)
91#define HCCTRL __REG_2700G(0x00002100)
92#define HCSIZE __REG_2700G(0x00002110)
93#define HCPOS __REG_2700G(0x00002120)
94#define HCBADR __REG_2700G(0x00002130)
95#define HCCKMSK __REG_2700G(0x00002140)
96#define GPLUT __REG_2700G(0x00002150)
97#define DSCTRL __REG_2700G(0x00002154)
98#define DHT01 __REG_2700G(0x00002158)
99#define DHT02 __REG_2700G(0x0000215c)
100#define DHT03 __REG_2700G(0x00002160)
101#define DVT01 __REG_2700G(0x00002164)
102#define DVT02 __REG_2700G(0x00002168)
103#define DVT03 __REG_2700G(0x0000216c)
104#define DBCOL __REG_2700G(0x00002170)
105#define BGCOLOR __REG_2700G(0x00002174)
106#define DINTRS __REG_2700G(0x00002178)
107#define DINTRE __REG_2700G(0x0000217c)
108#define DINTRCNT __REG_2700G(0x00002180)
109#define DSIG __REG_2700G(0x00002184)
110#define DMCTRL __REG_2700G(0x00002188)
111#define CLIPCTRL __REG_2700G(0x0000218c)
112#define SPOCTRL __REG_2700G(0x00002190)
113#define SVCTRL __REG_2700G(0x00002194)
114
115/* 0x0000_2198 */
116/* 0x0000_21A8 VSCOEFF[0:4] Video Scalar Vertical Coefficient [0:4] 4.14.5 */
117#define VSCOEFF0 __REG_2700G(0x00002198)
118#define VSCOEFF1 __REG_2700G(0x0000219c)
119#define VSCOEFF2 __REG_2700G(0x000021a0)
120#define VSCOEFF3 __REG_2700G(0x000021a4)
121#define VSCOEFF4 __REG_2700G(0x000021a8)
122
123#define SHCTRL __REG_2700G(0x000021b0)
124
125/* 0x0000_21B4 */
126/* 0x0000_21D4 HSCOEFF[0:8] Video Scalar Horizontal Coefficient [0:8] 4.14.7 */
127#define HSCOEFF0 __REG_2700G(0x000021b4)
128#define HSCOEFF1 __REG_2700G(0x000021b8)
129#define HSCOEFF2 __REG_2700G(0x000021bc)
Raphael Assenatce7405f2006-12-08 02:40:33 -0800130#define HSCOEFF3 __REG_2700G(0x000021c0)
Mike Rapoport22caf042006-07-14 00:24:34 -0700131#define HSCOEFF4 __REG_2700G(0x000021c4)
132#define HSCOEFF5 __REG_2700G(0x000021c8)
133#define HSCOEFF6 __REG_2700G(0x000021cc)
134#define HSCOEFF7 __REG_2700G(0x000021d0)
135#define HSCOEFF8 __REG_2700G(0x000021d4)
136
137#define SSSIZE __REG_2700G(0x000021D8)
138
139/* 0x0000_2200 */
140/* 0x0000_2240 VIDGAM[0:16] Video Gamma LUT Index [0:16] 4.15.2 */
141#define VIDGAM0 __REG_2700G(0x00002200)
142#define VIDGAM1 __REG_2700G(0x00002204)
143#define VIDGAM2 __REG_2700G(0x00002208)
144#define VIDGAM3 __REG_2700G(0x0000220c)
145#define VIDGAM4 __REG_2700G(0x00002210)
146#define VIDGAM5 __REG_2700G(0x00002214)
147#define VIDGAM6 __REG_2700G(0x00002218)
148#define VIDGAM7 __REG_2700G(0x0000221c)
149#define VIDGAM8 __REG_2700G(0x00002220)
150#define VIDGAM9 __REG_2700G(0x00002224)
151#define VIDGAM10 __REG_2700G(0x00002228)
152#define VIDGAM11 __REG_2700G(0x0000222c)
153#define VIDGAM12 __REG_2700G(0x00002230)
154#define VIDGAM13 __REG_2700G(0x00002234)
155#define VIDGAM14 __REG_2700G(0x00002238)
156#define VIDGAM15 __REG_2700G(0x0000223c)
157#define VIDGAM16 __REG_2700G(0x00002240)
158
159/* 0x0000_2250 */
160/* 0x0000_2290 GFXGAM[0:16] Graphics Gamma LUT Index [0:16] 4.15.3 */
161#define GFXGAM0 __REG_2700G(0x00002250)
162#define GFXGAM1 __REG_2700G(0x00002254)
163#define GFXGAM2 __REG_2700G(0x00002258)
164#define GFXGAM3 __REG_2700G(0x0000225c)
165#define GFXGAM4 __REG_2700G(0x00002260)
166#define GFXGAM5 __REG_2700G(0x00002264)
167#define GFXGAM6 __REG_2700G(0x00002268)
168#define GFXGAM7 __REG_2700G(0x0000226c)
169#define GFXGAM8 __REG_2700G(0x00002270)
170#define GFXGAM9 __REG_2700G(0x00002274)
171#define GFXGAM10 __REG_2700G(0x00002278)
172#define GFXGAM11 __REG_2700G(0x0000227c)
173#define GFXGAM12 __REG_2700G(0x00002280)
174#define GFXGAM13 __REG_2700G(0x00002284)
175#define GFXGAM14 __REG_2700G(0x00002288)
176#define GFXGAM15 __REG_2700G(0x0000228c)
177#define GFXGAM16 __REG_2700G(0x00002290)
178
179#define DLSTS __REG_2700G(0x00002300)
180#define DLLCTRL __REG_2700G(0x00002304)
181#define DVLNUM __REG_2700G(0x00002308)
182#define DUCTRL __REG_2700G(0x0000230c)
183#define DVECTRL __REG_2700G(0x00002310)
184#define DHDET __REG_2700G(0x00002314)
185#define DVDET __REG_2700G(0x00002318)
186#define DODMSK __REG_2700G(0x0000231c)
187#define CSC01 __REG_2700G(0x00002330)
188#define CSC02 __REG_2700G(0x00002334)
189#define CSC03 __REG_2700G(0x00002338)
190#define CSC04 __REG_2700G(0x0000233c)
191#define CSC05 __REG_2700G(0x00002340)
192
193#define FB_MEMORY_START __REG_2700G(0x00060000)
194
195#endif /* __REGS_2700G_ */